From: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
To: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Subject: Re: [PATCH] dt-bindings: arm,gic-v3: require that reserved cells are always 0
Date: Wed, 3 Feb 2016 18:20:54 +0000 [thread overview]
Message-ID: <20160203182054.GH1234@leverpostej> (raw)
In-Reply-To: <1454522458-29643-1-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org>
On Wed, Feb 03, 2016 at 06:00:58PM +0000, Will Deacon wrote:
> The arm,gic-v3 binding was written with good intentions and doesn't
> enforce interrupt-cells to be 3, therefore making it easy to extend
> the irq description in future if necessary:
>
> > Cells 4 and beyond are reserved for future use.
>
> Unfortunately, this sentence is immediately followed up with:
>
> > When the 1st cell has a value of 0 or 1, cells 4 and beyond act as
> > padding, and may be ignored. It is recommended that padding cells
> > have a value of 0.
The initial intention of this was to allow for new, longer entries which
were identified by a new value in cell 1.
Regardless, I agree that it should be a requirement that padding cells
must be zero.
> Consequently, any extensions to the PPI or SPI interrupt specifiers must
> be able to work with random crap from legacy DTs, effectively
> necessitating a new interrupt type in the first cell. Sigh.
I'm not sure that's true if we allocate a new value for the 1st cell for
"extended" PPI or SPI interrupt-sepcficiers (which presumably add
restrictions). That would also allow old kernels to safely skip such
interrupts rather than mis-parsing them.
> This patch fixes the text so that additional, reserved cells are
> required to be zero. This looks like a reasonable thing to require and
> is already satisifed by the .dts files in-tree.
>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
> Signed-off-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
This patch itself makes sense, so FWIW:
Acked-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Any proposed extention to the binding requires its own discussion.
Thanks,
Mark.
> ---
> .../devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
> index 7803e77d85cb..007a5b46256a 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
> @@ -24,9 +24,8 @@ Main node required properties:
> 1 = edge triggered
> 4 = level triggered
>
> - Cells 4 and beyond are reserved for future use. When the 1st cell
> - has a value of 0 or 1, cells 4 and beyond act as padding, and may be
> - ignored. It is recommended that padding cells have a value of 0.
> + Cells 4 and beyond are reserved for future use and must have a value
> + of 0 if present.
>
> - reg : Specifies base physical address(s) and size of the GIC
> registers, in the following order:
> --
> 2.1.4
>
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next prev parent reply other threads:[~2016-02-03 18:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-03 18:00 [PATCH] dt-bindings: arm,gic-v3: require that reserved cells are always 0 Will Deacon
[not found] ` <1454522458-29643-1-git-send-email-will.deacon-5wv7dgnIgG8@public.gmane.org>
2016-02-03 18:15 ` Marc Zyngier
2016-02-03 18:20 ` Mark Rutland [this message]
2016-02-03 18:40 ` Will Deacon
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