Re: [PATCH V8 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver.

[Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>]

On Monday, February 08, 2016 at 12:19:25 PM, Vignesh R wrote:
> On 02/06/2016 01:12 PM, Marek Vasut wrote:
> > On Thursday, February 04, 2016 at 06:30:27 PM, R, Vignesh wrote:
> >> On 2/4/2016 4:55 PM, Marek Vasut wrote:
> [...]
> 
> >> Yeah, there is delay(of few ns) required between writing to
> >> INDIRECTWR_START bit and actually writing data to flash(i.e writesl()
> >> call). This is specific to TI K2G SoC and needs to be tied to the new
> >> binding.
> > 
> > Can't you somehow poll the hardware to check whether or not it's ready
> > instead of adding some random delay ?
> 
> There is no dedicated register to poll as such.
> 
> According to TRM:
> "Wait for couple of cycles of QSPI_REF_CLK(functional clock of QSPI
> @384MHz) until CQSPI_REG_INDIRECTWR[0] bit is internally synchronized by
> the QSPI module before writing to flash".
> 
> So, a few ns(~6ns @384MHz) delay is needed (or accessing a QSPI module
> register should be sufficient as it will take more than 2 clock cycles).
> I believe this delay is specific to TI K2G SoC and maybe needs to be
> tied to the binding.

OK, got it. Dinh/Graham, can you check if this might be needed on SoCFPGA too 
please?

Best regards,
Marek Vasut
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