[RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Antony Pavlov]

This driver can be easely upgraded for other Atheros
SoCs (e.g. AR724X/AR913X) support.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Alban Bedel <albeu@free.fr>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
---
 drivers/clk/Makefile                  |   1 +
 drivers/clk/clk-ath79.c               | 354 ++++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/ath79-clk.h |  22 +++
 3 files changed, 377 insertions(+)

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b038e36..d7ad50e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -18,6 +18,7 @@ endif
 # hardware specific clock types
 # please keep this section sorted lexicographically by file/directory path name
 obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
+obj-$(CONFIG_ATH79)			+= clk-ath79.o
 obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
 obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
 obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
new file mode 100644
index 0000000..e899d31
--- /dev/null
+++ b/drivers/clk/clk-ath79.c
@@ -0,0 +1,354 @@
+/*
+ * Clock driver for Atheros AR933X SoCs
+ *
+ * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This driver is based on Ingenic CGU linux driver by Paul Burton
+ * and AR9331 barebox driver by Antony Pavlov.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/ath79-clk.h>
+
+#include "asm/mach-ath79/ar71xx_regs.h"
+
+struct ath79_pll_info {
+	u32 div_shift;
+	u32 div_mask;
+};
+
+struct ath79_cblk;
+
+/**
+ * struct ath79_clk_info - information about a clock
+ * @name: name of the clock
+ * @type: a bitmask formed from ATH79_CLK_* values
+ * @parents: an index of parent of this clock
+ *           within the clock_info array, or -1
+ *           which correspond to no valid parent
+ * @pll: information valid if type includes ATH79_CLK_PLL
+ */
+struct ath79_clk_info {
+	const char *name;
+
+	enum {
+		ATH79_CLK_NONE		= 0,
+		ATH79_CLK_EXT		= 1,
+		ATH79_CLK_PLL		= 2,
+		ATH79_CLK_ALIAS		= 3,
+	} type;
+
+	struct ath79_cblk *cblk;
+	int parent;
+
+	struct ath79_pll_info pll;
+};
+
+struct ath79_cblk {
+	struct device_node *np;
+	void __iomem *base;
+
+	const struct ath79_clk_info *clock_info;
+	struct clk_onecell_data clocks;
+};
+
+/**
+ * struct ath79_clk - private data for a clock
+ * @hw: see Documentation/clk.txt
+ * @cblk: a pointer to the cblk data
+ * @idx: the index of this clock cblk->clock_info
+ * @pll: information valid if type includes ATH79_CLK_PLL
+ */
+struct ath79_clk {
+	struct clk_hw hw;
+	struct ath79_cblk *cblk;
+	unsigned idx;
+};
+
+#define to_ath79_clk(_hw) container_of(_hw, struct ath79_clk, hw)
+
+static const struct ath79_clk_info ar9331_clocks[] = {
+
+	/* External clock */
+	[ATH79_CLK_REF] = { "ref", ATH79_CLK_EXT },
+
+	[ATH79_CLK_CPU] = {
+		"cpu", ATH79_CLK_PLL,
+		.parent = ATH79_CLK_REF,
+		.pll = {
+			.div_shift = AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
+			.div_mask = AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK,
+		},
+	},
+
+	[ATH79_CLK_DDR] = {
+		"ddr", ATH79_CLK_PLL,
+		.parent = ATH79_CLK_REF,
+		.pll = {
+			.div_shift = AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
+			.div_mask = AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK,
+		},
+	},
+
+	[ATH79_CLK_AHB] = {
+		"ahb", ATH79_CLK_PLL,
+		.parent = ATH79_CLK_REF,
+		.pll = {
+			.div_shift = AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
+			.div_mask = AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK,
+		},
+	},
+
+	[ATH79_CLK_WDT] = {
+		"wdt", ATH79_CLK_ALIAS,
+		.parent = ATH79_CLK_AHB,
+	},
+
+	[ATH79_CLK_UART] = {
+		"uart", ATH79_CLK_ALIAS,
+		.parent = ATH79_CLK_REF,
+	},
+};
+
+struct ath79_cblk *
+ath79_cblk_new(const struct ath79_clk_info *clock_info,
+		unsigned num_clocks, struct device_node *np)
+{
+	struct ath79_cblk *cblk;
+
+	cblk = kzalloc(sizeof(*cblk), GFP_KERNEL);
+	if (!cblk)
+		goto err_out;
+
+	cblk->base = of_iomap(np, 0);
+	if (!cblk->base) {
+		pr_err("%s: failed to map clock block registers\n", __func__);
+		goto err_out_free;
+	}
+
+	cblk->np = np;
+	cblk->clock_info = clock_info;
+	cblk->clocks.clk_num = num_clocks;
+
+	return cblk;
+
+err_out_free:
+	kfree(cblk);
+
+err_out:
+	return NULL;
+}
+
+static unsigned long
+ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
+	struct ath79_cblk *cblk = ath79_clk->cblk;
+	const struct ath79_clk_info *clk_info = &cblk->clock_info[ath79_clk->idx];
+	const struct ath79_pll_info *pll_info;
+	unsigned long rate;
+	unsigned long freq;
+	u32 clock_ctrl;
+	u32 cpu_config;
+	u32 t;
+
+	BUG_ON(clk_info->type != ATH79_CLK_PLL);
+
+	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
+
+	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+		return parent_rate;
+	}
+
+	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
+
+	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+	freq = parent_rate / t;
+
+	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
+	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
+	freq *= t;
+
+	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+	if (t == 0)
+		t = 1;
+
+	freq >>= t;
+
+	pll_info = &clk_info->pll;
+
+	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
+	rate = freq / t;
+
+	return rate;
+}
+
+static const struct clk_ops ath79_pll_clk_ops = {
+	.recalc_rate = ath79_pll_recalc_rate,
+};
+
+static int ath79_register_clock(struct ath79_cblk *cblk, unsigned idx)
+{
+	const struct ath79_clk_info *clk_info = &cblk->clock_info[idx];
+	const struct ath79_clk_info *parent_clk_info;
+	struct clk_init_data clk_init;
+	struct ath79_clk *ath79_clk = NULL;
+	struct clk *clk;
+	int err = -EINVAL;
+
+	if (clk_info->type == ATH79_CLK_EXT) {
+		clk = of_clk_get_by_name(cblk->np, clk_info->name);
+		if (IS_ERR(clk)) {
+			pr_err("%s: no external clock '%s' provided\n",
+			       __func__, clk_info->name);
+			err = -ENODEV;
+			goto out;
+		}
+
+		err = clk_register_clkdev(clk, clk_info->name, NULL);
+		if (err) {
+			clk_put(clk);
+			goto out;
+		}
+
+		cblk->clocks.clks[idx] = clk;
+
+		return 0;
+	}
+
+	parent_clk_info = &cblk->clock_info[clk_info->parent];
+
+	if (clk_info->type == ATH79_CLK_ALIAS) {
+		clk = clk_register_fixed_factor(NULL, clk_info->name,
+						parent_clk_info->name, 0, 1, 1);
+		if (IS_ERR(clk)) {
+			pr_err("%s: failed to register clock '%s'\n", __func__,
+			       clk_info->name);
+			err = PTR_ERR(clk);
+			goto out;
+		}
+
+		cblk->clocks.clks[idx] = clk;
+
+		return 0;
+	}
+
+	if (!clk_info->type) {
+		pr_err("%s: no clock type specified for '%s'\n", __func__,
+		       clk_info->name);
+		goto out;
+	}
+
+	ath79_clk = kzalloc(sizeof(*ath79_clk), GFP_KERNEL);
+	if (!ath79_clk) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	ath79_clk->hw.init = &clk_init;
+	ath79_clk->cblk = cblk;
+	ath79_clk->idx = idx;
+
+	clk_init.name = clk_info->name;
+	clk_init.flags = 0;
+	clk_init.parent_names = &parent_clk_info->name;
+	clk_init.num_parents = 1;
+
+	if (clk_info->type == ATH79_CLK_PLL) {
+		clk_init.ops = &ath79_pll_clk_ops;
+	}
+
+	clk = clk_register(NULL, &ath79_clk->hw);
+	if (IS_ERR(clk)) {
+		pr_err("%s: failed to register clock '%s'\n", __func__,
+		       clk_info->name);
+		err = PTR_ERR(clk);
+		goto out;
+	}
+
+	err = clk_register_clkdev(clk, clk_info->name, NULL);
+	if (err)
+		goto out;
+
+	cblk->clocks.clks[idx] = clk;
+out:
+	if (err)
+		kfree(ath79_clk);
+
+	return err;
+}
+
+static int ath79_cblk_register_clocks(struct ath79_cblk *cblk)
+{
+	unsigned i;
+	int err;
+
+	cblk->clocks.clks = kcalloc(cblk->clocks.clk_num, sizeof(struct clk *),
+				   GFP_KERNEL);
+	if (!cblk->clocks.clks) {
+		err = -ENOMEM;
+		goto err_out;
+	}
+
+	for (i = 0; i < cblk->clocks.clk_num; i++) {
+		err = ath79_register_clock(cblk, i);
+		if (err)
+			goto err_out_unregister;
+	}
+
+	err = of_clk_add_provider(cblk->np, of_clk_src_onecell_get,
+				  &cblk->clocks);
+	if (err)
+		goto err_out_unregister;
+
+	return 0;
+
+err_out_unregister:
+	for (i = 0; i < cblk->clocks.clk_num; i++) {
+		if (!cblk->clocks.clks[i])
+			continue;
+		if (cblk->clock_info[i].type == ATH79_CLK_EXT)
+			clk_put(cblk->clocks.clks[i]);
+		else
+			clk_unregister(cblk->clocks.clks[i]);
+	}
+
+	kfree(cblk->clocks.clks);
+
+err_out:
+	return err;
+}
+
+static void __init ar9130_init(struct device_node *np)
+{
+	int retval;
+	struct ath79_cblk *cblk;
+
+	cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
+	if (!cblk) {
+		pr_err("%s: failed to initialise clk block\n", __func__);
+		return;
+	}
+
+	retval = ath79_cblk_register_clocks(cblk);
+	if (retval)
+		pr_err("%s: failed to register clocks\n", __func__);
+}
+CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);
diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
new file mode 100644
index 0000000..1c6fb04
--- /dev/null
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_ATH79_CLK_H
+#define __DT_BINDINGS_ATH79_CLK_H
+
+#define ATH79_CLK_REF		0
+#define ATH79_CLK_CPU		1
+#define ATH79_CLK_DDR		2
+#define ATH79_CLK_AHB		3
+#define ATH79_CLK_WDT		4
+#define ATH79_CLK_UART		5
+
+#define ATH79_CLK_END		6
+
+#endif /* __DT_BINDINGS_ATH79_CLK_H */
-- 
2.7.0

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:47 AM, Antony Pavlov wrote:
> This driver can be easely upgraded for other Atheros
> SoCs (e.g. AR724X/AR913X) support.
> 

Hi!

[...]

> +static unsigned long
> +ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> +	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
> +	struct ath79_cblk *cblk = ath79_clk->cblk;
> +	const struct ath79_clk_info *clk_info =
> &cblk->clock_info[ath79_clk->idx]; +	const struct ath79_pll_info
> *pll_info;
> +	unsigned long rate;
> +	unsigned long freq;
> +	u32 clock_ctrl;
> +	u32 cpu_config;
> +	u32 t;
> +
> +	BUG_ON(clk_info->type != ATH79_CLK_PLL);
> +
> +	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
> +
> +	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
> +		return parent_rate;
> +	}

You can drop the {} here.

> +	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
> +	freq = parent_rate / t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
> +	freq *= t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
> +	if (t == 0)
> +		t = 1;
> +
> +	freq >>= t;
> +
> +	pll_info = &clk_info->pll;
> +
> +	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
> +	rate = freq / t;
> +
> +	return rate;
> +}

[...]

> +static void __init ar9130_init(struct device_node *np)
> +{
> +	int retval;
> +	struct ath79_cblk *cblk;
> +
> +	cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
> +	if (!cblk) {
> +		pr_err("%s: failed to initialise clk block\n", __func__);
> +		return;
> +	}
> +
> +	retval = ath79_cblk_register_clocks(cblk);
> +	if (retval)
> +		pr_err("%s: failed to register clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);

Is that ar9130_init name correct? Shouldn't it be ar9330_init ?

Looks good otherwise, thanks!

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Alban]

On Tue,  9 Feb 2016 11:13:47 +0300
Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> This driver can be easely upgraded for other Atheros
> SoCs (e.g. AR724X/AR913X) support.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Cc: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
> Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  drivers/clk/Makefile                  |   1 +
>  drivers/clk/clk-ath79.c               | 354 ++++++++++++++++++++++++++++++++++
>  include/dt-bindings/clock/ath79-clk.h |  22 +++
>  3 files changed, 377 insertions(+)
> 
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index b038e36..d7ad50e 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -18,6 +18,7 @@ endif
>  # hardware specific clock types
>  # please keep this section sorted lexicographically by file/directory path name
>  obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
> +obj-$(CONFIG_ATH79)			+= clk-ath79.o
>  obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
>  obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
>  obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
> diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
> new file mode 100644
> index 0000000..e899d31
> --- /dev/null
> +++ b/drivers/clk/clk-ath79.c
> @@ -0,0 +1,354 @@
> +/*
> + * Clock driver for Atheros AR933X SoCs
> + *
> + * Copyright (C) 2016 Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This driver is based on Ingenic CGU linux driver by Paul Burton
> + * and AR9331 barebox driver by Antony Pavlov.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +
> +#include <dt-bindings/clock/ath79-clk.h>
> +
> +#include "asm/mach-ath79/ar71xx_regs.h"

This header shouldn't be used in new code, just defines the few
registers needed here. Not using this header allow the driver
to be built in compile test which increase test coverage.

> +struct ath79_pll_info {
> +	u32 div_shift;
> +	u32 div_mask;
> +};
> +
> +struct ath79_cblk;
> +
> +/**
> + * struct ath79_clk_info - information about a clock
> + * @name: name of the clock
> + * @type: a bitmask formed from ATH79_CLK_* values
> + * @parents: an index of parent of this clock
> + *           within the clock_info array, or -1
> + *           which correspond to no valid parent
> + * @pll: information valid if type includes ATH79_CLK_PLL
> + */
> +struct ath79_clk_info {
> +	const char *name;
> +
> +	enum {
> +		ATH79_CLK_NONE		= 0,
> +		ATH79_CLK_EXT		= 1,
> +		ATH79_CLK_PLL		= 2,
> +		ATH79_CLK_ALIAS		= 3,
> +	} type;
> +
> +	struct ath79_cblk *cblk;
> +	int parent;
> +
> +	struct ath79_pll_info pll;
> +};
> +
> +struct ath79_cblk {
> +	struct device_node *np;
> +	void __iomem *base;
> +
> +	const struct ath79_clk_info *clock_info;
> +	struct clk_onecell_data clocks;
> +};
> +
> +/**
> + * struct ath79_clk - private data for a clock
> + * @hw: see Documentation/clk.txt
> + * @cblk: a pointer to the cblk data
> + * @idx: the index of this clock cblk->clock_info
> + * @pll: information valid if type includes ATH79_CLK_PLL
> + */
> +struct ath79_clk {
> +	struct clk_hw hw;
> +	struct ath79_cblk *cblk;
> +	unsigned idx;
> +};
> +
> +#define to_ath79_clk(_hw) container_of(_hw, struct ath79_clk, hw)
> +
> +static const struct ath79_clk_info ar9331_clocks[] = {
> +
> +	/* External clock */
> +	[ATH79_CLK_REF] = { "ref", ATH79_CLK_EXT },
> +
> +	[ATH79_CLK_CPU] = {
> +		"cpu", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_DDR] = {
> +		"ddr", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_AHB] = {
> +		"ahb", ATH79_CLK_PLL,
> +		.parent = ATH79_CLK_REF,
> +		.pll = {
> +			.div_shift = AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
> +			.div_mask = AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK,
> +		},
> +	},
> +
> +	[ATH79_CLK_WDT] = {
> +		"wdt", ATH79_CLK_ALIAS,
> +		.parent = ATH79_CLK_AHB,
> +	},
> +
> +	[ATH79_CLK_UART] = {
> +		"uart", ATH79_CLK_ALIAS,
> +		.parent = ATH79_CLK_REF,
> +	},
> +};
> +
> +struct ath79_cblk *
> +ath79_cblk_new(const struct ath79_clk_info *clock_info,
> +		unsigned num_clocks, struct device_node *np)
> +{
> +	struct ath79_cblk *cblk;
> +
> +	cblk = kzalloc(sizeof(*cblk), GFP_KERNEL);
> +	if (!cblk)
> +		goto err_out;
> +
> +	cblk->base = of_iomap(np, 0);
> +	if (!cblk->base) {
> +		pr_err("%s: failed to map clock block registers\n", __func__);
> +		goto err_out_free;
> +	}
> +
> +	cblk->np = np;
> +	cblk->clock_info = clock_info;
> +	cblk->clocks.clk_num = num_clocks;
> +
> +	return cblk;
> +
> +err_out_free:
> +	kfree(cblk);
> +
> +err_out:
> +	return NULL;
> +}
> +
> +static unsigned long
> +ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> +	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
> +	struct ath79_cblk *cblk = ath79_clk->cblk;
> +	const struct ath79_clk_info *clk_info = &cblk->clock_info[ath79_clk->idx];
> +	const struct ath79_pll_info *pll_info;
> +	unsigned long rate;
> +	unsigned long freq;
> +	u32 clock_ctrl;
> +	u32 cpu_config;
> +	u32 t;
> +
> +	BUG_ON(clk_info->type != ATH79_CLK_PLL);

It's probably debatable if such a BUG_ON() is really needed.

> +	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
> +
> +	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
> +		return parent_rate;
> +	}

Those brace should goes away.

> +	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
> +	freq = parent_rate / t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
> +	freq *= t;
> +
> +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
> +	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
> +	if (t == 0)
> +		t = 1;
> +
> +	freq >>= t;
> +
> +	pll_info = &clk_info->pll;
> +
> +	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
> +	rate = freq / t;

If we just compute a fixed rate we could as well use
clk_register_fixed_factor() and drop 80% of the code of this driver.

> +	return rate;
> +}
> +
> +static const struct clk_ops ath79_pll_clk_ops = {
> +	.recalc_rate = ath79_pll_recalc_rate,
> +};
> +
> +static int ath79_register_clock(struct ath79_cblk *cblk, unsigned idx)
> +{
> +	const struct ath79_clk_info *clk_info = &cblk->clock_info[idx];
> +	const struct ath79_clk_info *parent_clk_info;
> +	struct clk_init_data clk_init;
> +	struct ath79_clk *ath79_clk = NULL;
> +	struct clk *clk;
> +	int err = -EINVAL;
> +
> +	if (clk_info->type == ATH79_CLK_EXT) {
> +		clk = of_clk_get_by_name(cblk->np, clk_info->name);
> +		if (IS_ERR(clk)) {
> +			pr_err("%s: no external clock '%s' provided\n",
> +			       __func__, clk_info->name);
> +			err = -ENODEV;
> +			goto out;
> +		}
> +
> +		err = clk_register_clkdev(clk, clk_info->name, NULL);
> +		if (err) {
> +			clk_put(clk);
> +			goto out;
> +		}

clk_register_clkdev() and naming providers is not needed on OF
platforms. This should only be used on legacy platforms.

> +		cblk->clocks.clks[idx] = clk;
> +
> +		return 0;
> +	}
> +
> +	parent_clk_info = &cblk->clock_info[clk_info->parent];
> +
> +	if (clk_info->type == ATH79_CLK_ALIAS) {
> +		clk = clk_register_fixed_factor(NULL, clk_info->name,
> +						parent_clk_info->name, 0, 1, 1);
> +		if (IS_ERR(clk)) {
> +			pr_err("%s: failed to register clock '%s'\n", __func__,
> +			       clk_info->name);
> +			err = PTR_ERR(clk);
> +			goto out;
> +		}
> +
> +		cblk->clocks.clks[idx] = clk;
> +
> +		return 0;
> +	}

I really don't get why you keep insisting on having those useless alias
clocks. Alias are only needed on legacy platforms to form connections
between clock providers and consumers. On OF platforms these
connections are nicely represented in the DT, so it is just not
needed at all.

> +	if (!clk_info->type) {
> +		pr_err("%s: no clock type specified for '%s'\n", __func__,
> +		       clk_info->name);
> +		goto out;
> +	}
> +
> +	ath79_clk = kzalloc(sizeof(*ath79_clk), GFP_KERNEL);
> +	if (!ath79_clk) {
> +		err = -ENOMEM;
> +		goto out;
> +	}
> +
> +	ath79_clk->hw.init = &clk_init;
> +	ath79_clk->cblk = cblk;
> +	ath79_clk->idx = idx;
> +
> +	clk_init.name = clk_info->name;
> +	clk_init.flags = 0;
> +	clk_init.parent_names = &parent_clk_info->name;
> +	clk_init.num_parents = 1;
> +
> +	if (clk_info->type == ATH79_CLK_PLL) {
> +		clk_init.ops = &ath79_pll_clk_ops;
> +	}
> +
> +	clk = clk_register(NULL, &ath79_clk->hw);
> +	if (IS_ERR(clk)) {
> +		pr_err("%s: failed to register clock '%s'\n", __func__,
> +		       clk_info->name);
> +		err = PTR_ERR(clk);
> +		goto out;
> +	}
> +
> +	err = clk_register_clkdev(clk, clk_info->name, NULL);
> +	if (err)
> +		goto out;

clk_register_clkdev() shouldn't be needed here either.

> +	cblk->clocks.clks[idx] = clk;
> +out:
> +	if (err)
> +		kfree(ath79_clk);
> +
> +	return err;
> +}
> +
> +static int ath79_cblk_register_clocks(struct ath79_cblk *cblk)
> +{
> +	unsigned i;
> +	int err;
> +
> +	cblk->clocks.clks = kcalloc(cblk->clocks.clk_num, sizeof(struct clk *),
> +				   GFP_KERNEL);
> +	if (!cblk->clocks.clks) {
> +		err = -ENOMEM;
> +		goto err_out;
> +	}
> +
> +	for (i = 0; i < cblk->clocks.clk_num; i++) {
> +		err = ath79_register_clock(cblk, i);
> +		if (err)
> +			goto err_out_unregister;
> +	}
> +
> +	err = of_clk_add_provider(cblk->np, of_clk_src_onecell_get,
> +				  &cblk->clocks);
> +	if (err)
> +		goto err_out_unregister;
> +
> +	return 0;
> +
> +err_out_unregister:
> +	for (i = 0; i < cblk->clocks.clk_num; i++) {
> +		if (!cblk->clocks.clks[i])
> +			continue;
> +		if (cblk->clock_info[i].type == ATH79_CLK_EXT)
> +			clk_put(cblk->clocks.clks[i]);
> +		else
> +			clk_unregister(cblk->clocks.clks[i]);
> +	}
> +
> +	kfree(cblk->clocks.clks);
> +
> +err_out:
> +	return err;
> +}
> +
> +static void __init ar9130_init(struct device_node *np)
> +{
> +	int retval;
> +	struct ath79_cblk *cblk;
> +
> +	cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
> +	if (!cblk) {
> +		pr_err("%s: failed to initialise clk block\n", __func__);
> +		return;
> +	}
> +
> +	retval = ath79_cblk_register_clocks(cblk);
> +	if (retval)
> +		pr_err("%s: failed to register clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);
> diff --git a/include/dt-bindings/clock/ath79-clk.h b/include/dt-bindings/clock/ath79-clk.h
> new file mode 100644
> index 0000000..1c6fb04
> --- /dev/null
> +++ b/include/dt-bindings/clock/ath79-clk.h
> @@ -0,0 +1,22 @@
> +/*
> + * Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_ATH79_CLK_H
> +#define __DT_BINDINGS_ATH79_CLK_H
> +
> +#define ATH79_CLK_REF		0
> +#define ATH79_CLK_CPU		1
> +#define ATH79_CLK_DDR		2
> +#define ATH79_CLK_AHB		3
> +#define ATH79_CLK_WDT		4
> +#define ATH79_CLK_UART		5
> +
> +#define ATH79_CLK_END		6
> +
> +#endif /* __DT_BINDINGS_ATH79_CLK_H */

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Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Antony Pavlov]

On Tue, 9 Feb 2016 22:51:34 +0100
Alban <albeu@free.fr> wrote:

> On Tue,  9 Feb 2016 11:13:47 +0300
> Antony Pavlov <antonynpavlov@gmail.com> wrote:
> 
> > This driver can be easely upgraded for other Atheros
> > SoCs (e.g. AR724X/AR913X) support.
> > 
> > Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
> > Cc: Alban Bedel <albeu@free.fr>
> > Cc: Michael Turquette <mturquette@baylibre.com>
> > Cc: Stephen Boyd <sboyd@codeaurora.org>
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Paul Burton <paul.burton@imgtec.com>
> > Cc: linux-clk@vger.kernel.org
> > Cc: linux-mips@linux-mips.org
> > Cc: devicetree@vger.kernel.org
> > ---
> >  drivers/clk/Makefile                  |   1 +
> >  drivers/clk/clk-ath79.c               | 354 ++++++++++++++++++++++++++++++++++
> >  include/dt-bindings/clock/ath79-clk.h |  22 +++
> >  3 files changed, 377 insertions(+)
> > 
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index b038e36..d7ad50e 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -18,6 +18,7 @@ endif
> >  # hardware specific clock types
> >  # please keep this section sorted lexicographically by file/directory path name
> >  obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
> > +obj-$(CONFIG_ATH79)			+= clk-ath79.o
> >  obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
> >  obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
> >  obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o
> > diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
> > new file mode 100644
> > index 0000000..e899d31
> > --- /dev/null
> > +++ b/drivers/clk/clk-ath79.c
> > @@ -0,0 +1,354 @@
> > +/*
> > + * Clock driver for Atheros AR933X SoCs
> > + *
> > + * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com>
> > + *
> > + * This driver is based on Ingenic CGU linux driver by Paul Burton
> > + * and AR9331 barebox driver by Antony Pavlov.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/clkdev.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +
> > +#include <dt-bindings/clock/ath79-clk.h>
> > +
> > +#include "asm/mach-ath79/ar71xx_regs.h"
> 
> This header shouldn't be used in new code, just defines the few
> registers needed here. Not using this header allow the driver
> to be built in compile test which increase test coverage.

ok.

> > +struct ath79_pll_info {
> > +	u32 div_shift;
> > +	u32 div_mask;
> > +};
> > +
> > +struct ath79_cblk;
> > +
> > +/**
> > + * struct ath79_clk_info - information about a clock
> > + * @name: name of the clock
> > + * @type: a bitmask formed from ATH79_CLK_* values
> > + * @parents: an index of parent of this clock
> > + *           within the clock_info array, or -1
> > + *           which correspond to no valid parent
> > + * @pll: information valid if type includes ATH79_CLK_PLL
> > + */
> > +struct ath79_clk_info {
> > +	const char *name;
> > +
> > +	enum {
> > +		ATH79_CLK_NONE		= 0,
> > +		ATH79_CLK_EXT		= 1,
> > +		ATH79_CLK_PLL		= 2,
> > +		ATH79_CLK_ALIAS		= 3,
> > +	} type;
> > +
> > +	struct ath79_cblk *cblk;
> > +	int parent;
> > +
> > +	struct ath79_pll_info pll;
> > +};
> > +
> > +struct ath79_cblk {
> > +	struct device_node *np;
> > +	void __iomem *base;
> > +
> > +	const struct ath79_clk_info *clock_info;
> > +	struct clk_onecell_data clocks;
> > +};
> > +
> > +/**
> > + * struct ath79_clk - private data for a clock
> > + * @hw: see Documentation/clk.txt
> > + * @cblk: a pointer to the cblk data
> > + * @idx: the index of this clock cblk->clock_info
> > + * @pll: information valid if type includes ATH79_CLK_PLL
> > + */
> > +struct ath79_clk {
> > +	struct clk_hw hw;
> > +	struct ath79_cblk *cblk;
> > +	unsigned idx;
> > +};
> > +
> > +#define to_ath79_clk(_hw) container_of(_hw, struct ath79_clk, hw)
> > +
> > +static const struct ath79_clk_info ar9331_clocks[] = {
> > +
> > +	/* External clock */
> > +	[ATH79_CLK_REF] = { "ref", ATH79_CLK_EXT },
> > +
> > +	[ATH79_CLK_CPU] = {
> > +		"cpu", ATH79_CLK_PLL,
> > +		.parent = ATH79_CLK_REF,
> > +		.pll = {
> > +			.div_shift = AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT,
> > +			.div_mask = AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_DDR] = {
> > +		"ddr", ATH79_CLK_PLL,
> > +		.parent = ATH79_CLK_REF,
> > +		.pll = {
> > +			.div_shift = AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT,
> > +			.div_mask = AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_AHB] = {
> > +		"ahb", ATH79_CLK_PLL,
> > +		.parent = ATH79_CLK_REF,
> > +		.pll = {
> > +			.div_shift = AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT,
> > +			.div_mask = AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK,
> > +		},
> > +	},
> > +
> > +	[ATH79_CLK_WDT] = {
> > +		"wdt", ATH79_CLK_ALIAS,
> > +		.parent = ATH79_CLK_AHB,
> > +	},
> > +
> > +	[ATH79_CLK_UART] = {
> > +		"uart", ATH79_CLK_ALIAS,
> > +		.parent = ATH79_CLK_REF,
> > +	},
> > +};
> > +
> > +struct ath79_cblk *
> > +ath79_cblk_new(const struct ath79_clk_info *clock_info,
> > +		unsigned num_clocks, struct device_node *np)
> > +{
> > +	struct ath79_cblk *cblk;
> > +
> > +	cblk = kzalloc(sizeof(*cblk), GFP_KERNEL);
> > +	if (!cblk)
> > +		goto err_out;
> > +
> > +	cblk->base = of_iomap(np, 0);
> > +	if (!cblk->base) {
> > +		pr_err("%s: failed to map clock block registers\n", __func__);
> > +		goto err_out_free;
> > +	}
> > +
> > +	cblk->np = np;
> > +	cblk->clock_info = clock_info;
> > +	cblk->clocks.clk_num = num_clocks;
> > +
> > +	return cblk;
> > +
> > +err_out_free:
> > +	kfree(cblk);
> > +
> > +err_out:
> > +	return NULL;
> > +}
> > +
> > +static unsigned long
> > +ath79_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> > +{
> > +	struct ath79_clk *ath79_clk = to_ath79_clk(hw);
> > +	struct ath79_cblk *cblk = ath79_clk->cblk;
> > +	const struct ath79_clk_info *clk_info = &cblk->clock_info[ath79_clk->idx];
> > +	const struct ath79_pll_info *pll_info;
> > +	unsigned long rate;
> > +	unsigned long freq;
> > +	u32 clock_ctrl;
> > +	u32 cpu_config;
> > +	u32 t;
> > +
> > +	BUG_ON(clk_info->type != ATH79_CLK_PLL);
> 
> It's probably debatable if such a BUG_ON() is really needed.

In simple RFC v5 driver version this check is redundant.
I suppose it's reasonable for more advanced version of the driver.
 
> > +	clock_ctrl = __raw_readl(cblk->base + AR933X_PLL_CLOCK_CTRL_REG);
> > +
> > +	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
> > +		return parent_rate;
> > +	}
> 
> Those brace should goes away.

Ok.

> > +	cpu_config = __raw_readl(cblk->base + AR933X_PLL_CPU_CONFIG_REG);
> > +
> > +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
> > +	freq = parent_rate / t;
> > +
> > +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_NINT_MASK;
> > +	freq *= t;
> > +
> > +	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
> > +	    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
> > +	if (t == 0)
> > +		t = 1;
> > +
> > +	freq >>= t;
> > +
> > +	pll_info = &clk_info->pll;
> > +
> > +	t = ((clock_ctrl >> pll_info->div_shift) & pll_info->div_mask) + 1;
> > +	rate = freq / t;
> 
> If we just compute a fixed rate we could as well use
> clk_register_fixed_factor() and drop 80% of the code of this driver.

80% is an overstatement.

> > +	return rate;
> > +}
> > +
> > +static const struct clk_ops ath79_pll_clk_ops = {
> > +	.recalc_rate = ath79_pll_recalc_rate,
> > +};
> > +
> > +static int ath79_register_clock(struct ath79_cblk *cblk, unsigned idx)
> > +{
> > +	const struct ath79_clk_info *clk_info = &cblk->clock_info[idx];
> > +	const struct ath79_clk_info *parent_clk_info;
> > +	struct clk_init_data clk_init;
> > +	struct ath79_clk *ath79_clk = NULL;
> > +	struct clk *clk;
> > +	int err = -EINVAL;
> > +
> > +	if (clk_info->type == ATH79_CLK_EXT) {
> > +		clk = of_clk_get_by_name(cblk->np, clk_info->name);
> > +		if (IS_ERR(clk)) {
> > +			pr_err("%s: no external clock '%s' provided\n",
> > +			       __func__, clk_info->name);
> > +			err = -ENODEV;
> > +			goto out;
> > +		}
> > +
> > +		err = clk_register_clkdev(clk, clk_info->name, NULL);
> > +		if (err) {
> > +			clk_put(clk);
> > +			goto out;
> > +		}
> 
> clk_register_clkdev() and naming providers is not needed on OF
> platforms. This should only be used on legacy platforms.

I can't drop these clk_register_clkdev() just now without patching legacy code.

If I just drop clk_register_clkdev() then I get

    Kernel panic - not syncing: unable to get cpu clock, err=-2

on start.


> > +		cblk->clocks.clks[idx] = clk;
> > +
> > +		return 0;
> > +	}
> > +
> > +	parent_clk_info = &cblk->clock_info[clk_info->parent];
> > +
> > +	if (clk_info->type == ATH79_CLK_ALIAS) {
> > +		clk = clk_register_fixed_factor(NULL, clk_info->name,
> > +						parent_clk_info->name, 0, 1, 1);
> > +		if (IS_ERR(clk)) {
> > +			pr_err("%s: failed to register clock '%s'\n", __func__,
> > +			       clk_info->name);
> > +			err = PTR_ERR(clk);
> > +			goto out;
> > +		}
> > +
> > +		cblk->clocks.clks[idx] = clk;
> > +
> > +		return 0;
> > +	}
> 
> I really don't get why you keep insisting on having those useless alias
> clocks. Alias are only needed on legacy platforms to form connections
> between clock providers and consumers. On OF platforms these
> connections are nicely represented in the DT, so it is just not
> needed at all.

I have droppped these aliases in RFC v6 series.

-- 
Best regards,
  Antony Pavlov

Re: [RFC v5 01/15] WIP: clk: add Atheros AR933X SoCs clock driver

[Michael Turquette]

Quoting Antony Pavlov (2016-02-09 00:13:47)
> +static void __init ar9130_init(struct device_node *np)
> +{
> +       int retval;
> +       struct ath79_cblk *cblk;
> +
> +       cblk = ath79_cblk_new(ar9331_clocks, ARRAY_SIZE(ar9331_clocks), np);
> +       if (!cblk) {
> +               pr_err("%s: failed to initialise clk block\n", __func__);
> +               return;
> +       }
> +
> +       retval = ath79_cblk_register_clocks(cblk);
> +       if (retval)
> +               pr_err("%s: failed to register clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(ar933x_clk, "qca,ar9330-pll", ar9130_init);

Is there any reason this isn't a platform_driver?

Thanks,
Mike

[RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Antony Pavlov]

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
index e0fc2c1..ae99f22 100644
--- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
+++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
 
 Required Properties:
-- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
+- compatible: has to be "qca,<soctype>-pll" and one of the following
   fallbacks:
   - "qca,ar7100-pll"
   - "qca,ar7240-pll"
@@ -21,7 +21,7 @@ Optional properties:
 
 Example:
 
-	memory-controller@18050000 {
+	pll-controller@18050000 {
 		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
 		reg = <0x18050000 0x20>;
 
-- 
2.7.0

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Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:48 AM, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

Acked-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>

Best regards,
Marek Vasut
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Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Alban]

On Tue,  9 Feb 2016 11:13:48 +0300
Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> index e0fc2c1..ae99f22 100644
> --- a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> +++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
> @@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
>  The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
>  
>  Required Properties:
> -- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
> +- compatible: has to be "qca,<soctype>-pll" and one of the following
>    fallbacks:
>    - "qca,ar7100-pll"
>    - "qca,ar7240-pll"
> @@ -21,7 +21,7 @@ Optional properties:
>  
>  Example:
>  
> -	memory-controller@18050000 {
> +	pll-controller@18050000 {
>  		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
>  		reg = <0x18050000 0x20>;
>  

Acked-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>

Alban
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Re: [RFC v5 02/15] dt-bindings: clock: qca,ath79-pll: fix copy-paste typos

[Rob Herring]

On Tue, Feb 09, 2016 at 11:13:48AM +0300, Antony Pavlov wrote:
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  Documentation/devicetree/bindings/clock/qca,ath79-pll.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[RFC v5 05/15] MIPS: dts: qca: introduce AR9331 devicetree

[Antony Pavlov]

This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
typically used in very cheap Access Points and Routers.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/ar9331.dtsi | 157 +++++++++++++++++++++++++++++++++++++
 1 file changed, 157 insertions(+)

diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi
new file mode 100644
index 0000000..333c7ff
--- /dev/null
+++ b/arch/mips/boot/dts/qca/ar9331.dtsi
@@ -0,0 +1,157 @@
+#include <dt-bindings/clock/ath79-clk.h>
+
+/ {
+	compatible = "qca,ar9331";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "mips,mips24Kc";
+			reg = <0>;
+		};
+	};
+
+	cpuintc: interrupt-controller {
+		compatible = "qca,ar7100-cpu-intc";
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		qca,ddr-wb-channel-interrupts = <2>, <3>;
+		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;
+	};
+
+	ref: ref {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		ranges;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+
+		apb {
+			compatible = "simple-bus";
+			ranges;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			interrupt-parent = <&miscintc>;
+
+			ddr_ctrl: memory-controller@18000000 {
+				compatible = "qca,ar7240-ddr-controller";
+				reg = <0x18000000 0x100>;
+
+				#qca,ddr-wb-channel-cells = <1>;
+			};
+
+			uart: uart@18020000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18020000 0x14>;
+
+				interrupts = <3>;
+
+				clocks = <&pll ATH79_CLK_UART>;
+				clock-names = "uart";
+
+				status = "disabled";
+			};
+
+			gpio: gpio@18040000 {
+				compatible = "qca,ar7100-gpio";
+				reg = <0x18040000 0x34>;
+				interrupts = <2>;
+
+				ngpios = <30>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				status = "disabled";
+			};
+
+			pll: pll-controller@18050000 {
+				compatible = "qca,ar9330-pll";
+				reg = <0x18050000 0x100>;
+
+				clocks = <&ref>;
+				clock-names = "ref";
+
+				#clock-cells = <1>;
+			};
+
+			miscintc: interrupt-controller@18060010 {
+				compatible = "qca,ar7240-misc-intc";
+				reg = <0x18060010 0x4>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <6>;
+
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			rst: reset-controller@1806001c {
+				compatible = "qca,ar7100-reset";
+				reg = <0x1806001c 0x4>;
+
+				#reset-cells = <1>;
+			};
+
+			usb: usb@1b000100 {
+				compatible = "qca,ar7100-ehci", "generic-ehci";
+				reg = <0x1b000100 0x100>;
+
+				interrupt-parent = <&cpuintc>;
+				interrupts = <3>;
+				resets = <&rst 5>;
+
+				has-transaction-translator;
+
+				phy-names = "usb";
+				phys = <&usb_phy>;
+
+				status = "disabled";
+			};
+
+			spi: spi@1f000000 {
+				compatible = "qca,ar7100-spi";
+				reg = <0x1f000000 0x10>;
+
+				clocks = <&pll ATH79_CLK_AHB>;
+				clock-names = "ahb";
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+	};
+
+	usb_phy: usb-phy {
+		compatible = "qca,ar7100-usb-phy";
+
+		reset-names = "usb-phy", "usb-suspend-override";
+		resets = <&rst 4>, <&rst 3>;
+
+		#phy-cells = <0>;
+
+		status = "disabled";
+	};
+};
-- 
2.7.0

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Re: [RFC v5 05/15] MIPS: dts: qca: introduce AR9331 devicetree

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:51 AM, Antony Pavlov wrote:
> This patch introduces devicetree for Atheros AR9331 SoC (AKA Hornet).
> The AR9331 chip is a Wi-Fi System-On-Chip (WiSOC),
> typically used in very cheap Access Points and Routers.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---

[...]

> +			usb: usb@1b000100 {
> +				compatible = "qca,ar7100-ehci", "generic-ehci";
> +				reg = <0x1b000100 0x100>;

It's actually chipidea HDRC , you should bind that driver with it instead.
See for example this:
http://patchwork.linux-mips.org/patch/4968/

> +				interrupt-parent = <&cpuintc>;
> +				interrupts = <3>;
> +				resets = <&rst 5>;
> +
> +				has-transaction-translator;
> +
> +				phy-names = "usb";
> +				phys = <&usb_phy>;
> +
> +				status = "disabled";
> +			};

[...]

Best regards,
Marek Vasut
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[RFC v5 06/15] MIPS: ath79: add initial support for TP-LINK MR3020

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * GPIO keys and LEDs.

Links:

  * http://www.tp-link.com/en/products/details/?model=TL-MR3020
  * http://wiki.openwrt.org/toh/tp-link/tl-mr3020
  * https://wikidevi.com/wiki/TP-LINK_TL-MR3020

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/Makefile      |  1 +
 arch/mips/boot/dts/qca/tl_mr3020.dts | 99 ++++++++++++++++++++++++++++++++++++
 2 files changed, 100 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index 14bd225..504c4b1 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
 obj-				+= dummy.o
diff --git a/arch/mips/boot/dts/qca/tl_mr3020.dts b/arch/mips/boot/dts/qca/tl_mr3020.dts
new file mode 100644
index 0000000..2a1b296
--- /dev/null
+++ b/arch/mips/boot/dts/qca/tl_mr3020.dts
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "TP-Link TL-MR3020";
+	compatible = "tplink,tl-mr3020";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "tp-link:green:wlan";
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		lan {
+			label = "tp-link:green:lan";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		wps {
+			label = "tp-link:green:wps";
+			gpios = <&gpio 26 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		led3g {
+			label = "tp-link:green:3g";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+		};
+
+		button@1 {
+			label = "sw1";
+			linux,code = <BTN_0>;
+			gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+		};
+
+		button@2 {
+			label = "sw2";
+			linux,code = <BTN_1>;
+			gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Spansion S25FL032PIF SPI flash */
+	spiflash: s25sl032p@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,s25sl032p", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

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Re: [RFC v5 06/15] MIPS: ath79: add initial support for TP-LINK MR3020

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:52 AM, Antony Pavlov wrote:
> The following features are supported:
> 
>   * UART;
>   * SPI-flash;
>   * GPIO keys and LEDs.
> 
> Links:
> 
>   * http://www.tp-link.com/en/products/details/?model=TL-MR3020
>   * http://wiki.openwrt.org/toh/tp-link/tl-mr3020
>   * https://wikidevi.com/wiki/TP-LINK_TL-MR3020
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  arch/mips/boot/dts/qca/Makefile      |  1 +
>  arch/mips/boot/dts/qca/tl_mr3020.dts | 99
> ++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/qca/Makefile
> b/arch/mips/boot/dts/qca/Makefile index 14bd225..504c4b1 100644
> --- a/arch/mips/boot/dts/qca/Makefile
> +++ b/arch/mips/boot/dts/qca/Makefile
> @@ -1,5 +1,6 @@
>  # All DTBs
>  dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
> +dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb

You might want to stay consistent and call it ar9331_tl_mr3020.dtb .

[...]

Best regards,
Marek Vasut
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[RFC v5 09/15] devicetree: add Dragino vendor id

[Antony Pavlov]

Please see http://www.dragino.com/about/about.html for details.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 72e2c5a..49d07bf 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -68,6 +68,7 @@ digilent	Diglent, Inc.
 dlg	Dialog Semiconductor
 dlink	D-Link Corporation
 dmo	Data Modul AG
+dragino	Dragino Technology Co., Limited
 ea	Embedded Artists AB
 ebv	EBV Elektronik
 edt	Emerging Display Technologies
-- 
2.7.0

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[RFC v5 10/15] MIPS: ath79: add initial support for Dragino MS14 (Dragino 2)

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Links:

    * http://www.dragino.com/products/mother-board/item/71-ms14-p.html
    * https://wiki.openwrt.org/toh/dragino/ms14

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/Makefile         |   1 +
 arch/mips/boot/dts/qca/dragino_ms14.dts | 101 ++++++++++++++++++++++++++++++++
 2 files changed, 102 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index 504c4b1..e949cff 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
diff --git a/arch/mips/boot/dts/qca/dragino_ms14.dts b/arch/mips/boot/dts/qca/dragino_ms14.dts
new file mode 100644
index 0000000..44abb77
--- /dev/null
+++ b/arch/mips/boot/dts/qca/dragino_ms14.dts
@@ -0,0 +1,101 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "Dragino MS14 (Dragino 2)";
+	compatible = "dragino,ms14";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wlan {
+			label = "dragino2:red:wlan";
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		lan {
+			label = "dragino2:red:lan";
+			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		wan {
+			label = "dragino2:red:wan";
+			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+
+		system {
+			label = "dragino2:red:system";
+			gpios = <&gpio 28 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "jumpstart";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		button@1 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128BVFG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

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Re: [RFC v5 10/15] MIPS: ath79: add initial support for Dragino MS14 (Dragino 2)

[Marek Vasut]

On Tuesday, February 09, 2016 at 09:13:56 AM, Antony Pavlov wrote:
> The following features are supported:
> 
>   * UART;
>   * SPI-flash;
>   * USB host;
>   * GPIO keys and LEDs.
> 
> Links:
> 
>     * http://www.dragino.com/products/mother-board/item/71-ms14-p.html
>     * https://wiki.openwrt.org/toh/dragino/ms14
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  arch/mips/boot/dts/qca/Makefile         |   1 +
>  arch/mips/boot/dts/qca/dragino_ms14.dts | 101
> ++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/qca/Makefile
> b/arch/mips/boot/dts/qca/Makefile index 504c4b1..e949cff 100644
> --- a/arch/mips/boot/dts/qca/Makefile
> +++ b/arch/mips/boot/dts/qca/Makefile
> @@ -1,5 +1,6 @@
>  # All DTBs
>  dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
> +dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb

ar9331_dragino_ms14.dtb ?

>  dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
> 

You should re-order the board additions at the end of the patchset, so you
can then squash the USB DT patch for the mr3020 board into it.

Best regards,
Marek Vasut
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[RFC v5 11/15] devicetree: add Onion Corporation vendor id

[Antony Pavlov]

Please see https://onion.io/contact for details.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 49d07bf..afb96f7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -166,6 +166,7 @@ nvidia	NVIDIA
 nxp	NXP Semiconductors
 okaya	Okaya Electric America, Inc.
 olimex	OLIMEX Ltd.
+onion	Onion Corporation
 onnn	ON Semiconductor Corp.
 opencores	OpenCores.org
 option	Option NV
-- 
2.7.0

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[RFC v5 12/15] MIPS: ath79: add initial support for Onion Omega

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Please see https://onion.io/omega for details.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Gabor Juhos <juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
Cc: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
Cc: L. D. Pinney <ldpinney-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Boken Lin <bl-Jj7zZGp/71Y@public.gmane.org>
Cc: Jacky Huang <huangfangcheng-9Onoh4P/yGk@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/Makefile  |  1 +
 arch/mips/boot/dts/qca/omega.dts | 77 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index e949cff..ca2ecb8 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,6 +1,7 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
 dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
+dtb-$(CONFIG_ATH79)			+= omega.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
 
 # Force kbuild to make empty built-in.o if necessary
diff --git a/arch/mips/boot/dts/qca/omega.dts b/arch/mips/boot/dts/qca/omega.dts
new file mode 100644
index 0000000..f4a7ed0
--- /dev/null
+++ b/arch/mips/boot/dts/qca/omega.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "Onion Omega";
+	compatible = "onion,omega";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system {
+			label = "onion:amber:system";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128FVSG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

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[RFC v5 13/15] devicetree: add DPTechnics vendor id

[Antony Pavlov]

Please see https://www.dptechnics.com/contact for details.

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Daan Pape <daan-xfAQRCeQ3RHuufBYgWm87A@public.gmane.org>
Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index afb96f7..8cb96f2 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -68,6 +68,7 @@ digilent	Diglent, Inc.
 dlg	Dialog Semiconductor
 dlink	D-Link Corporation
 dmo	Data Modul AG
+dptechnics	DPTechnics
 dragino	Dragino Technology Co., Limited
 ea	Embedded Artists AB
 ebv	EBV Elektronik
-- 
2.7.0

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Re: [RFC v5 13/15] devicetree: add DPTechnics vendor id

[Rob Herring]

On Tue, Feb 09, 2016 at 11:13:59AM +0300, Antony Pavlov wrote:
> Please see https://www.dptechnics.com/contact for details.
> 
> Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Daan Pape <daan-xfAQRCeQ3RHuufBYgWm87A@public.gmane.org>
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[RFC v5 14/15] MIPS: ath79: add DPT-Module support

[Antony Pavlov]

The following features are supported:

  * UART;
  * SPI-flash;
  * USB host;
  * GPIO keys and LEDs.

Links:

  * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=50
  * https://dptechnics.com/shop/index.php?route=product/product&path=59&product_id=63

Signed-off-by: Antony Pavlov <antonynpavlov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Daan Pape <daan-xfAQRCeQ3RHuufBYgWm87A@public.gmane.org>
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/qca/Makefile       |  1 +
 arch/mips/boot/dts/qca/dpt_module.dts | 77 +++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile
index ca2ecb8..7d4bf43 100644
--- a/arch/mips/boot/dts/qca/Makefile
+++ b/arch/mips/boot/dts/qca/Makefile
@@ -1,5 +1,6 @@
 # All DTBs
 dtb-$(CONFIG_ATH79)			+= ar9132_tl_wr1043nd_v1.dtb
+dtb-$(CONFIG_ATH79)			+= dpt_module.dtb
 dtb-$(CONFIG_ATH79)			+= dragino_ms14.dtb
 dtb-$(CONFIG_ATH79)			+= omega.dtb
 dtb-$(CONFIG_ATH79)			+= tl_mr3020.dtb
diff --git a/arch/mips/boot/dts/qca/dpt_module.dts b/arch/mips/boot/dts/qca/dpt_module.dts
new file mode 100644
index 0000000..f4ccb74
--- /dev/null
+++ b/arch/mips/boot/dts/qca/dpt_module.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9331.dtsi"
+
+/ {
+	model = "DPTechnics DPT-Module";
+	compatible = "dptechnics,dpt-module";
+
+	aliases {
+		serial0 = &uart;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x4000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		system {
+			label = "dpt-module:green:system";
+			gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+			default-state = "off";
+		};
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <100>;
+
+		button@0 {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&ref {
+	clock-frequency = <25000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&spi {
+	num-chipselects = <1>;
+	status = "okay";
+
+	/* Winbond 25Q128FVSG SPI flash */
+	spiflash: w25q128@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "winbond,w25q128", "jedec,spi-nor";
+		spi-max-frequency = <104000000>;
+		reg = <0>;
+	};
+};
-- 
2.7.0

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