[PATCH] ARM: dts: DRA7: change address-cells and size-cells

[PATCH] ARM: dts: DRA7: change address-cells and size-cells

[Lokesh Vutla]

DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
represent this in memory dt node, the address-cells and size cells
should be 2. So, changing the address-cells and size-cells to 2 and
updating the memory nodes accordingly.

Signed-off-by: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>
---
 arch/arm/boot/dts/am57xx-beagle-x15.dts   |  2 +-
 arch/arm/boot/dts/am57xx-cl-som-am57x.dts |  2 +-
 arch/arm/boot/dts/dra7-evm.dts            |  2 +-
 arch/arm/boot/dts/dra7.dtsi               | 20 ++++++++++----------
 arch/arm/boot/dts/dra72-evm.dts           |  2 +-
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 50312f8..9b664c5 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -24,7 +24,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x80000000>;
+		reg = <0x0 0x80000000 0x0 0x80000000>;
 	};
 
 	vdd_3v3: fixedregulator-vdd_3v3 {
diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
index c538826..e6c40db 100644
--- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts
@@ -21,7 +21,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x20000000>; /* 512 MB - minimal configuration */
+		reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
 	};
 
 	leds {
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index cfc24e5..2d1d3dd 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -18,7 +18,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x60000000>; /* 1536 MB */
+		reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
 	};
 
 	evm_3v3_sd: fixedregulator-sd {
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8ea153a..5460a2a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -15,8 +15,8 @@
 #define MAX_SOURCES 400
 
 / {
-	#address-cells = <1>;
-	#size-cells = <1>;
+	#address-cells = <2>;
+	#size-cells = <2>;
 
 	compatible = "ti,dra7xx";
 	interrupt-parent = <&crossbar_mpu>;
@@ -57,10 +57,10 @@
 		compatible = "arm,cortex-a15-gic";
 		interrupt-controller;
 		#interrupt-cells = <3>;
-		reg = <0x48211000 0x1000>,
-		      <0x48212000 0x1000>,
-		      <0x48214000 0x2000>,
-		      <0x48216000 0x2000>;
+		reg = <0x0 0x48211000 0x0 0x1000>,
+		      <0x0 0x48212000 0x0 0x1000>,
+		      <0x0 0x48214000 0x0 0x2000>,
+		      <0x0 0x48216000 0x0 0x2000>;
 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		interrupt-parent = <&gic>;
 	};
@@ -69,7 +69,7 @@
 		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 		interrupt-controller;
 		#interrupt-cells = <3>;
-		reg = <0x48281000 0x1000>;
+		reg = <0x0 0x48281000 0x0 0x1000>;
 		interrupt-parent = <&gic>;
 	};
 
@@ -96,10 +96,10 @@
 		compatible = "ti,dra7-l3-noc", "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges;
+		ranges = <0x0 0x0 0x0 0xc0000000>;
 		ti,hwmods = "l3_main_1", "l3_main_2";
-		reg = <0x44000000 0x1000000>,
-		      <0x45000000 0x1000>;
+		reg = <0x0 0x44000000 0x0 0x1000000>,
+		      <0x0 0x45000000 0x0 0x1000>;
 		interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 				      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 00b1200..6a5b0c8 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -17,7 +17,7 @@
 
 	memory {
 		device_type = "memory";
-		reg = <0x80000000 0x40000000>; /* 1024 MB */
+		reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
 	};
 
 	aliases {
-- 
2.1.4

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Re: [PATCH] ARM: dts: DRA7: change address-cells and size-cells

[Tony Lindgren]

* Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org> [160224 02:14]:
> DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
> represent this in memory dt node, the address-cells and size cells
> should be 2. So, changing the address-cells and size-cells to 2 and
> updating the memory nodes accordingly.
> @@ -57,10 +57,10 @@
>  		compatible = "arm,cortex-a15-gic";
>  		interrupt-controller;
>  		#interrupt-cells = <3>;
> -		reg = <0x48211000 0x1000>,
> -		      <0x48212000 0x1000>,
> -		      <0x48214000 0x2000>,
> -		      <0x48216000 0x2000>;
> +		reg = <0x0 0x48211000 0x0 0x1000>,
> +		      <0x0 0x48212000 0x0 0x1000>,
> +		      <0x0 0x48214000 0x0 0x2000>,
> +		      <0x0 0x48216000 0x0 0x2000>;
>  		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>  		interrupt-parent = <&gic>;
>  	};
> @@ -69,7 +69,7 @@
>  		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
>  		interrupt-controller;
>  		#interrupt-cells = <3>;
> -		reg = <0x48281000 0x1000>;
> +		reg = <0x0 0x48281000 0x0 0x1000>;
>  		interrupt-parent = <&gic>;
>  	};
>  
> @@ -96,10 +96,10 @@
>  		compatible = "ti,dra7-l3-noc", "simple-bus";
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> -		ranges;
> +		ranges = <0x0 0x0 0x0 0xc0000000>;
>  		ti,hwmods = "l3_main_1", "l3_main_2";
> -		reg = <0x44000000 0x1000000>,
> -		      <0x45000000 0x1000>;
> +		reg = <0x0 0x44000000 0x0 0x1000000>,
> +		      <0x0 0x45000000 0x0 0x1000>;
>  		interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>  				      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>  

Is size-cells 2 needed for all these devices too? Can't
you just set it for the memory nodes?

Regards,

Tony
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Re: [PATCH] ARM: dts: DRA7: change address-cells and size-cells

[Lokesh Vutla]

Hi Tony,

On Saturday 27 February 2016 12:41 AM, Tony Lindgren wrote:
> * Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org> [160224 02:14]:
>> DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
>> represent this in memory dt node, the address-cells and size cells
>> should be 2. So, changing the address-cells and size-cells to 2 and
>> updating the memory nodes accordingly.
>> @@ -57,10 +57,10 @@
>>  		compatible = "arm,cortex-a15-gic";
>>  		interrupt-controller;
>>  		#interrupt-cells = <3>;
>> -		reg = <0x48211000 0x1000>,
>> -		      <0x48212000 0x1000>,
>> -		      <0x48214000 0x2000>,
>> -		      <0x48216000 0x2000>;
>> +		reg = <0x0 0x48211000 0x0 0x1000>,
>> +		      <0x0 0x48212000 0x0 0x1000>,
>> +		      <0x0 0x48214000 0x0 0x2000>,
>> +		      <0x0 0x48216000 0x0 0x2000>;
>>  		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>>  		interrupt-parent = <&gic>;
>>  	};
>> @@ -69,7 +69,7 @@
>>  		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
>>  		interrupt-controller;
>>  		#interrupt-cells = <3>;
>> -		reg = <0x48281000 0x1000>;
>> +		reg = <0x0 0x48281000 0x0 0x1000>;
>>  		interrupt-parent = <&gic>;
>>  	};
>>  
>> @@ -96,10 +96,10 @@
>>  		compatible = "ti,dra7-l3-noc", "simple-bus";
>>  		#address-cells = <1>;
>>  		#size-cells = <1>;
>> -		ranges;
>> +		ranges = <0x0 0x0 0x0 0xc0000000>;
>>  		ti,hwmods = "l3_main_1", "l3_main_2";
>> -		reg = <0x44000000 0x1000000>,
>> -		      <0x45000000 0x1000>;
>> +		reg = <0x0 0x44000000 0x0 0x1000000>,
>> +		      <0x0 0x45000000 0x0 0x1000>;
>>  		interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>>  				      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>>  
> 
> Is size-cells 2 needed for all these devices too? Can't
> you just set it for the memory nodes?

For updating memory nodes with 64bit, I have to change the address and
size cells as 2 for the root node. So, reg property in all the children
to the root node should also be updated with 2 address cells and 2 size
cells or else the below warning shows up:

Warning (reg_format): "reg" property in /interrupt-controller@48281000
has invalid length (8 bytes) (#address-cells == 2, #size-cells == 2)
Warning (ranges_format): /ocp has empty "ranges" property but its
#address-cells (1) differs from / (2)
Warning (ranges_format): /ocp has empty "ranges" property but its
#size-cells (1) differs from / (2)

This is why I am updating all the children to the root node.

Thanks and regards,
Lokesh
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Re: [PATCH] ARM: dts: DRA7: change address-cells and size-cells

[Tony Lindgren]

* Lokesh Vutla <a0131933-l0cyMroinI0@public.gmane.org> [160229 00:48]:
> On Saturday 27 February 2016 12:41 AM, Tony Lindgren wrote:
> > * Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org> [160224 02:14]:
> > 
> > Is size-cells 2 needed for all these devices too? Can't
> > you just set it for the memory nodes?
> 
> For updating memory nodes with 64bit, I have to change the address and
> size cells as 2 for the root node. So, reg property in all the children
> to the root node should also be updated with 2 address cells and 2 size
> cells or else the below warning shows up:

Yes I understand that if we need to set it at the top level. But what
happens if you only set it for the memory node?

With just something like:

memory {
       #address-cells = <2>;
       #size-cells = <2>;
       ...
};

Regards,

Tony

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Re: [PATCH] ARM: dts: DRA7: change address-cells and size-cells

[Arnd Bergmann]

On Monday 29 February 2016 10:16:07 Tony Lindgren wrote:
> Yes I understand that if we need to set it at the top level. But what
> happens if you only set it for the memory node?
> 
> With just something like:
> 
> memory {
>        #address-cells = <2>;
>        #size-cells = <2>;
>        ...
> };

Nothing happens there: the memory node has no children, and no
ranges property, so the two properties are never referenced.

	Arnd
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Re: [PATCH] ARM: dts: DRA7: change address-cells and size-cells

[Tony Lindgren]

* Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> [160229 12:46]:
> On Monday 29 February 2016 10:16:07 Tony Lindgren wrote:
> > Yes I understand that if we need to set it at the top level. But what
> > happens if you only set it for the memory node?
> > 
> > With just something like:
> > 
> > memory {
> >        #address-cells = <2>;
> >        #size-cells = <2>;
> >        ...
> > };
> 
> Nothing happens there: the memory node has no children, and no
> ranges property, so the two properties are never referenced.

OK thanks.

Tony
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Re: [PATCH] ARM: dts: DRA7: change address-cells and size-cells

[Tony Lindgren]

* Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org> [160224 02:14]:
> DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
> represent this in memory dt node, the address-cells and size cells
> should be 2. So, changing the address-cells and size-cells to 2 and
> updating the memory nodes accordingly.

Applying into omap-for-v4.6/dt thanks.

Tony
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