From: Borislav Petkov <bp@alien8.de>
To: tthayer@opensource.altera.com
Cc: dougthompson@xmission.com, m.chehab@samsung.com,
robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
linux@arm.linux.org.uk, dinguyen@opensource.altera.com,
grant.likely@linaro.org, devicetree@vger.kernel.org,
linux-doc@vger.kernel.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, tthayer.linux@gmail.com
Subject: Re: [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry
Date: Tue, 29 Mar 2016 10:45:49 +0200 [thread overview]
Message-ID: <20160329084549.GC3705@pd.tnic> (raw)
In-Reply-To: <1458576106-24505-10-git-send-email-tthayer@opensource.altera.com>
On Mon, Mar 21, 2016 at 11:01:46AM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
>
> Add the device tree entries needed to support the Altera L2
> cache EDAC on the Arria10 chip.
>
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> v2 Match register value (l2-ecc@ffd06010)
> v3 Set ecc_manager to beginning of system_manager. Add sysman
> phandle. Move IRQs into ecc_manager from children.
> ---
> arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index cce9e50..345ea97 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -599,6 +599,21 @@
> reg = <0xffe00000 0x40000>;
> };
>
> + eccmgr: eccmgr@ffd06000 {
> + compatible = "altr,socfpga-a10-ecc-manager";
> + altr,sysmgr-syscon = <&sysmgr>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 IRQ_TYPE_LEVEL_HIGH>;
> + ranges;
> +
> + l2-ecc@ffd06010 {
> + compatible = "altr,socfpga-a10-l2-ecc";
> + reg = <0xffd06010 0x4>;
> + };
> + };
> +
> rst: rstmgr@ffd05000 {
> #reset-cells = <1>;
> compatible = "altr,rst-mgr";
> --
I've picked up all except this one: need an ACK for it too. Dinh, DT-people?
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
next prev parent reply other threads:[~2016-03-29 8:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-21 16:01 Series adding Arria10 L2 Cache EDAC tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
2016-03-21 16:01 ` [PATCHv3 1/9] EDAC: Altera L2 Kconfig change from select to depends upon tthayer
2016-03-21 16:01 ` [PATCHv3 2/9] EDAC, altera: Move Device structs and defines to header file tthayer
2016-03-21 16:01 ` [PATCHv3 3/9] EDAC, altera: Remove platform device from check_deps() tthayer
2016-03-21 16:01 ` [PATCHv3 4/9] EDAC, altera: Abstract ECC Enable Mask in check_deps() tthayer
2016-03-21 16:01 ` [PATCHv3 5/9] EDAC, altera: Add register offset for ECC Error Inject tthayer
2016-03-21 16:01 ` [PATCHv3 6/9] Documentation: dt: socfpga: Add Altera Arria10 L2 cache binding tthayer
2016-03-23 14:24 ` Rob Herring
2016-03-21 16:01 ` [PATCHv3 7/9] EDAC, altera: Addition of Arria10 L2 Cache ECC tthayer
2016-03-21 16:01 ` [PATCHv3 8/9] ARM: socfpga: Enable Arria10 L2 cache ECC on startup tthayer
2016-03-21 16:01 ` [PATCHv3 9/9] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry tthayer
2016-03-29 8:45 ` Borislav Petkov [this message]
2016-03-29 12:15 ` Dinh Nguyen
2016-03-29 14:00 ` Borislav Petkov
2016-03-29 15:48 ` Dinh Nguyen
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