From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v3 4/9] drm/fsl-dcu: add extra clock for pixel clock Date: Thu, 7 Apr 2016 12:57:40 -0500 Message-ID: <20160407175740.GJ32257@rob-hp-laptop> References: <1459834121-25997-1-git-send-email-stefan@agner.ch> <1459834121-25997-5-git-send-email-stefan@agner.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1459834121-25997-5-git-send-email-stefan@agner.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Stefan Agner Cc: meng.yi@nxp.com, pawel.moll@arm.com, alison.wang@freescale.com, daniel.vetter@ffwll.ch, mturquette@baylibre.com, ijc+devicetree@hellion.org.uk, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, kernel@pengutronix.de, galak@codeaurora.org, mark.rutland@arm.com, shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org, alexander.stein@systec-electronic.com List-Id: devicetree@vger.kernel.org T24gTW9uLCBBcHIgMDQsIDIwMTYgYXQgMTA6Mjg6MzZQTSAtMDcwMCwgU3RlZmFuIEFnbmVyIHdy b3RlOgo+IFRoZSBWeWJyaWQgRENVIHZhcmlhbnQgaGFzIHR3byBpbmRlcGVuZGVudCBjbG9jayBp bnB1dHMsIG9uZQo+IGZvciB0aGUgcmVnaXN0ZXJzIChJUEcgYnVzIGNsb2NrKSBhbmQgb25lIGZv ciB0aGUgcGl4ZWwgY2xvY2suCj4gU3VwcG9ydCB0aGlzIGRpc3RpbmN0aW9uIGluIHRoZSBEQ1Ug RFJNIGRyaXZlciB3aGlsZSBzdGF5aW5nCj4gYmFja3dhcmQgY29tcGF0aWJsZSBmb3Igb2xkIGRl dmljZSB0cmVlcy4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBTdGVmYW4gQWduZXIgPHN0ZWZhbkBhZ25l ci5jaD4KPiAtLS0KPiAgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2Rpc3BsYXkv ZnNsLGRjdS50eHQgfCAxMSArKysrKysrLS0tLQoKQWNrZWQtYnk6IFJvYiBIZXJyaW5nIDxyb2Jo QGtlcm5lbC5vcmc+Cgo+ICBkcml2ZXJzL2dwdS9kcm0vZnNsLWRjdS9mc2xfZGN1X2RybV9jcnRj LmMgICAgICAgICAgICB8ICAyICstCj4gIGRyaXZlcnMvZ3B1L2RybS9mc2wtZGN1L2ZzbF9kY3Vf ZHJtX2Rydi5jICAgICAgICAgICAgIHwgMTYgKysrKysrKysrKysrKysrLQo+ICBkcml2ZXJzL2dw dS9kcm0vZnNsLWRjdS9mc2xfZGN1X2RybV9kcnYuaCAgICAgICAgICAgICB8ICAxICsKPiAgNCBm aWxlcyBjaGFuZ2VkLCAyNCBpbnNlcnRpb25zKCspLCA2IGRlbGV0aW9ucygtKQpfX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBs aXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVz a3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK