From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Rutland Subject: Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs Date: Thu, 21 Apr 2016 11:19:30 +0100 Message-ID: <20160421101930.GG6879@leverpostej> References: <1461122150-9042-1-git-send-email-jay.xu@rock-chips.com> <1461211092-26331-1-git-send-email-jay.xu@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1461211092-26331-1-git-send-email-jay.xu@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org To: Jianqun Xu , will.deacon@arm.com, marc.zyngier@arm.com Cc: robh+dt@kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, catalin.marinas@arm.com, heiko@sntech.de, huangtao@rock-chips.com, davidriley@chromium.org, dianders@chromium.org, jwerner@chromium.org, smbarber@chromium.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: devicetree@vger.kernel.org On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote: > + cpu_l0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + #cooling-cells = <2>; /* min followed by max */ > + clocks = <&cru ARMCLKL>; > + }; > + cpu_b0: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + #cooling-cells = <2>; /* min followed by max */ > + clocks = <&cru ARMCLKB>; > + }; > + > + arm-pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = ; > + }; This is wrong, and must go. There should be a separate node for the PMU of each microarchitecture, with the appropriate compatible string to represent that (see the juno dts). In this case things are messier as the same PPI number is being used across clusters. Marc (Cc'd) has been working on PPI partitions, which should allow us to support that. Thanks, Mark.