* [PATCH v2 02/12] of: add J-Core cpu bindings
2016-05-20 2:53 [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
[not found] ` <cover.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
@ 2016-05-20 2:53 ` Rich Felker
[not found] ` <f3c89e4834665790ff13478c571cc9aaa9de5559.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-20 2:53 ` [PATCH v2 03/12] of: add J-Core interrupt controller bindings Rich Felker
` (2 subsequent siblings)
4 siblings, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-20 2:53 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rob Herring
Signed-off-by: Rich Felker <dalias@libc.org>
---
Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
new file mode 100644
index 0000000..00ef112
--- /dev/null
+++ b/Documentation/devicetree/bindings/jcore/cpus.txt
@@ -0,0 +1,91 @@
+===================
+J-Core cpu bindings
+===================
+
+The J-Core processors are open source CPU cores that can be built as FPGA
+soft cores or ASICs. The device tree is also responsible for describing the
+cache controls and, for SMP configurations, all details of the SMP method,
+as documented below.
+
+
+---------------------
+Top-level "cpus" node
+---------------------
+
+Required properties:
+
+- #address-cells: Must be 1.
+
+- #size-cells: Must be 0.
+
+Optional properties:
+
+- enable-method: Required only for SMP systems. If present, must be
+ "jcore,spin-table".
+
+
+--------------------
+Individual cpu nodes
+--------------------
+
+Required properties:
+
+- device_type: Must be "cpu".
+
+- compatible: Must be "jcore,j2".
+
+- reg: Must be 0 on uniprocessor systems, or the sequential, zero-based
+ hardware cpu id on SMP systems.
+
+Optional properties:
+
+- clock-frequency: Clock frequency of the cpu in Hz.
+
+- cpu-release-addr: Necessary only for secondary processors on SMP systems
+ using the "jcore,spin-table" enable method. If present, must consist of
+ two cells containing physical addresses. The first cell contains an
+ address which, when written, unblocks the secondary cpu. The second cell
+ contains an address from which the cpu will read its initial program
+ counter when unblocked.
+
+
+---------------------
+Cache controller node
+---------------------
+
+Required properties:
+
+- compatible: Must be "jcore,cache".
+
+- reg: A memory range for the cache controller registers.
+
+
+--------
+IPI node
+--------
+
+Device trees for SMP systems must have an IPI node representing the mechanism
+used for inter-processor interrupt generation.
+
+Required properties:
+
+- compatible: Must be "jcore,ipi-controller".
+
+- reg: A memory range used to IPI generation.
+
+- interrupts: An irq on which IPI will be received.
+
+
+----------
+CPUID node
+----------
+
+Device trees for SMP systems must have a CPUID node representing the mechanism
+used to identify the current processor on which execution is taking place.
+
+Required properties:
+
+- compatible: Must be "jcore,cpuid-mmio".
+
+- reg: A memory range containing a single 32-bit mmio register which produces
+ the current cpu id when read.
--
2.8.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support
@ 2016-05-20 2:53 Rich Felker
[not found] ` <cover.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
` (4 more replies)
0 siblings, 5 replies; 31+ messages in thread
From: Rich Felker @ 2016-05-20 2:53 UTC (permalink / raw)
To: linux-kernel, linux-sh, devicetree
The following patchset adds support for the J-core J2, an open-source
VHDL reimplementation of the SH-2 ISA, and drivers for the associated
SoC devices (interrupt controller, clocksource, and SPI).
As arch/sh co-maintainer my intent is to have this merged for 4.7, but
I realized my previous post of the patch series omitted device tree
bindings and omitted Cc'ing of subsystem maintainers for the necessary
clocksource, irqchip, and spi drivers.
Rich Felker (12):
of: add vendor prefix for J-Core
of: add J-Core cpu bindings
of: add J-Core interrupt controller bindings
of: add J-Core timer bindings
of: add J-Core SPI master bindings
sh: add support for J-Core J2 processor
sh: add AT_HWCAP flag for J-Core cas.l instruction
irqchip: add J-Core AIC driver
clocksource: add J-Core PIT/RTC driver
spi: add driver for J-Core SPI controller
sh: add defconfig for J-Core J2
sh: add device tree source for J2 FPGA on Mimas v2 board
.../bindings/interrupt-controller/jcore,aic.txt | 28 +++
Documentation/devicetree/bindings/jcore/cpus.txt | 91 +++++++
.../devicetree/bindings/spi/jcore,spi.txt | 23 ++
.../devicetree/bindings/timer/jcore,pit.txt | 28 +++
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/sh/Kconfig | 8 +
arch/sh/Makefile | 1 +
arch/sh/boot/dts/j2_mimas_v2.dts | 87 +++++++
arch/sh/configs/j2_defconfig | 38 +++
arch/sh/include/asm/processor.h | 2 +-
arch/sh/include/uapi/asm/cpu-features.h | 1 +
arch/sh/kernel/cpu/init.c | 2 +-
arch/sh/kernel/cpu/proc.c | 1 +
arch/sh/kernel/cpu/sh2/entry.S | 5 +
arch/sh/kernel/cpu/sh2/probe.c | 36 ++-
arch/sh/mm/Makefile | 3 +-
arch/sh/mm/cache-j2.c | 58 +++++
arch/sh/mm/cache.c | 6 +-
drivers/clocksource/Kconfig | 9 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/jcore-pit.c | 176 ++++++++++++++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-jcore-aic.c | 95 ++++++++
drivers/spi/Kconfig | 4 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-jcore.c | 266 +++++++++++++++++++++
27 files changed, 973 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
create mode 100644 Documentation/devicetree/bindings/spi/jcore,spi.txt
create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
create mode 100755 arch/sh/boot/dts/j2_mimas_v2.dts
create mode 100644 arch/sh/configs/j2_defconfig
create mode 100644 arch/sh/mm/cache-j2.c
create mode 100644 drivers/clocksource/jcore-pit.c
create mode 100644 drivers/irqchip/irq-jcore-aic.c
create mode 100644 drivers/spi/spi-jcore.c
--
2.8.1
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2 01/12] of: add vendor prefix for J-Core
[not found] ` <cover.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
@ 2016-05-20 2:53 ` Rich Felker
2016-05-23 20:49 ` Rob Herring
2016-05-20 2:53 ` [PATCH v2 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board Rich Felker
1 sibling, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-20 2:53 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rob Herring
The J-Core project (j-core.org) produces open source cpu and SoC
peripheral cores synthesizable as FPGA bitstreams or ASICs.
Signed-off-by: Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 86740d4..9c070b8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -126,6 +126,7 @@ invensense InvenSense Inc.
isee ISEE 2007 S.L.
isil Intersil
issi Integrated Silicon Solutions Inc.
+jcore J-Core.org
jedec JEDEC Solid State Technology Association
karo Ka-Ro electronics GmbH
keymile Keymile GmbH
--
2.8.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 04/12] of: add J-Core timer bindings
2016-05-20 2:53 [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (3 preceding siblings ...)
2016-05-20 2:53 ` [PATCH v2 05/12] of: add J-Core SPI master bindings Rich Felker
@ 2016-05-20 2:53 ` Rich Felker
2016-05-20 8:03 ` Geert Uytterhoeven
4 siblings, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-20 2:53 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rob Herring
Signed-off-by: Rich Felker <dalias@libc.org>
---
.../devicetree/bindings/timer/jcore,pit.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
new file mode 100644
index 0000000..d53759a
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
@@ -0,0 +1,28 @@
+J-Core Programmable Interval Timer and Realtime Clock
+
+Required properties:
+
+- compatible: Must be "jcore,pit".
+
+- reg: Memory region for timer/rtc registers.
+
+- interrupts: An interrupt to assign for the timer. The actual pit
+ core is integrated with the aic and allows the timer interrupt
+ assignment to be programmed by software, but this property is
+ required in order to reserve an interrupt number that doesn't
+ conflict with other devices.
+
+Optional properties:
+
+- cpu-offset: For SMP, the per-cpu offset to the local timer
+ programming memory range.
+
+
+Example:
+
+timer {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 >;
+ cpu-offset = < 0x300 >;
+ interrupts = < 0x48 >;
+};
--
2.8.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 05/12] of: add J-Core SPI master bindings
2016-05-20 2:53 [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
` (2 preceding siblings ...)
2016-05-20 2:53 ` [PATCH v2 03/12] of: add J-Core interrupt controller bindings Rich Felker
@ 2016-05-20 2:53 ` Rich Felker
2016-05-20 8:05 ` Geert Uytterhoeven
2016-05-23 21:00 ` Rob Herring
2016-05-20 2:53 ` [PATCH v2 04/12] of: add J-Core timer bindings Rich Felker
4 siblings, 2 replies; 31+ messages in thread
From: Rich Felker @ 2016-05-20 2:53 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rob Herring
Signed-off-by: Rich Felker <dalias@libc.org>
---
.../devicetree/bindings/spi/jcore,spi.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/jcore,spi.txt
diff --git a/Documentation/devicetree/bindings/spi/jcore,spi.txt b/Documentation/devicetree/bindings/spi/jcore,spi.txt
new file mode 100644
index 0000000..9055e7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/jcore,spi.txt
@@ -0,0 +1,23 @@
+J-Core SPI master
+
+Required properties:
+
+- compatible: Must be "jcore,spi2".
+
+- reg: Memory region for registers.
+
+- #address-cells: Must be 1.
+
+- #size-cells: Must be 0.
+
+See spi-bus.txt for additional properties not specific to this device.
+
+Example:
+
+spi {
+ compatible = "jcore,spi2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = < 0x40 0x8 >;
+ spi-max-frequency = <12500000>;
+}
--
2.8.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board
[not found] ` <cover.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-20 2:53 ` [PATCH v2 01/12] of: add vendor prefix for J-Core Rich Felker
@ 2016-05-20 2:53 ` Rich Felker
[not found] ` <9960d6526523727d1bee3d11c6704e09e600c6fe.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
1 sibling, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-20 2:53 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sh-u79uwXL29TY76Z2rM5mHXA
Cc: Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll, Rich Felker,
Rob Herring, Yoshinori Sato
Signed-off-by: Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org>
---
arch/sh/boot/dts/j2_mimas_v2.dts | 87 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100755 arch/sh/boot/dts/j2_mimas_v2.dts
diff --git a/arch/sh/boot/dts/j2_mimas_v2.dts b/arch/sh/boot/dts/j2_mimas_v2.dts
new file mode 100755
index 0000000..f47fb2f
--- /dev/null
+++ b/arch/sh/boot/dts/j2_mimas_v2.dts
@@ -0,0 +1,87 @@
+/dts-v1/;
+
+/ {
+ compatible = "jcore,j2-soc";
+ model = "J2 FPGA SoC on Mimas v2 board";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&aic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "jcore,j2";
+ reg = < 0 >;
+ clock-frequency = < 50000000 >;
+ };
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = < 0x10000000 0x4000000 >;
+ };
+
+ chosen {
+ stdout-path = "/soc@abcd0000/serial@100";
+ };
+
+ soc@abcd0000 {
+ compatible = "simple-bus";
+ ranges = <0 0xabcd0000 0x100000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aic: interrupt-controller {
+ compatible = "jcore,aic1";
+ reg = < 0x200 0x10 >;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ cache-controller {
+ compatible = "jcore,cache";
+ reg = < 0xc0 4 >;
+ };
+
+ timer {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 >;
+ interrupts = < 0x48 >;
+ };
+
+ spi {
+ compatible = "jcore,spi2";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi-max-frequency = <12500000>;
+
+ reg = < 0x40 0x8 >;
+
+ sdcard@1 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <12500000>;
+ voltage-ranges = <3200 3400>;
+ mode = <0>;
+ };
+ };
+
+ serial@100 {
+ clock-frequency = <125000000>;
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ current-speed = <19200>;
+ device_type = "serial";
+ interrupts = < 0x12 >;
+ port-number = <0>;
+ reg = < 0x100 0x10 >;
+ };
+ };
+};
--
2.8.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v2 03/12] of: add J-Core interrupt controller bindings
2016-05-20 2:53 [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
[not found] ` <cover.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-20 2:53 ` [PATCH v2 02/12] of: add J-Core cpu bindings Rich Felker
@ 2016-05-20 2:53 ` Rich Felker
2016-05-20 8:04 ` Geert Uytterhoeven
2016-05-23 20:53 ` Rob Herring
2016-05-20 2:53 ` [PATCH v2 05/12] of: add J-Core SPI master bindings Rich Felker
2016-05-20 2:53 ` [PATCH v2 04/12] of: add J-Core timer bindings Rich Felker
4 siblings, 2 replies; 31+ messages in thread
From: Rich Felker @ 2016-05-20 2:53 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-sh
Cc: Ian Campbell, Jason Cooper, Kumar Gala, Marc Zyngier,
Mark Rutland, Pawel Moll, Rob Herring, Thomas Gleixner
Signed-off-by: Rich Felker <dalias@libc.org>
---
.../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
new file mode 100644
index 0000000..dc9fde8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
@@ -0,0 +1,28 @@
+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
+ with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+ the "aic2" core with 64 interrupts.
+
+- interrupt-controller : Identifies the node as an interrupt controller
+
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+Additional properties required for aic1:
+
+- reg : Memory region for configuration.
+
+- cpu-offset : For SMP, the offset to the per-cpu memory region for
+ configuration, to be scaled by the cpu number.
+
+
+Example:
+
+aic: interrupt-controller {
+ compatible = "jcore,aic2";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
--
2.8.1
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH v2 04/12] of: add J-Core timer bindings
2016-05-20 2:53 ` [PATCH v2 04/12] of: add J-Core timer bindings Rich Felker
@ 2016-05-20 8:03 ` Geert Uytterhoeven
0 siblings, 0 replies; 31+ messages in thread
From: Geert Uytterhoeven @ 2016-05-20 8:03 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Linux-sh list, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll,
Rob Herring
On Fri, May 20, 2016 at 4:53 AM, Rich Felker <dalias@libc.org> wrote:
> +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
> @@ -0,0 +1,28 @@
> +Example:
> +
> +timer {
timer@200
> + compatible = "jcore,pit";
> + reg = < 0x200 0x30 >;
> + cpu-offset = < 0x300 >;
> + interrupts = < 0x48 >;
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings
2016-05-20 2:53 ` [PATCH v2 03/12] of: add J-Core interrupt controller bindings Rich Felker
@ 2016-05-20 8:04 ` Geert Uytterhoeven
[not found] ` <CAMuHMdVs9=8BGwmCBuYch2abJBnCLKoEx7i3EMghW3UUjXc7dA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-05-23 20:53 ` Rob Herring
1 sibling, 1 reply; 31+ messages in thread
From: Geert Uytterhoeven @ 2016-05-20 8:04 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Linux-sh list, Ian Campbell, Jason Cooper, Kumar Gala,
Marc Zyngier, Mark Rutland, Pawel Moll, Rob Herring,
Thomas Gleixner
On Fri, May 20, 2016 at 4:53 AM, Rich Felker <dalias@libc.org> wrote:
> +Additional properties required for aic1:
> +
> +- reg : Memory region for configuration.
> +
> +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> + configuration, to be scaled by the cpu number.
Does cpu-offset apply to aic1 only?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 05/12] of: add J-Core SPI master bindings
2016-05-20 2:53 ` [PATCH v2 05/12] of: add J-Core SPI master bindings Rich Felker
@ 2016-05-20 8:05 ` Geert Uytterhoeven
2016-05-23 21:00 ` Rob Herring
1 sibling, 0 replies; 31+ messages in thread
From: Geert Uytterhoeven @ 2016-05-20 8:05 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Linux-sh list, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll,
Rob Herring
On Fri, May 20, 2016 at 4:53 AM, Rich Felker <dalias@libc.org> wrote:
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/jcore,spi.txt
> @@ -0,0 +1,23 @@
> +Example:
> +
> +spi {
spi@40
> + compatible = "jcore,spi2";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = < 0x40 0x8 >;
> + spi-max-frequency = <12500000>;
> +}
Gr{oetje,eeting}s,
Geert
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board
[not found] ` <9960d6526523727d1bee3d11c6704e09e600c6fe.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
@ 2016-05-20 8:17 ` Geert Uytterhoeven
2016-05-20 22:42 ` Rich Felker
0 siblings, 1 reply; 31+ messages in thread
From: Geert Uytterhoeven @ 2016-05-20 8:17 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Linux-sh list, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll,
Rob Herring, Yoshinori Sato
On Fri, May 20, 2016 at 4:53 AM, Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org> wrote:
> --- /dev/null
> +++ b/arch/sh/boot/dts/j2_mimas_v2.dts
> @@ -0,0 +1,87 @@
> +/dts-v1/;
> +
> +/ {
> + compatible = "jcore,j2-soc";
> + model = "J2 FPGA SoC on Mimas v2 board";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + interrupt-parent = <&aic>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "jcore,j2";
> + reg = < 0 >;
> + clock-frequency = < 50000000 >;
> + };
> + };
> +
> + memory@10000000 {
> + device_type = "memory";
> + reg = < 0x10000000 0x4000000 >;
> + };
> +
> + chosen {
> + stdout-path = "/soc@abcd0000/serial@100";
> + };
> +
> + soc@abcd0000 {
> + compatible = "simple-bus";
> + ranges = <0 0xabcd0000 0x100000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + aic: interrupt-controller {
aic: interrupt-controller@200 {
> + compatible = "jcore,aic1";
> + reg = < 0x200 0x10 >;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + cache-controller {
@c0
> + compatible = "jcore,cache";
> + reg = < 0xc0 4 >;
> + };
> +
> + timer {
@200
> + compatible = "jcore,pit";
> + reg = < 0x200 0x30 >;
> + interrupts = < 0x48 >;
> + };
> +
> + spi {
@40
> + compatible = "jcore,spi2";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + spi-max-frequency = <12500000>;
> +
> + reg = < 0x40 0x8 >;
> +
> + sdcard@1 {
@0, to match reg below?
> + compatible = "mmc-spi-slot";
> + reg = <0>;
> + spi-max-frequency = <12500000>;
> + voltage-ranges = <3200 3400>;
> + mode = <0>;
> + };
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings
[not found] ` <CAMuHMdVs9=8BGwmCBuYch2abJBnCLKoEx7i3EMghW3UUjXc7dA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-05-20 22:34 ` Rich Felker
2016-05-21 18:07 ` Geert Uytterhoeven
0 siblings, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-20 22:34 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Linux-sh list, Ian Campbell, Jason Cooper, Kumar Gala,
Marc Zyngier, Mark Rutland, Pawel Moll, Rob Herring,
Thomas Gleixner
On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
> On Fri, May 20, 2016 at 4:53 AM, Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org> wrote:
> > +Additional properties required for aic1:
> > +
> > +- reg : Memory region for configuration.
> > +
> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> > + configuration, to be scaled by the cpu number.
>
> Does cpu-offset apply to aic1 only?
The current kernel driver doesn't have any reason to _need_ cpu-offset
for aic2, but since there are registers there that a driver (even a
non-Linux one) may want to use, I think it makes sense that it should
be present in the bindings.
Rich
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board
2016-05-20 8:17 ` Geert Uytterhoeven
@ 2016-05-20 22:42 ` Rich Felker
0 siblings, 0 replies; 31+ messages in thread
From: Rich Felker @ 2016-05-20 22:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Linux-sh list, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll,
Rob Herring, Yoshinori Sato
On Fri, May 20, 2016 at 10:17:34AM +0200, Geert Uytterhoeven wrote:
> On Fri, May 20, 2016 at 4:53 AM, Rich Felker <dalias@libc.org> wrote:
> > --- /dev/null
> > +++ b/arch/sh/boot/dts/j2_mimas_v2.dts
> > @@ -0,0 +1,87 @@
> > +/dts-v1/;
> > +
> > +/ {
> > + compatible = "jcore,j2-soc";
> > + model = "J2 FPGA SoC on Mimas v2 board";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + interrupt-parent = <&aic>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu@0 {
> > + device_type = "cpu";
> > + compatible = "jcore,j2";
> > + reg = < 0 >;
> > + clock-frequency = < 50000000 >;
> > + };
> > + };
> > +
> > + memory@10000000 {
> > + device_type = "memory";
> > + reg = < 0x10000000 0x4000000 >;
> > + };
> > +
> > + chosen {
> > + stdout-path = "/soc@abcd0000/serial@100";
> > + };
> > +
> > + soc@abcd0000 {
> > + compatible = "simple-bus";
> > + ranges = <0 0xabcd0000 0x100000>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + aic: interrupt-controller {
>
> aic: interrupt-controller@200 {
>
> > + compatible = "jcore,aic1";
> > + reg = < 0x200 0x10 >;
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + };
> > +
> > + cache-controller {
>
> @c0
>
> > + compatible = "jcore,cache";
> > + reg = < 0xc0 4 >;
> > + };
> > +
> > + timer {
>
> @200
>
> > + compatible = "jcore,pit";
> > + reg = < 0x200 0x30 >;
> > + interrupts = < 0x48 >;
> > + };
> > +
> > + spi {
>
> @40
>
> > + compatible = "jcore,spi2";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + spi-max-frequency = <12500000>;
> > +
> > + reg = < 0x40 0x8 >;
> > +
> > + sdcard@1 {
>
> @0, to match reg below?
Yes; thanks for catching that. The chipselect logic was wrong a long
time ago and the wrong setting to compensate for that was fixed in the
actual reg cell but not in the name when the driver was fixed. I'm
applying all these changes.
Rich
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings
2016-05-20 22:34 ` Rich Felker
@ 2016-05-21 18:07 ` Geert Uytterhoeven
2016-05-21 19:17 ` Rich Felker
0 siblings, 1 reply; 31+ messages in thread
From: Geert Uytterhoeven @ 2016-05-21 18:07 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Linux-sh list, Ian Campbell, Jason Cooper, Kumar Gala,
Marc Zyngier, Mark Rutland, Pawel Moll, Rob Herring,
Thomas Gleixner
On Sat, May 21, 2016 at 12:34 AM, Rich Felker <dalias@libc.org> wrote:
> On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
>> On Fri, May 20, 2016 at 4:53 AM, Rich Felker <dalias@libc.org> wrote:
>> > +Additional properties required for aic1:
>> > +
>> > +- reg : Memory region for configuration.
>> > +
>> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
>> > + configuration, to be scaled by the cpu number.
>>
>> Does cpu-offset apply to aic1 only?
>
> The current kernel driver doesn't have any reason to _need_ cpu-offset
> for aic2, but since there are registers there that a driver (even a
> non-Linux one) may want to use, I think it makes sense that it should
> be present in the bindings.
Hence the "for aic1" should be dropped?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings
2016-05-21 18:07 ` Geert Uytterhoeven
@ 2016-05-21 19:17 ` Rich Felker
0 siblings, 0 replies; 31+ messages in thread
From: Rich Felker @ 2016-05-21 19:17 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Linux-sh list, Ian Campbell, Jason Cooper, Kumar Gala,
Marc Zyngier, Mark Rutland, Pawel Moll, Rob Herring,
Thomas Gleixner
On Sat, May 21, 2016 at 08:07:54PM +0200, Geert Uytterhoeven wrote:
> On Sat, May 21, 2016 at 12:34 AM, Rich Felker <dalias@libc.org> wrote:
> > On Fri, May 20, 2016 at 10:04:26AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, May 20, 2016 at 4:53 AM, Rich Felker <dalias@libc.org> wrote:
> >> > +Additional properties required for aic1:
> >> > +
> >> > +- reg : Memory region for configuration.
> >> > +
> >> > +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> >> > + configuration, to be scaled by the cpu number.
> >>
> >> Does cpu-offset apply to aic1 only?
> >
> > The current kernel driver doesn't have any reason to _need_ cpu-offset
> > for aic2, but since there are registers there that a driver (even a
> > non-Linux one) may want to use, I think it makes sense that it should
> > be present in the bindings.
>
> Hence the "for aic1" should be dropped?
Yes, I've fixed that locally. Moved reg to required and cpu-offset
to optional but needed for smp.
Rich
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 02/12] of: add J-Core cpu bindings
[not found] ` <f3c89e4834665790ff13478c571cc9aaa9de5559.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
@ 2016-05-23 20:48 ` Rob Herring
2016-05-23 21:03 ` Rich Felker
0 siblings, 1 reply; 31+ messages in thread
From: Rob Herring @ 2016-05-23 20:48 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sh-u79uwXL29TY76Z2rM5mHXA, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org>
> ---
> Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
>
> diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
> new file mode 100644
> index 0000000..00ef112
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/jcore/cpus.txt
> @@ -0,0 +1,91 @@
> +===================
> +J-Core cpu bindings
> +===================
> +
> +The J-Core processors are open source CPU cores that can be built as FPGA
> +soft cores or ASICs. The device tree is also responsible for describing the
> +cache controls and, for SMP configurations, all details of the SMP method,
> +as documented below.
> +
> +
> +---------------------
> +Top-level "cpus" node
> +---------------------
> +
> +Required properties:
> +
> +- #address-cells: Must be 1.
> +
> +- #size-cells: Must be 0.
> +
> +Optional properties:
> +
> +- enable-method: Required only for SMP systems. If present, must be
> + "jcore,spin-table".
> +
> +
> +--------------------
> +Individual cpu nodes
> +--------------------
> +
> +Required properties:
> +
> +- device_type: Must be "cpu".
> +
> +- compatible: Must be "jcore,j2".
Okay to have this, but you should have compatible strings for specific
core implementations. AIUI, J2 is just the ISA.
> +
> +- reg: Must be 0 on uniprocessor systems, or the sequential, zero-based
> + hardware cpu id on SMP systems.
> +
> +Optional properties:
> +
> +- clock-frequency: Clock frequency of the cpu in Hz.
> +
> +- cpu-release-addr: Necessary only for secondary processors on SMP systems
> + using the "jcore,spin-table" enable method. If present, must consist of
> + two cells containing physical addresses. The first cell contains an
> + address which, when written, unblocks the secondary cpu. The second cell
> + contains an address from which the cpu will read its initial program
> + counter when unblocked.
> +
> +
> +---------------------
> +Cache controller node
> +---------------------
> +
> +Required properties:
> +
> +- compatible: Must be "jcore,cache".
That's pretty generic...
> +
> +- reg: A memory range for the cache controller registers.
And standard cache properties? Are size, sets, ways, line size, etc.
discoverable?
> +
> +
> +--------
> +IPI node
> +--------
> +
> +Device trees for SMP systems must have an IPI node representing the mechanism
> +used for inter-processor interrupt generation.
> +
> +Required properties:
> +
> +- compatible: Must be "jcore,ipi-controller".
Again, seems pretty generic.
> +
> +- reg: A memory range used to IPI generation.
> +
> +- interrupts: An irq on which IPI will be received.
> +
> +
> +----------
> +CPUID node
> +----------
> +
> +Device trees for SMP systems must have a CPUID node representing the mechanism
> +used to identify the current processor on which execution is taking place.
> +
> +Required properties:
> +
> +- compatible: Must be "jcore,cpuid-mmio".
> +
> +- reg: A memory range containing a single 32-bit mmio register which produces
> + the current cpu id when read.
This id matches the reg value in cpu node, right? If not, it should.
Rob
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 01/12] of: add vendor prefix for J-Core
2016-05-20 2:53 ` [PATCH v2 01/12] of: add vendor prefix for J-Core Rich Felker
@ 2016-05-23 20:49 ` Rob Herring
0 siblings, 0 replies; 31+ messages in thread
From: Rob Herring @ 2016-05-23 20:49 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
> The J-Core project (j-core.org) produces open source cpu and SoC
> peripheral cores synthesizable as FPGA bitstreams or ASICs.
>
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings
2016-05-20 2:53 ` [PATCH v2 03/12] of: add J-Core interrupt controller bindings Rich Felker
2016-05-20 8:04 ` Geert Uytterhoeven
@ 2016-05-23 20:53 ` Rob Herring
2016-05-23 21:13 ` Rich Felker
1 sibling, 1 reply; 31+ messages in thread
From: Rob Herring @ 2016-05-23 20:53 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Jason Cooper,
Kumar Gala, Marc Zyngier, Mark Rutland, Pawel Moll,
Thomas Gleixner
On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
> .../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> new file mode 100644
> index 0000000..dc9fde8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> @@ -0,0 +1,28 @@
> +J-Core Advanced Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> + the "aic2" core with 64 interrupts.
> +
> +- interrupt-controller : Identifies the node as an interrupt controller
> +
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The value shall be 1.
No level/edge support? Need 2 cells if so.
> +
> +Additional properties required for aic1:
> +
> +- reg : Memory region for configuration.
> +
> +- cpu-offset : For SMP, the offset to the per-cpu memory region for
> + configuration, to be scaled by the cpu number.
> +
> +
> +Example:
> +
> +aic: interrupt-controller {
> + compatible = "jcore,aic2";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +};
> --
> 2.8.1
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 05/12] of: add J-Core SPI master bindings
2016-05-20 2:53 ` [PATCH v2 05/12] of: add J-Core SPI master bindings Rich Felker
2016-05-20 8:05 ` Geert Uytterhoeven
@ 2016-05-23 21:00 ` Rob Herring
2016-05-23 21:06 ` Rich Felker
1 sibling, 1 reply; 31+ messages in thread
From: Rob Herring @ 2016-05-23 21:00 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote:
> Signed-off-by: Rich Felker <dalias@libc.org>
> ---
> .../devicetree/bindings/spi/jcore,spi.txt | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/jcore,spi.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/jcore,spi.txt b/Documentation/devicetree/bindings/spi/jcore,spi.txt
> new file mode 100644
> index 0000000..9055e7d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/jcore,spi.txt
> @@ -0,0 +1,23 @@
> +J-Core SPI master
> +
> +Required properties:
> +
> +- compatible: Must be "jcore,spi2".
In general, these all seem a bit generic. You should be able to
correlate IP versions to compatible strings.
Rob
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 02/12] of: add J-Core cpu bindings
2016-05-23 20:48 ` Rob Herring
@ 2016-05-23 21:03 ` Rich Felker
2016-05-23 23:29 ` Rob Herring
0 siblings, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-23 21:03 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Mon, May 23, 2016 at 03:48:46PM -0500, Rob Herring wrote:
> On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
> > Signed-off-by: Rich Felker <dalias@libc.org>
> > ---
> > Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
> > 1 file changed, 91 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
> >
> > diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
> > new file mode 100644
> > index 0000000..00ef112
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/jcore/cpus.txt
> > @@ -0,0 +1,91 @@
> > +===================
> > +J-Core cpu bindings
> > +===================
> > +
> > +The J-Core processors are open source CPU cores that can be built as FPGA
> > +soft cores or ASICs. The device tree is also responsible for describing the
> > +cache controls and, for SMP configurations, all details of the SMP method,
> > +as documented below.
> > +
> > +
> > +---------------------
> > +Top-level "cpus" node
> > +---------------------
> > +
> > +Required properties:
> > +
> > +- #address-cells: Must be 1.
> > +
> > +- #size-cells: Must be 0.
> > +
> > +Optional properties:
> > +
> > +- enable-method: Required only for SMP systems. If present, must be
> > + "jcore,spin-table".
> > +
> > +
> > +--------------------
> > +Individual cpu nodes
> > +--------------------
> > +
> > +Required properties:
> > +
> > +- device_type: Must be "cpu".
> > +
> > +- compatible: Must be "jcore,j2".
>
> Okay to have this, but you should have compatible strings for specific
> core implementations. AIUI, J2 is just the ISA.
There was some past discussion you probably missed on the linux-sh
list, starting here:
http://www.spinics.net/lists/linux-sh/msg50028.html
Basically it's really hard to identify what "the specific core
implementation" even means with a soft core. If you have some ideas
I'd be happy to hear them, but I think there should always be a
"jcore,j2" fallback compatible tag in any case.
FYI the way we're trying to use DT is to avoid hard-coding any
properties about the SoC (like mmio register addresses, cache
properties, etc.) in the cpu compatible tag, and instead breaking
things down into as many device nodes as possible, to allow variations
to be represented without having to encode them in the kernel/driver
sources.
> > +- reg: Must be 0 on uniprocessor systems, or the sequential, zero-based
> > + hardware cpu id on SMP systems.
> > +
> > +Optional properties:
> > +
> > +- clock-frequency: Clock frequency of the cpu in Hz.
> > +
> > +- cpu-release-addr: Necessary only for secondary processors on SMP systems
> > + using the "jcore,spin-table" enable method. If present, must consist of
> > + two cells containing physical addresses. The first cell contains an
> > + address which, when written, unblocks the secondary cpu. The second cell
> > + contains an address from which the cpu will read its initial program
> > + counter when unblocked.
> > +
> > +
> > +---------------------
> > +Cache controller node
> > +---------------------
> > +
> > +Required properties:
> > +
> > +- compatible: Must be "jcore,cache".
>
> That's pretty generic...
Most of the DT compatible tags were derived from the component
directory/source-file names in the J-Core source. In the case of
cache, it's actually called "icache" in the source for historical
reasons despite also including dcache, so I just used "cache" in the
DT.
> > +
> > +- reg: A memory range for the cache controller registers.
>
> And standard cache properties? Are size, sets, ways, line size, etc.
> discoverable?
I want to do the cache properties in a way that's generic for all of
arch/sh rather than specific to J2, but that's going to be part of the
DT conversion project. That's why I just have properties hard-coded
for now in the kernel source. They're not really used anyway except
for presenting them in /proc/cpuinfo.
> > +--------
> > +IPI node
> > +--------
> > +
> > +Device trees for SMP systems must have an IPI node representing the mechanism
> > +used for inter-processor interrupt generation.
> > +
> > +Required properties:
> > +
> > +- compatible: Must be "jcore,ipi-controller".
>
> Again, seems pretty generic.
I'm open to different ideas for naming schemes, but in the big scheme
of things it doesn't really matter. When there's a new incompatible
one, it can have a new compatible tag.
> > +----------
> > +CPUID node
> > +----------
> > +
> > +Device trees for SMP systems must have a CPUID node representing the mechanism
> > +used to identify the current processor on which execution is taking place.
> > +
> > +Required properties:
> > +
> > +- compatible: Must be "jcore,cpuid-mmio".
> > +
> > +- reg: A memory range containing a single 32-bit mmio register which produces
> > + the current cpu id when read.
>
> This id matches the reg value in cpu node, right? If not, it should.
Yes. Should I document that here?
Rich
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 05/12] of: add J-Core SPI master bindings
2016-05-23 21:00 ` Rob Herring
@ 2016-05-23 21:06 ` Rich Felker
[not found] ` <20160523210618.GF21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
0 siblings, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-23 21:06 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-kernel, linux-sh, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Mon, May 23, 2016 at 04:00:20PM -0500, Rob Herring wrote:
> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote:
> > Signed-off-by: Rich Felker <dalias@libc.org>
> > ---
> > .../devicetree/bindings/spi/jcore,spi.txt | 23 ++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/spi/jcore,spi.txt
> >
> > diff --git a/Documentation/devicetree/bindings/spi/jcore,spi.txt b/Documentation/devicetree/bindings/spi/jcore,spi.txt
> > new file mode 100644
> > index 0000000..9055e7d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/spi/jcore,spi.txt
> > @@ -0,0 +1,23 @@
> > +J-Core SPI master
> > +
> > +Required properties:
> > +
> > +- compatible: Must be "jcore,spi2".
>
> In general, these all seem a bit generic. You should be able to
> correlate IP versions to compatible strings.
"spi2" is the name of the "IP core" in the J-Core source tree. The WIP
that adds DMA support and makes some changes is called "spi3" there;
I'll submit a patch adding "jcore,spi3" to the binding file once the
vhdl for it has been released.
Rich
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings
2016-05-23 20:53 ` Rob Herring
@ 2016-05-23 21:13 ` Rich Felker
[not found] ` <20160523211342.GG21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
0 siblings, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-23 21:13 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sh-u79uwXL29TY76Z2rM5mHXA, Ian Campbell, Jason Cooper,
Kumar Gala, Marc Zyngier, Mark Rutland, Pawel Moll,
Thomas Gleixner
On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote:
> > Signed-off-by: Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org>
> > ---
> > .../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > new file mode 100644
> > index 0000000..dc9fde8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> > @@ -0,0 +1,28 @@
> > +J-Core Advanced Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> > + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> > + the "aic2" core with 64 interrupts.
> > +
> > +- interrupt-controller : Identifies the node as an interrupt controller
> > +
> > +- #interrupt-cells : Specifies the number of cells needed to encode an
> > + interrupt source. The value shall be 1.
>
> No level/edge support? Need 2 cells if so.
No, all the logic is in hardware. From the software side you just need
handle_simple_irq or equivalent.
Rich
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 05/12] of: add J-Core SPI master bindings
[not found] ` <20160523210618.GF21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
@ 2016-05-23 23:16 ` Rob Herring
0 siblings, 0 replies; 31+ messages in thread
From: Rob Herring @ 2016-05-23 23:16 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, SH-Linux,
Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Mon, May 23, 2016 at 4:06 PM, Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org> wrote:
> On Mon, May 23, 2016 at 04:00:20PM -0500, Rob Herring wrote:
>> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote:
>> > Signed-off-by: Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org>
>> > ---
>> > .../devicetree/bindings/spi/jcore,spi.txt | 23 ++++++++++++++++++++++
>> > 1 file changed, 23 insertions(+)
>> > create mode 100644 Documentation/devicetree/bindings/spi/jcore,spi.txt
>> >
>> > diff --git a/Documentation/devicetree/bindings/spi/jcore,spi.txt b/Documentation/devicetree/bindings/spi/jcore,spi.txt
>> > new file mode 100644
>> > index 0000000..9055e7d
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/spi/jcore,spi.txt
>> > @@ -0,0 +1,23 @@
>> > +J-Core SPI master
>> > +
>> > +Required properties:
>> > +
>> > +- compatible: Must be "jcore,spi2".
>>
>> In general, these all seem a bit generic. You should be able to
>> correlate IP versions to compatible strings.
>
> "spi2" is the name of the "IP core" in the J-Core source tree. The WIP
> that adds DMA support and makes some changes is called "spi3" there;
> I'll submit a patch adding "jcore,spi3" to the binding file once the
> vhdl for it has been released.
Okay.
Rob
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 02/12] of: add J-Core cpu bindings
2016-05-23 21:03 ` Rich Felker
@ 2016-05-23 23:29 ` Rob Herring
2016-05-24 2:39 ` Rich Felker
2016-05-24 21:30 ` Rob Landley
0 siblings, 2 replies; 31+ messages in thread
From: Rob Herring @ 2016-05-23 23:29 UTC (permalink / raw)
To: Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Mon, May 23, 2016 at 4:03 PM, Rich Felker <dalias@libc.org> wrote:
> On Mon, May 23, 2016 at 03:48:46PM -0500, Rob Herring wrote:
>> On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
>> > Signed-off-by: Rich Felker <dalias@libc.org>
>> > ---
>> > Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
>> > 1 file changed, 91 insertions(+)
>> > create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
>> >
>> > diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
>> > new file mode 100644
>> > index 0000000..00ef112
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/jcore/cpus.txt
>> > @@ -0,0 +1,91 @@
>> > +===================
>> > +J-Core cpu bindings
>> > +===================
>> > +
>> > +The J-Core processors are open source CPU cores that can be built as FPGA
>> > +soft cores or ASICs. The device tree is also responsible for describing the
>> > +cache controls and, for SMP configurations, all details of the SMP method,
>> > +as documented below.
>> > +
>> > +
>> > +---------------------
>> > +Top-level "cpus" node
>> > +---------------------
>> > +
>> > +Required properties:
>> > +
>> > +- #address-cells: Must be 1.
>> > +
>> > +- #size-cells: Must be 0.
>> > +
>> > +Optional properties:
>> > +
>> > +- enable-method: Required only for SMP systems. If present, must be
>> > + "jcore,spin-table".
>> > +
>> > +
>> > +--------------------
>> > +Individual cpu nodes
>> > +--------------------
>> > +
>> > +Required properties:
>> > +
>> > +- device_type: Must be "cpu".
>> > +
>> > +- compatible: Must be "jcore,j2".
>>
>> Okay to have this, but you should have compatible strings for specific
>> core implementations. AIUI, J2 is just the ISA.
>
> There was some past discussion you probably missed on the linux-sh
> list, starting here:
>
> http://www.spinics.net/lists/linux-sh/msg50028.html
>
> Basically it's really hard to identify what "the specific core
> implementation" even means with a soft core. If you have some ideas
> I'd be happy to hear them, but I think there should always be a
> "jcore,j2" fallback compatible tag in any case.
Presumably you do some sort of versioning on the VHDL source that you
can correlate to.
If you have sufficient s/w accessible version registers that are
always going to be updated on IP changes then, you don't really need
more specific compatible strings.
> FYI the way we're trying to use DT is to avoid hard-coding any
> properties about the SoC (like mmio register addresses, cache
> properties, etc.) in the cpu compatible tag, and instead breaking
> things down into as many device nodes as possible, to allow variations
> to be represented without having to encode them in the kernel/driver
> sources.
Yes, that is the purpose of DT.
>> > +- reg: Must be 0 on uniprocessor systems, or the sequential, zero-based
>> > + hardware cpu id on SMP systems.
>> > +
>> > +Optional properties:
>> > +
>> > +- clock-frequency: Clock frequency of the cpu in Hz.
>> > +
>> > +- cpu-release-addr: Necessary only for secondary processors on SMP systems
>> > + using the "jcore,spin-table" enable method. If present, must consist of
>> > + two cells containing physical addresses. The first cell contains an
>> > + address which, when written, unblocks the secondary cpu. The second cell
>> > + contains an address from which the cpu will read its initial program
>> > + counter when unblocked.
>> > +
>> > +
>> > +---------------------
>> > +Cache controller node
>> > +---------------------
>> > +
>> > +Required properties:
>> > +
>> > +- compatible: Must be "jcore,cache".
>>
>> That's pretty generic...
>
> Most of the DT compatible tags were derived from the component
> directory/source-file names in the J-Core source. In the case of
> cache, it's actually called "icache" in the source for historical
> reasons despite also including dcache, so I just used "cache" in the
> DT.
>
>> > +
>> > +- reg: A memory range for the cache controller registers.
>>
>> And standard cache properties? Are size, sets, ways, line size, etc.
>> discoverable?
>
> I want to do the cache properties in a way that's generic for all of
> arch/sh rather than specific to J2, but that's going to be part of the
> DT conversion project. That's why I just have properties hard-coded
> for now in the kernel source. They're not really used anyway except
> for presenting them in /proc/cpuinfo.
The DT spec (devicetree.org, formerly ePAPR) already defines arch
independent cache properties.
>> > +--------
>> > +IPI node
>> > +--------
>> > +
>> > +Device trees for SMP systems must have an IPI node representing the mechanism
>> > +used for inter-processor interrupt generation.
>> > +
>> > +Required properties:
>> > +
>> > +- compatible: Must be "jcore,ipi-controller".
>>
>> Again, seems pretty generic.
>
> I'm open to different ideas for naming schemes, but in the big scheme
> of things it doesn't really matter. When there's a new incompatible
> one, it can have a new compatible tag.
It should make sense according to how you version the VHDL sources.
The Xilinx folks have X.Y version numbers for example. We generally
don't accept those, but for soft IP that is an exception.
Better yet, since you can change "the hardware", make it more
discoverable with registers for version numbering and feature bits.
The failure here is having a process where that can be forgotten...
>> > +----------
>> > +CPUID node
>> > +----------
>> > +
>> > +Device trees for SMP systems must have a CPUID node representing the mechanism
>> > +used to identify the current processor on which execution is taking place.
>> > +
>> > +Required properties:
>> > +
>> > +- compatible: Must be "jcore,cpuid-mmio".
>> > +
>> > +- reg: A memory range containing a single 32-bit mmio register which produces
>> > + the current cpu id when read.
>>
>> This id matches the reg value in cpu node, right? If not, it should.
>
> Yes. Should I document that here?
Yes.
Rob
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 02/12] of: add J-Core cpu bindings
2016-05-23 23:29 ` Rob Herring
@ 2016-05-24 2:39 ` Rich Felker
2016-05-24 21:30 ` Rob Landley
1 sibling, 0 replies; 31+ messages in thread
From: Rich Felker @ 2016-05-24 2:39 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On Mon, May 23, 2016 at 06:29:48PM -0500, Rob Herring wrote:
> >> > +- compatible: Must be "jcore,j2".
> >>
> >> Okay to have this, but you should have compatible strings for specific
> >> core implementations. AIUI, J2 is just the ISA.
> >
> > There was some past discussion you probably missed on the linux-sh
> > list, starting here:
> >
> > http://www.spinics.net/lists/linux-sh/msg50028.html
> >
> > Basically it's really hard to identify what "the specific core
> > implementation" even means with a soft core. If you have some ideas
> > I'd be happy to hear them, but I think there should always be a
> > "jcore,j2" fallback compatible tag in any case.
>
> Presumably you do some sort of versioning on the VHDL source that you
> can correlate to.
Yes, but I'm not convinced that helps with anything. Presumably the
point of having a fine-grained version in the compatible tag would be
to work around bugs. But if those bugs could come from build options,
specific version of the FPGA tools used, specific board targets, etc.
then a version really isn't sufficient to help you work around bugs.
On the other hand, as long as it's soft core, if there is a bug you
just fix the bitstream rather than putting workaround hacks in the
kernel or other software.
It does make sense to have some identifier for particular builds and
production runs once we have ASICs, of course, but that's a topic to
discuss when we get there.
I think most of this was already discussed in the thread I linked
above.
> >> > +- reg: A memory range for the cache controller registers.
> >>
> >> And standard cache properties? Are size, sets, ways, line size, etc.
> >> discoverable?
> >
> > I want to do the cache properties in a way that's generic for all of
> > arch/sh rather than specific to J2, but that's going to be part of the
> > DT conversion project. That's why I just have properties hard-coded
> > for now in the kernel source. They're not really used anyway except
> > for presenting them in /proc/cpuinfo.
>
> The DT spec (devicetree.org, formerly ePAPR) already defines arch
> independent cache properties.
Indeed, but they don't seem to be comprehensive. In particular they
don't seem to represent the properties needed to compute aliasing for
VIPT cache architectures, or to represent whether the cache is
virtually or physically indexed or tagged.
> >> > +--------
> >> > +IPI node
> >> > +--------
> >> > +
> >> > +Device trees for SMP systems must have an IPI node representing the mechanism
> >> > +used for inter-processor interrupt generation.
> >> > +
> >> > +Required properties:
> >> > +
> >> > +- compatible: Must be "jcore,ipi-controller".
> >>
> >> Again, seems pretty generic.
> >
> > I'm open to different ideas for naming schemes, but in the big scheme
> > of things it doesn't really matter. When there's a new incompatible
> > one, it can have a new compatible tag.
>
> It should make sense according to how you version the VHDL sources.
> The Xilinx folks have X.Y version numbers for example. We generally
> don't accept those, but for soft IP that is an exception.
>
> Better yet, since you can change "the hardware", make it more
> discoverable with registers for version numbering and feature bits.
> The failure here is having a process where that can be forgotten...
I suspect that takes more space on the FPGA/ASIC than adding a few
bytes to the DTB in the boot rom would, so it's probably a worse
solution.
We could potentially allow compatible tags of the form "foo-v*" for
each "foo" documented now, where the version is from the jcore source
repo, and recommend (for example):
compatible = "jcore,foo-v1.23", "jcore,foo";
This would be separate from the numbers that are already present in
things like "spi2" and "spi3" (functionally distinct spi master
devices) or "aic1" and "aic2" (functionally distinct interrupt
controllers).
How would you want this to be documented, if we go that route?
Certainly all possible values cannot be specified in the binding docs
then.
> >> > +----------
> >> > +CPUID node
> >> > +----------
> >> > +
> >> > +Device trees for SMP systems must have a CPUID node representing the mechanism
> >> > +used to identify the current processor on which execution is taking place.
> >> > +
> >> > +Required properties:
> >> > +
> >> > +- compatible: Must be "jcore,cpuid-mmio".
> >> > +
> >> > +- reg: A memory range containing a single 32-bit mmio register which produces
> >> > + the current cpu id when read.
> >>
> >> This id matches the reg value in cpu node, right? If not, it should.
> >
> > Yes. Should I document that here?
>
> Yes.
OK, adding it to read:
- reg: A memory range containing a single 32-bit mmio register which produces
the current cpu id (matching the "reg" property of the cpu performing the
read) when read.
Rich
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings
[not found] ` <20160523211342.GG21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
@ 2016-05-24 8:09 ` Marc Zyngier
[not found] ` <57440C45.5040105-5wv7dgnIgG8@public.gmane.org>
0 siblings, 1 reply; 31+ messages in thread
From: Marc Zyngier @ 2016-05-24 8:09 UTC (permalink / raw)
To: Rich Felker, Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sh-u79uwXL29TY76Z2rM5mHXA, Ian Campbell, Jason Cooper,
Kumar Gala, Mark Rutland, Pawel Moll, Thomas Gleixner
On 23/05/16 22:13, Rich Felker wrote:
> On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
>> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote:
>>> Signed-off-by: Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org>
>>> ---
>>> .../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++
>>> 1 file changed, 28 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>> new file mode 100644
>>> index 0000000..dc9fde8
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
>>> @@ -0,0 +1,28 @@
>>> +J-Core Advanced Interrupt Controller
>>> +
>>> +Required properties:
>>> +
>>> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
>>> + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
>>> + the "aic2" core with 64 interrupts.
>>> +
>>> +- interrupt-controller : Identifies the node as an interrupt controller
>>> +
>>> +- #interrupt-cells : Specifies the number of cells needed to encode an
>>> + interrupt source. The value shall be 1.
>>
>> No level/edge support? Need 2 cells if so.
>
> No, all the logic is in hardware. From the software side you just need
> handle_simple_irq or equivalent.
Not even an EOI?
M.
--
Jazz is not dead. It just smells funny...
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 02/12] of: add J-Core cpu bindings
2016-05-23 23:29 ` Rob Herring
2016-05-24 2:39 ` Rich Felker
@ 2016-05-24 21:30 ` Rob Landley
2016-05-25 1:13 ` Rob Herring
1 sibling, 1 reply; 31+ messages in thread
From: Rob Landley @ 2016-05-24 21:30 UTC (permalink / raw)
To: Rob Herring, Rich Felker
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
SH-Linux, Ian Campbell, Kumar Gala, Mark Rutland, Pawel Moll
On 05/23/2016 06:29 PM, Rob Herring wrote:
> On Mon, May 23, 2016 at 4:03 PM, Rich Felker <dalias@libc.org> wrote:
>> On Mon, May 23, 2016 at 03:48:46PM -0500, Rob Herring wrote:
>>> On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
>>>> Signed-off-by: Rich Felker <dalias@libc.org>
>>>> ---
>>>> Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
>>>> 1 file changed, 91 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
>>>> new file mode 100644
>>>> index 0000000..00ef112
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/jcore/cpus.txt
>>>> @@ -0,0 +1,91 @@
>>>> +===================
>>>> +J-Core cpu bindings
>>>> +===================
>>>> +
>>>> +The J-Core processors are open source CPU cores that can be built as FPGA
>>>> +soft cores or ASICs. The device tree is also responsible for describing the
>>>> +cache controls and, for SMP configurations, all details of the SMP method,
>>>> +as documented below.
>>>> +
>>>> +
>>>> +---------------------
>>>> +Top-level "cpus" node
>>>> +---------------------
>>>> +
>>>> +Required properties:
>>>> +
>>>> +- #address-cells: Must be 1.
>>>> +
>>>> +- #size-cells: Must be 0.
>>>> +
>>>> +Optional properties:
>>>> +
>>>> +- enable-method: Required only for SMP systems. If present, must be
>>>> + "jcore,spin-table".
>>>> +
>>>> +
>>>> +--------------------
>>>> +Individual cpu nodes
>>>> +--------------------
>>>> +
>>>> +Required properties:
>>>> +
>>>> +- device_type: Must be "cpu".
>>>> +
>>>> +- compatible: Must be "jcore,j2".
>>>
>>> Okay to have this, but you should have compatible strings for specific
>>> core implementations. AIUI, J2 is just the ISA.
>>
>> There was some past discussion you probably missed on the linux-sh
>> list, starting here:
>>
>> http://www.spinics.net/lists/linux-sh/msg50028.html
>>
>> Basically it's really hard to identify what "the specific core
>> implementation" even means with a soft core. If you have some ideas
>> I'd be happy to hear them, but I think there should always be a
>> "jcore,j2" fallback compatible tag in any case.
>
> Presumably you do some sort of versioning on the VHDL source that you
> can correlate to.
>
> If you have sufficient s/w accessible version registers that are
> always going to be updated on IP changes then, you don't really need
> more specific compatible strings.
There are no version registers: the boot ROM can be output as part of
the build, and the dtb can be provided by the boot ROM. So you don't
need boot registers, you literally put any version info you need in the
dtb in the boot rom.
> Better yet, since you can change "the hardware", make it more
> discoverable with registers for version numbering and feature bits.
> The failure here is having a process where that can be forgotten...
Why would you add hardware version registers when the hardware's
attached boot rom is providing a dtb?
What's the point?
Rob
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 02/12] of: add J-Core cpu bindings
2016-05-24 21:30 ` Rob Landley
@ 2016-05-25 1:13 ` Rob Herring
2016-05-25 2:33 ` Rich Felker
0 siblings, 1 reply; 31+ messages in thread
From: Rob Herring @ 2016-05-25 1:13 UTC (permalink / raw)
To: Rob Landley
Cc: Rich Felker, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, SH-Linux, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Tue, May 24, 2016 at 4:30 PM, Rob Landley <rob@landley.net> wrote:
>
>
> On 05/23/2016 06:29 PM, Rob Herring wrote:
>> On Mon, May 23, 2016 at 4:03 PM, Rich Felker <dalias@libc.org> wrote:
>>> On Mon, May 23, 2016 at 03:48:46PM -0500, Rob Herring wrote:
>>>> On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
>>>>> Signed-off-by: Rich Felker <dalias@libc.org>
>>>>> ---
>>>>> Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
>>>>> 1 file changed, 91 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
>>>>> new file mode 100644
>>>>> index 0000000..00ef112
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/jcore/cpus.txt
>>>>> @@ -0,0 +1,91 @@
>>>>> +===================
>>>>> +J-Core cpu bindings
>>>>> +===================
>>>>> +
>>>>> +The J-Core processors are open source CPU cores that can be built as FPGA
>>>>> +soft cores or ASICs. The device tree is also responsible for describing the
>>>>> +cache controls and, for SMP configurations, all details of the SMP method,
>>>>> +as documented below.
>>>>> +
>>>>> +
>>>>> +---------------------
>>>>> +Top-level "cpus" node
>>>>> +---------------------
>>>>> +
>>>>> +Required properties:
>>>>> +
>>>>> +- #address-cells: Must be 1.
>>>>> +
>>>>> +- #size-cells: Must be 0.
>>>>> +
>>>>> +Optional properties:
>>>>> +
>>>>> +- enable-method: Required only for SMP systems. If present, must be
>>>>> + "jcore,spin-table".
>>>>> +
>>>>> +
>>>>> +--------------------
>>>>> +Individual cpu nodes
>>>>> +--------------------
>>>>> +
>>>>> +Required properties:
>>>>> +
>>>>> +- device_type: Must be "cpu".
>>>>> +
>>>>> +- compatible: Must be "jcore,j2".
>>>>
>>>> Okay to have this, but you should have compatible strings for specific
>>>> core implementations. AIUI, J2 is just the ISA.
>>>
>>> There was some past discussion you probably missed on the linux-sh
>>> list, starting here:
>>>
>>> http://www.spinics.net/lists/linux-sh/msg50028.html
>>>
>>> Basically it's really hard to identify what "the specific core
>>> implementation" even means with a soft core. If you have some ideas
>>> I'd be happy to hear them, but I think there should always be a
>>> "jcore,j2" fallback compatible tag in any case.
>>
>> Presumably you do some sort of versioning on the VHDL source that you
>> can correlate to.
>>
>> If you have sufficient s/w accessible version registers that are
>> always going to be updated on IP changes then, you don't really need
>> more specific compatible strings.
>
> There are no version registers: the boot ROM can be output as part of
> the build, and the dtb can be provided by the boot ROM. So you don't
> need boot registers, you literally put any version info you need in the
> dtb in the boot rom.
You can, but you are not doing that from the looks of it. Maybe you're
not to that point to need versioning and that's fine, but it doesn't
sound like you all have thought about it.
>> Better yet, since you can change "the hardware", make it more
>> discoverable with registers for version numbering and feature bits.
>> The failure here is having a process where that can be forgotten...
>
> Why would you add hardware version registers when the hardware's
> attached boot rom is providing a dtb?
>
> What's the point?
You are missing who is reading and caring about what the version is.
It's all the software that cares what's in either version registers or
dtb to know what are the specific features of the h/w. At some point
you will have a single driver that needs to support multiple versions
and/or configurations of hardware/IP.
Rob
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 03/12] of: add J-Core interrupt controller bindings
[not found] ` <57440C45.5040105-5wv7dgnIgG8@public.gmane.org>
@ 2016-05-25 2:25 ` Rich Felker
0 siblings, 0 replies; 31+ messages in thread
From: Rich Felker @ 2016-05-25 2:25 UTC (permalink / raw)
To: Marc Zyngier
Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sh-u79uwXL29TY76Z2rM5mHXA, Ian Campbell, Jason Cooper,
Kumar Gala, Mark Rutland, Pawel Moll, Thomas Gleixner
On Tue, May 24, 2016 at 09:09:41AM +0100, Marc Zyngier wrote:
> On 23/05/16 22:13, Rich Felker wrote:
> > On Mon, May 23, 2016 at 03:53:20PM -0500, Rob Herring wrote:
> >> On Fri, May 20, 2016 at 02:53:04AM +0000, Rich Felker wrote:
> >>> Signed-off-by: Rich Felker <dalias-8zAoT0mYgF4@public.gmane.org>
> >>> ---
> >>> .../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++
> >>> 1 file changed, 28 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>> new file mode 100644
> >>> index 0000000..dc9fde8
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
> >>> @@ -0,0 +1,28 @@
> >>> +J-Core Advanced Interrupt Controller
> >>> +
> >>> +Required properties:
> >>> +
> >>> +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic
> >>> + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
> >>> + the "aic2" core with 64 interrupts.
> >>> +
> >>> +- interrupt-controller : Identifies the node as an interrupt controller
> >>> +
> >>> +- #interrupt-cells : Specifies the number of cells needed to encode an
> >>> + interrupt source. The value shall be 1.
> >>
> >> No level/edge support? Need 2 cells if so.
> >
> > No, all the logic is in hardware. From the software side you just need
> > handle_simple_irq or equivalent.
>
> Not even an EOI?
What I mean is that there is no ack/eoi interface. While I haven't
worked directly on the relevant vhdl, my understanding is that the aic
clears the pending status of an interrupt atomically with acceptance
of the interrupt by the cpu.
Do you have any more specific questions I can try to answer?
Rich
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 02/12] of: add J-Core cpu bindings
2016-05-25 1:13 ` Rob Herring
@ 2016-05-25 2:33 ` Rich Felker
2016-05-25 13:13 ` Rob Herring
0 siblings, 1 reply; 31+ messages in thread
From: Rich Felker @ 2016-05-25 2:33 UTC (permalink / raw)
To: Rob Herring
Cc: Rob Landley, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, SH-Linux, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Tue, May 24, 2016 at 08:13:14PM -0500, Rob Herring wrote:
> On Tue, May 24, 2016 at 4:30 PM, Rob Landley <rob@landley.net> wrote:
> >
> >
> > On 05/23/2016 06:29 PM, Rob Herring wrote:
> >> On Mon, May 23, 2016 at 4:03 PM, Rich Felker <dalias@libc.org> wrote:
> >>> On Mon, May 23, 2016 at 03:48:46PM -0500, Rob Herring wrote:
> >>>> On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
> >>>>> Signed-off-by: Rich Felker <dalias@libc.org>
> >>>>> ---
> >>>>> Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
> >>>>> 1 file changed, 91 insertions(+)
> >>>>> create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
> >>>>>
> >>>>> diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
> >>>>> new file mode 100644
> >>>>> index 0000000..00ef112
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/jcore/cpus.txt
> >>>>> @@ -0,0 +1,91 @@
> >>>>> +===================
> >>>>> +J-Core cpu bindings
> >>>>> +===================
> >>>>> +
> >>>>> +The J-Core processors are open source CPU cores that can be built as FPGA
> >>>>> +soft cores or ASICs. The device tree is also responsible for describing the
> >>>>> +cache controls and, for SMP configurations, all details of the SMP method,
> >>>>> +as documented below.
> >>>>> +
> >>>>> +
> >>>>> +---------------------
> >>>>> +Top-level "cpus" node
> >>>>> +---------------------
> >>>>> +
> >>>>> +Required properties:
> >>>>> +
> >>>>> +- #address-cells: Must be 1.
> >>>>> +
> >>>>> +- #size-cells: Must be 0.
> >>>>> +
> >>>>> +Optional properties:
> >>>>> +
> >>>>> +- enable-method: Required only for SMP systems. If present, must be
> >>>>> + "jcore,spin-table".
> >>>>> +
> >>>>> +
> >>>>> +--------------------
> >>>>> +Individual cpu nodes
> >>>>> +--------------------
> >>>>> +
> >>>>> +Required properties:
> >>>>> +
> >>>>> +- device_type: Must be "cpu".
> >>>>> +
> >>>>> +- compatible: Must be "jcore,j2".
> >>>>
> >>>> Okay to have this, but you should have compatible strings for specific
> >>>> core implementations. AIUI, J2 is just the ISA.
> >>>
> >>> There was some past discussion you probably missed on the linux-sh
> >>> list, starting here:
> >>>
> >>> http://www.spinics.net/lists/linux-sh/msg50028.html
> >>>
> >>> Basically it's really hard to identify what "the specific core
> >>> implementation" even means with a soft core. If you have some ideas
> >>> I'd be happy to hear them, but I think there should always be a
> >>> "jcore,j2" fallback compatible tag in any case.
> >>
> >> Presumably you do some sort of versioning on the VHDL source that you
> >> can correlate to.
> >>
> >> If you have sufficient s/w accessible version registers that are
> >> always going to be updated on IP changes then, you don't really need
> >> more specific compatible strings.
> >
> > There are no version registers: the boot ROM can be output as part of
> > the build, and the dtb can be provided by the boot ROM. So you don't
> > need boot registers, you literally put any version info you need in the
> > dtb in the boot rom.
>
> You can, but you are not doing that from the looks of it. Maybe you're
> not to that point to need versioning and that's fine, but it doesn't
> sound like you all have thought about it.
It's been thought about and discussed both on the linux-sh list and
internally in the J-Core development process, but it's certainly a
topic that could use more discussion. I don't think it should be a
blocking issue for registering current bindings, though.
> >> Better yet, since you can change "the hardware", make it more
> >> discoverable with registers for version numbering and feature bits.
> >> The failure here is having a process where that can be forgotten...
> >
> > Why would you add hardware version registers when the hardware's
> > attached boot rom is providing a dtb?
> >
> > What's the point?
>
> You are missing who is reading and caring about what the version is.
> It's all the software that cares what's in either version registers or
> dtb to know what are the specific features of the h/w. At some point
> you will have a single driver that needs to support multiple versions
> and/or configurations of hardware/IP.
This is why we have both "jcore,aic1" and "jcore,aic2" now, and why
we'll soon have a "jcore,spi3" binding for the new SPI master with DMA
support. The intent is that stable hardware interfaces are maintained
at the hardware source level, and the binding names correspond to
component names in the hardware source.
If there are good reasons for more fine-grained version information,
we can add binding specifications for such, but the only reason I've
seen so far is bug workarounds, and it really doesn't make sense to be
putting bug workarounds in the kernel rather than just fixing the
source and flashing the FPGA configuration. Once we get to ASICs of
course it might make sense.
Do you have other compelling reasons for fine-grained versioning?
Rich
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2 02/12] of: add J-Core cpu bindings
2016-05-25 2:33 ` Rich Felker
@ 2016-05-25 13:13 ` Rob Herring
0 siblings, 0 replies; 31+ messages in thread
From: Rob Herring @ 2016-05-25 13:13 UTC (permalink / raw)
To: Rich Felker
Cc: Rob Landley, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, SH-Linux, Ian Campbell, Kumar Gala,
Mark Rutland, Pawel Moll
On Tue, May 24, 2016 at 9:33 PM, Rich Felker <dalias@libc.org> wrote:
> On Tue, May 24, 2016 at 08:13:14PM -0500, Rob Herring wrote:
>> On Tue, May 24, 2016 at 4:30 PM, Rob Landley <rob@landley.net> wrote:
>> >
>> >
>> > On 05/23/2016 06:29 PM, Rob Herring wrote:
>> >> On Mon, May 23, 2016 at 4:03 PM, Rich Felker <dalias@libc.org> wrote:
>> >>> On Mon, May 23, 2016 at 03:48:46PM -0500, Rob Herring wrote:
>> >>>> On Fri, May 20, 2016 at 02:53:03AM +0000, Rich Felker wrote:
>> >>>>> Signed-off-by: Rich Felker <dalias@libc.org>
>> >>>>> ---
>> >>>>> Documentation/devicetree/bindings/jcore/cpus.txt | 91 ++++++++++++++++++++++++
>> >>>>> 1 file changed, 91 insertions(+)
>> >>>>> create mode 100644 Documentation/devicetree/bindings/jcore/cpus.txt
>> >>>>>
>> >>>>> diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
>> >>>>> new file mode 100644
>> >>>>> index 0000000..00ef112
>> >>>>> --- /dev/null
>> >>>>> +++ b/Documentation/devicetree/bindings/jcore/cpus.txt
>> >>>>> @@ -0,0 +1,91 @@
>> >>>>> +===================
>> >>>>> +J-Core cpu bindings
>> >>>>> +===================
>> >>>>> +
>> >>>>> +The J-Core processors are open source CPU cores that can be built as FPGA
>> >>>>> +soft cores or ASICs. The device tree is also responsible for describing the
>> >>>>> +cache controls and, for SMP configurations, all details of the SMP method,
>> >>>>> +as documented below.
>> >>>>> +
>> >>>>> +
>> >>>>> +---------------------
>> >>>>> +Top-level "cpus" node
>> >>>>> +---------------------
>> >>>>> +
>> >>>>> +Required properties:
>> >>>>> +
>> >>>>> +- #address-cells: Must be 1.
>> >>>>> +
>> >>>>> +- #size-cells: Must be 0.
>> >>>>> +
>> >>>>> +Optional properties:
>> >>>>> +
>> >>>>> +- enable-method: Required only for SMP systems. If present, must be
>> >>>>> + "jcore,spin-table".
>> >>>>> +
>> >>>>> +
>> >>>>> +--------------------
>> >>>>> +Individual cpu nodes
>> >>>>> +--------------------
>> >>>>> +
>> >>>>> +Required properties:
>> >>>>> +
>> >>>>> +- device_type: Must be "cpu".
>> >>>>> +
>> >>>>> +- compatible: Must be "jcore,j2".
>> >>>>
>> >>>> Okay to have this, but you should have compatible strings for specific
>> >>>> core implementations. AIUI, J2 is just the ISA.
>> >>>
>> >>> There was some past discussion you probably missed on the linux-sh
>> >>> list, starting here:
>> >>>
>> >>> http://www.spinics.net/lists/linux-sh/msg50028.html
>> >>>
>> >>> Basically it's really hard to identify what "the specific core
>> >>> implementation" even means with a soft core. If you have some ideas
>> >>> I'd be happy to hear them, but I think there should always be a
>> >>> "jcore,j2" fallback compatible tag in any case.
>> >>
>> >> Presumably you do some sort of versioning on the VHDL source that you
>> >> can correlate to.
>> >>
>> >> If you have sufficient s/w accessible version registers that are
>> >> always going to be updated on IP changes then, you don't really need
>> >> more specific compatible strings.
>> >
>> > There are no version registers: the boot ROM can be output as part of
>> > the build, and the dtb can be provided by the boot ROM. So you don't
>> > need boot registers, you literally put any version info you need in the
>> > dtb in the boot rom.
>>
>> You can, but you are not doing that from the looks of it. Maybe you're
>> not to that point to need versioning and that's fine, but it doesn't
>> sound like you all have thought about it.
>
> It's been thought about and discussed both on the linux-sh list and
> internally in the J-Core development process, but it's certainly a
> topic that could use more discussion. I don't think it should be a
> blocking issue for registering current bindings, though.
It's not, I just want to understand the direction and that the need
here is understood.
>> >> Better yet, since you can change "the hardware", make it more
>> >> discoverable with registers for version numbering and feature bits.
>> >> The failure here is having a process where that can be forgotten...
>> >
>> > Why would you add hardware version registers when the hardware's
>> > attached boot rom is providing a dtb?
>> >
>> > What's the point?
>>
>> You are missing who is reading and caring about what the version is.
>> It's all the software that cares what's in either version registers or
>> dtb to know what are the specific features of the h/w. At some point
>> you will have a single driver that needs to support multiple versions
>> and/or configurations of hardware/IP.
>
> This is why we have both "jcore,aic1" and "jcore,aic2" now, and why
> we'll soon have a "jcore,spi3" binding for the new SPI master with DMA
> support. The intent is that stable hardware interfaces are maintained
> at the hardware source level, and the binding names correspond to
> component names in the hardware source.
>
> If there are good reasons for more fine-grained version information,
> we can add binding specifications for such, but the only reason I've
> seen so far is bug workarounds, and it really doesn't make sense to be
> putting bug workarounds in the kernel rather than just fixing the
> source and flashing the FPGA configuration. Once we get to ASICs of
> course it might make sense.
>
> Do you have other compelling reasons for fine-grained versioning?
Differences in features implied by compatible strings is the other
main reason. These would be features that are not configurable as
those you will probably want separate properties for. But if your
going to respin the VHDL to fix any issues, then what you have is
sufficient.
ASIC implementations should have compatible strings tied to the particular ASIC.
Rob
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2016-05-25 13:13 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-05-20 2:53 [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
[not found] ` <cover.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-20 2:53 ` [PATCH v2 01/12] of: add vendor prefix for J-Core Rich Felker
2016-05-23 20:49 ` Rob Herring
2016-05-20 2:53 ` [PATCH v2 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board Rich Felker
[not found] ` <9960d6526523727d1bee3d11c6704e09e600c6fe.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-20 8:17 ` Geert Uytterhoeven
2016-05-20 22:42 ` Rich Felker
2016-05-20 2:53 ` [PATCH v2 02/12] of: add J-Core cpu bindings Rich Felker
[not found] ` <f3c89e4834665790ff13478c571cc9aaa9de5559.1463708766.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-23 20:48 ` Rob Herring
2016-05-23 21:03 ` Rich Felker
2016-05-23 23:29 ` Rob Herring
2016-05-24 2:39 ` Rich Felker
2016-05-24 21:30 ` Rob Landley
2016-05-25 1:13 ` Rob Herring
2016-05-25 2:33 ` Rich Felker
2016-05-25 13:13 ` Rob Herring
2016-05-20 2:53 ` [PATCH v2 03/12] of: add J-Core interrupt controller bindings Rich Felker
2016-05-20 8:04 ` Geert Uytterhoeven
[not found] ` <CAMuHMdVs9=8BGwmCBuYch2abJBnCLKoEx7i3EMghW3UUjXc7dA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-05-20 22:34 ` Rich Felker
2016-05-21 18:07 ` Geert Uytterhoeven
2016-05-21 19:17 ` Rich Felker
2016-05-23 20:53 ` Rob Herring
2016-05-23 21:13 ` Rich Felker
[not found] ` <20160523211342.GG21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
2016-05-24 8:09 ` Marc Zyngier
[not found] ` <57440C45.5040105-5wv7dgnIgG8@public.gmane.org>
2016-05-25 2:25 ` Rich Felker
2016-05-20 2:53 ` [PATCH v2 05/12] of: add J-Core SPI master bindings Rich Felker
2016-05-20 8:05 ` Geert Uytterhoeven
2016-05-23 21:00 ` Rob Herring
2016-05-23 21:06 ` Rich Felker
[not found] ` <20160523210618.GF21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
2016-05-23 23:16 ` Rob Herring
2016-05-20 2:53 ` [PATCH v2 04/12] of: add J-Core timer bindings Rich Felker
2016-05-20 8:03 ` Geert Uytterhoeven
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