Re: [PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree

Kuninori Morimoto
2016-06-17T02:14:50Z

Hi Geert

> > Right, I had forgotten about that.
> > Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)
> >
> > it seems the RCAN clock can just be modeled as a fixed clock. However,
> > its divider value isn't clear to me, as 15.9 MHz cannot be generated from PLL1
> > using an integer divider. Morimoto-san, can you please ask for clarification?
>
> OK.
> Now, I asked to HW team about that.
> Please wait.

RCAN divider is fixed for 1/49

PLL1 (= 1560MHz)
-> 1/2 (= 780MHz)
-> RCAN divider 1/49 (= 15.9183..MHz)

Is this clear for you ?