From mboxrd@z Thu Jan 1 00:00:00 1970 From: megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org Subject: [PATCH v2 10/14] ARM: dts: sun8i: Add r_twi I2C controller Date: Sat, 25 Jun 2016 05:45:07 +0200 Message-ID: <20160625034511.7966-11-megous@megous.com> References: <20160625034511.7966-1-megous@megous.com> Reply-To: megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20160625034511.7966-1-megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: dev-3kdeTeqwOZ9EV1b7eY7vFQ@public.gmane.org Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Ondrej Jirman , Rob Herring , Mark Rutland , Russell King , Maxime Ripard , Chen-Yu Tsai , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list List-Id: devicetree@vger.kernel.org From: Ondrej Jirman H3 SoC contains I2C controller optionally available on the PL0 and PL1 pins. This patch makes this controller available. Signed-off-by: Ondrej Jirman --- arch/arm/boot/dts/sun8i-h3.dtsi | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 56f211e..e32f211 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -322,8 +322,9 @@ reg = <0x01f01428 0x4>; #clock-cells = <1>; clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; + clock-indices = <0>, <1>, <6>; + clock-output-names = "apb0_pio", "apb0_ir", "apb0_i2c"; + }; ir_clk: ir_clk@01f01454 { @@ -656,6 +657,20 @@ status = "disabled"; }; + r_twi: i2c@01f02400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01f02400 0x400>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_twi_pins_a>; + clocks = <&apb0_gates 6>; + clock-frequency = <100000>; + resets = <&apb0_reset 6>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, @@ -707,6 +722,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + r_twi_pins_a: r_twi@0 { + allwinner,pins = "PL0", "PL1"; + allwinner,function = "s_twi"; + allwinner,drive = ; + allwinner,pull = ; + }; }; }; }; -- 2.9.0