From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v5 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk Date: Thu, 30 Jun 2016 21:38:25 -0500 Message-ID: <20160701023825.GA27978@rob-hp-laptop> References: <1467285176-25222-1-git-send-email-william.wu@rock-chips.com> <1467285176-25222-5-git-send-email-william.wu@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1467285176-25222-5-git-send-email-william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: William Wu Cc: huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org, balbi-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org, sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org, linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org, dianders-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, eddie.cai-TNX95d0MmH7DzftRWevZcw@public.gmane.org, briannorris-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, John.Youn-HKixBCOQz3hWk0Htik3J/w@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On Thu, Jun 30, 2016 at 07:12:55PM +0800, William Wu wrote: > Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit, > which specifies whether disable delay PHY power change > from P0 to P1/P2/P3 when link state changing from U0 > to U1/U2/U3 respectively. > > Signed-off-by: William Wu > --- > Changes in v5: > - None > > Changes in v4: > - rebase on top of balbi testing/next, remove pdata (balbi) > > Changes in v3: > - None > > Changes in v2: > - None > > Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++ > drivers/usb/dwc3/core.c | 5 +++++ > drivers/usb/dwc3/core.h | 3 +++ > 3 files changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt > index 34d13a5..bd5bef0 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt > @@ -42,6 +42,8 @@ Optional properties: > - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists > in GUSB2PHYCFG, specify that USB2 PHY doesn't provide > a free-running PHY clock. > + - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power > + from P0 to P1/P2/P3 without delay. Use '-', not '_'. > - snps,phyif_utmi_quirk: when set core will set phyif UTMI+ interface. > - snps,phyif_utmi: the value to configure the core to support a UTMI+ PHY > with an 8- or 16-bit interface. Value 0 select 8-bit