From: Rich Felker <dalias@libc.org>
To: Rob Herring <robh@kernel.org>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
SH-Linux <linux-sh@vger.kernel.org>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Mark Rutland <mark.rutland@arm.com>,
Pawel Moll <pawel.moll@arm.com>
Subject: Re: [PATCH v3 04/12] of: add J-Core timer bindings
Date: Thu, 14 Jul 2016 18:18:08 -0400 [thread overview]
Message-ID: <20160714221808.GP15995@brightrain.aerifal.cx> (raw)
In-Reply-To: <20160623211608.GA10893@brightrain.aerifal.cx>
On Thu, Jun 23, 2016 at 05:16:08PM -0400, Rich Felker wrote:
> On Thu, Jun 02, 2016 at 05:44:25PM -0500, Rob Herring wrote:
> > > > > In theory it would even be possible to just require a DT node per
> > > > > cpulocal timer, but I didn't see a good way to make the bindings
> > > > > represent the relationship to cpus or to make the driver handle irqs
> > > > > correctly for such a setup, so I'd need a viable proposal for how that
> > > > > could be done to even consider such an approach.
> > > >
> > > > Yeah, there's not really a standard way to map per cpu blocks to cpus.
> > > > We could, but doesn't really seem necessary here.
> > > >
> > > > For the irqs, percpu irqs doesn't help you?
> > >
> > > What I mean is that, if there were a separate device node and driver
> > > instance per cpu, they'd all want to register the same irq just to
> > > handle it on their own cpu, so we'd have a lot of spurious handlers
> > > running. The right way to model this, I think, would be as a virtual
> > > irqchip that's the irq parent of all the timer nodes, and that
> > > multiplexes the real irq to one virq per cpu (where the current cpu id
> > > becomes the irq number in its irq domain). But that's a lot of virtual
> > > infrastructure just for the sake of modelling each percpu timer as its
> > > own DT node and I don't think it makes sense to do it that way.
> >
> > I would have thought your interrupt controller did all this. On the ARM
> > GIC for example, you have the same irq number but there is a per cpu
> > interface and really N (== # cpus) physical irq lines.
>
> I've looked at the ARM GIC code and bindings and I don't see where the
> per-cpu interrupt interfaces are modelled with multiple interrupt
> controller nodes or irq domains. It looks to me like it just uses a
> single interrupt controller/domain with percpu irq. Does that match
> your understanding?
Ping.
I want to submit this again for the upcoming merge window and need to
know whether you still want me to pursue different approaches.
Rich
next prev parent reply other threads:[~2016-07-14 22:18 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-25 5:43 [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
2016-05-25 5:43 ` [PATCH v3 01/12] of: add vendor prefix for J-Core Rich Felker
2016-05-25 13:18 ` Rob Herring
2016-07-27 5:31 ` Rich Felker
2016-08-04 22:27 ` Rich Felker
[not found] ` <20160804222757.GO15995-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
2016-08-30 21:13 ` Rob Herring
2016-05-25 5:43 ` [PATCH v3 05/12] of: add J-Core SPI master bindings Rich Felker
2016-05-25 19:04 ` Rob Herring
2016-05-25 5:43 ` [PATCH v3 03/12] of: add J-Core interrupt controller bindings Rich Felker
2016-05-25 10:25 ` Mark Rutland
2016-05-25 23:08 ` Rich Felker
2016-05-25 5:43 ` [PATCH v3 02/12] of: add J-Core cpu bindings Rich Felker
[not found] ` <39ad5c69533ef537e6ab0426efc057f9064ee581.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-25 10:22 ` Mark Rutland
2016-05-25 23:04 ` Rich Felker
2016-05-26 7:54 ` Geert Uytterhoeven
2016-05-26 10:38 ` Mark Rutland
2016-05-26 15:33 ` Rich Felker
[not found] ` <20160526153323.GX21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
2016-05-27 9:13 ` Mark Rutland
2016-05-26 21:44 ` Rob Landley
[not found] ` <57476E22.6010000-VoJi6FS/r0vR7s880joybQ@public.gmane.org>
2016-05-27 11:51 ` Afzal Mohammed
2016-05-25 5:43 ` [PATCH v3 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board Rich Felker
[not found] ` <3d6f6fd6d674942a6446b0a14d9877017c53eb2f.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-25 10:33 ` Mark Rutland
2016-05-25 23:15 ` Rich Felker
2016-05-26 10:39 ` Mark Rutland
2016-05-25 5:43 ` [PATCH v3 04/12] of: add J-Core timer bindings Rich Felker
2016-06-01 13:58 ` Rob Herring
2016-06-01 17:53 ` Rich Felker
2016-06-01 21:53 ` Rich Felker
2016-06-01 22:36 ` Rob Herring
2016-06-02 1:34 ` Rich Felker
2016-06-02 22:44 ` Rob Herring
2016-06-23 21:16 ` Rich Felker
2016-07-14 22:18 ` Rich Felker [this message]
[not found] ` <cover.1464148904.git.dalias-8zAoT0mYgF4@public.gmane.org>
2016-05-25 7:22 ` [PATCH v3 00/12] J-core J2 cpu and SoC peripherals support Geert Uytterhoeven
2016-05-25 9:54 ` Mark Brown
2016-05-25 22:24 ` Rich Felker
[not found] ` <20160525222441.GS21636-C3MtFaGISjmo6RMmaWD+6Sb1p8zYI1N1@public.gmane.org>
2016-05-26 0:42 ` Mark Brown
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