[PATCH v2 0/5] mmc: sunxi: sun4i / sun5i do not have sample clocks

[PATCH v2 0/5] mmc: sunxi: sun4i / sun5i do not have sample clocks

[Hans de Goede]

Hi Ulf, Maxime and Chen-Yu,

Here is v2 of my patch set to deal with sun4i / sun5i not having
mmc sample clocks, this time introducing a new sun7i-a20-mmc
compatible for the models which do have sample clks, as discussed
in the review of v1 of this set.

Ulf, can you please add patches 1-4 to your tree for 4.9, and
Maxime can you please pick up patch 5 ?

Thanks & Regards,

Hans

[PATCH v2 1/5] mmc: sunxi: Disable sample clks on remove

[Hans de Goede]

When support for the sample clks was added calls to prepare_enable
were added to the probe path, but matching calls to disable_unprepare
were forgotten in the remove path, this fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
-No changes
---
 drivers/mmc/host/sunxi-mmc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index a4d2b63..71a480b 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1160,6 +1160,8 @@ static int sunxi_mmc_remove(struct platform_device *pdev)
 	if (!IS_ERR(host->reset))
 		reset_control_assert(host->reset);
 
+	clk_disable_unprepare(host->clk_sample);
+	clk_disable_unprepare(host->clk_output);
 	clk_disable_unprepare(host->clk_mmc);
 	clk_disable_unprepare(host->clk_ahb);
 
-- 
2.7.4

Re: [PATCH v2 1/5] mmc: sunxi: Disable sample clks on remove

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 512 bytes --]

On Sat, Jul 30, 2016 at 04:25:44PM +0200, Hans de Goede wrote:
> When support for the sample clks was added calls to prepare_enable
> were added to the probe path, but matching calls to disable_unprepare
> were forgotten in the remove path, this fixes this.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks,
Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH v2 2/5] mmc: sunxi: Introduce a sunxi_mmc_cfg struct

[Hans de Goede]

Create a struct to hold the various model / compatible string dependend
settings.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
-New patch in v2 of this patch-set
---
 drivers/mmc/host/sunxi-mmc.c | 77 ++++++++++++++++++++++++++------------------
 1 file changed, 45 insertions(+), 32 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 71a480b..9f44c83 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -229,9 +229,15 @@ struct sunxi_idma_des {
 	u32	buf_addr_ptr2;
 };
 
+struct sunxi_mmc_cfg {
+	u32 idma_des_size_bits;
+	const struct sunxi_mmc_clk_delay *clk_delays;
+};
+
 struct sunxi_mmc_host {
 	struct mmc_host	*mmc;
 	struct reset_control *reset;
+	const struct sunxi_mmc_cfg *cfg;
 
 	/* IO mapping base */
 	void __iomem	*reg_base;
@@ -241,7 +247,6 @@ struct sunxi_mmc_host {
 	struct clk	*clk_mmc;
 	struct clk	*clk_sample;
 	struct clk	*clk_output;
-	const struct sunxi_mmc_clk_delay *clk_delays;
 
 	/* irq */
 	spinlock_t	lock;
@@ -250,7 +255,6 @@ struct sunxi_mmc_host {
 	u32		sdio_imask;
 
 	/* dma */
-	u32		idma_des_size_bits;
 	dma_addr_t	sg_dma;
 	void		*sg_cpu;
 	bool		wait_dma;
@@ -322,7 +326,7 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 {
 	struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
 	dma_addr_t next_desc = host->sg_dma;
-	int i, max_len = (1 << host->idma_des_size_bits);
+	int i, max_len = (1 << host->cfg->idma_des_size_bits);
 
 	for (i = 0; i < data->sg_len; i++) {
 		pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
@@ -656,6 +660,7 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 				  struct mmc_ios *ios)
 {
+	const struct sunxi_mmc_clk_delay *clk_delays = host->cfg->clk_delays;
 	u32 rate, oclk_dly, rval, sclk_dly;
 	u32 clock = ios->clock;
 	int ret;
@@ -694,22 +699,22 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 
 	/* determine delays */
 	if (rate <= 400000) {
-		oclk_dly = host->clk_delays[SDXC_CLK_400K].output;
-		sclk_dly = host->clk_delays[SDXC_CLK_400K].sample;
+		oclk_dly = clk_delays[SDXC_CLK_400K].output;
+		sclk_dly = clk_delays[SDXC_CLK_400K].sample;
 	} else if (rate <= 25000000) {
-		oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
-		sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
+		oclk_dly = clk_delays[SDXC_CLK_25M].output;
+		sclk_dly = clk_delays[SDXC_CLK_25M].sample;
 	} else if (rate <= 52000000) {
 		if (ios->timing != MMC_TIMING_UHS_DDR50 &&
 		    ios->timing != MMC_TIMING_MMC_DDR52) {
-			oclk_dly = host->clk_delays[SDXC_CLK_50M].output;
-			sclk_dly = host->clk_delays[SDXC_CLK_50M].sample;
+			oclk_dly = clk_delays[SDXC_CLK_50M].output;
+			sclk_dly = clk_delays[SDXC_CLK_50M].sample;
 		} else if (ios->bus_width == MMC_BUS_WIDTH_8) {
-			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
-			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
+			oclk_dly = clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
+			sclk_dly = clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
 		} else {
-			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
-			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
+			oclk_dly = clk_delays[SDXC_CLK_50M_DDR].output;
+			sclk_dly = clk_delays[SDXC_CLK_50M_DDR].sample;
 		}
 	} else {
 		return -EINVAL;
@@ -938,14 +943,6 @@ static int sunxi_mmc_card_busy(struct mmc_host *mmc)
 	return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
 }
 
-static const struct of_device_id sunxi_mmc_of_match[] = {
-	{ .compatible = "allwinner,sun4i-a10-mmc", },
-	{ .compatible = "allwinner,sun5i-a13-mmc", },
-	{ .compatible = "allwinner,sun9i-a80-mmc", },
-	{ /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
-
 static struct mmc_host_ops sunxi_mmc_ops = {
 	.request	 = sunxi_mmc_request,
 	.set_ios	 = sunxi_mmc_set_ios,
@@ -974,21 +971,37 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
 	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  72, .sample =  72 },
 };
 
+static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
+	.idma_des_size_bits = 13,
+	.clk_delays = sunxi_mmc_clk_delays,
+};
+
+static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
+	.idma_des_size_bits = 16,
+	.clk_delays = sunxi_mmc_clk_delays,
+};
+
+static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
+	.idma_des_size_bits = 16,
+	.clk_delays = sun9i_mmc_clk_delays,
+};
+
+static const struct of_device_id sunxi_mmc_of_match[] = {
+	{ .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
+	{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
+	{ .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
+
 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
 				      struct platform_device *pdev)
 {
-	struct device_node *np = pdev->dev.of_node;
 	int ret;
 
-	if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
-		host->idma_des_size_bits = 13;
-	else
-		host->idma_des_size_bits = 16;
-
-	if (of_device_is_compatible(np, "allwinner,sun9i-a80-mmc"))
-		host->clk_delays = sun9i_mmc_clk_delays;
-	else
-		host->clk_delays = sunxi_mmc_clk_delays;
+	host->cfg = of_device_get_match_data(&pdev->dev);
+	if (!host->cfg)
+		return -EINVAL;
 
 	ret = mmc_regulator_get_supply(host->mmc);
 	if (ret) {
@@ -1120,7 +1133,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 	mmc->max_blk_count	= 8192;
 	mmc->max_blk_size	= 4096;
 	mmc->max_segs		= PAGE_SIZE / sizeof(struct sunxi_idma_des);
-	mmc->max_seg_size	= (1 << host->idma_des_size_bits);
+	mmc->max_seg_size	= (1 << host->cfg->idma_des_size_bits);
 	mmc->max_req_size	= mmc->max_seg_size * mmc->max_segs;
 	/* 400kHz ~ 52MHz */
 	mmc->f_min		=   400000;
-- 
2.7.4

Re: [PATCH v2 2/5] mmc: sunxi: Introduce a sunxi_mmc_cfg struct

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 395 bytes --]

On Sat, Jul 30, 2016 at 04:25:45PM +0200, Hans de Goede wrote:
> Create a struct to hold the various model / compatible string dependend
> settings.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks,
Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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[PATCH v2 3/5] mmc: sunxi: Factor out clock phase setting code into a helper function

[Hans de Goede]

Add a sunxi_mmc_clk_set_phase() helper function.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
-New patch in v2 of this patch-set
---
 drivers/mmc/host/sunxi-mmc.c | 61 ++++++++++++++++++++++++--------------------
 1 file changed, 33 insertions(+), 28 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 9f44c83..b631b5c 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -657,12 +657,39 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
 	return 0;
 }
 
+static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
+				   struct mmc_ios *ios, u32 rate)
+{
+	int index;
+
+	/* determine delays */
+	if (rate <= 400000) {
+		index = SDXC_CLK_400K;
+	} else if (rate <= 25000000) {
+		index = SDXC_CLK_25M;
+	} else if (rate <= 52000000) {
+		if (ios->timing != MMC_TIMING_UHS_DDR50 &&
+		    ios->timing != MMC_TIMING_MMC_DDR52) {
+			index = SDXC_CLK_50M;
+		} else if (ios->bus_width == MMC_BUS_WIDTH_8) {
+			index = SDXC_CLK_50M_DDR_8BIT;
+		} else {
+			index = SDXC_CLK_50M_DDR;
+		}
+	} else {
+		return -EINVAL;
+	}
+
+	clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
+	clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
+
+	return 0;
+}
+
 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 				  struct mmc_ios *ios)
 {
-	const struct sunxi_mmc_clk_delay *clk_delays = host->cfg->clk_delays;
-	u32 rate, oclk_dly, rval, sclk_dly;
-	u32 clock = ios->clock;
+	u32 rate, rval, clock = ios->clock;
 	int ret;
 
 	/* 8 bit DDR requires a higher module clock */
@@ -697,31 +724,9 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 	}
 	mmc_writel(host, REG_CLKCR, rval);
 
-	/* determine delays */
-	if (rate <= 400000) {
-		oclk_dly = clk_delays[SDXC_CLK_400K].output;
-		sclk_dly = clk_delays[SDXC_CLK_400K].sample;
-	} else if (rate <= 25000000) {
-		oclk_dly = clk_delays[SDXC_CLK_25M].output;
-		sclk_dly = clk_delays[SDXC_CLK_25M].sample;
-	} else if (rate <= 52000000) {
-		if (ios->timing != MMC_TIMING_UHS_DDR50 &&
-		    ios->timing != MMC_TIMING_MMC_DDR52) {
-			oclk_dly = clk_delays[SDXC_CLK_50M].output;
-			sclk_dly = clk_delays[SDXC_CLK_50M].sample;
-		} else if (ios->bus_width == MMC_BUS_WIDTH_8) {
-			oclk_dly = clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
-			sclk_dly = clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
-		} else {
-			oclk_dly = clk_delays[SDXC_CLK_50M_DDR].output;
-			sclk_dly = clk_delays[SDXC_CLK_50M_DDR].sample;
-		}
-	} else {
-		return -EINVAL;
-	}
-
-	clk_set_phase(host->clk_sample, sclk_dly);
-	clk_set_phase(host->clk_output, oclk_dly);
+	ret = sunxi_mmc_clk_set_phase(host, ios, rate);
+	if (ret)
+		return ret;
 
 	return sunxi_mmc_oclk_onoff(host, 1);
 }
-- 
2.7.4

Re: [PATCH v2 3/5] mmc: sunxi: Factor out clock phase setting code into a helper function

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 359 bytes --]

On Sat, Jul 30, 2016 at 04:25:46PM +0200, Hans de Goede wrote:
> Add a sunxi_mmc_clk_set_phase() helper function.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks,
Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v2 3/5] mmc: sunxi: Factor out clock phase setting code into a helper function

[Icenowy Zheng]

30.07.2016, 22:26, "Hans de Goede" <hdegoede@redhat.com>:
> Add a sunxi_mmc_clk_set_phase() helper function.
Thanks! It's useful for A64 MMC implementation.

>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> Changes in v2:
> -New patch in v2 of this patch-set
> ---
>  drivers/mmc/host/sunxi-mmc.c | 61 ++++++++++++++++++++++++--------------------
>  1 file changed, 33 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 9f44c83..b631b5c 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -657,12 +657,39 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
>          return 0;
>  }
>
> +static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
> + struct mmc_ios *ios, u32 rate)
> +{
> + int index;
> +
> + /* determine delays */
> + if (rate <= 400000) {
> + index = SDXC_CLK_400K;
> + } else if (rate <= 25000000) {
> + index = SDXC_CLK_25M;
> + } else if (rate <= 52000000) {
> + if (ios->timing != MMC_TIMING_UHS_DDR50 &&
> + ios->timing != MMC_TIMING_MMC_DDR52) {
> + index = SDXC_CLK_50M;
> + } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
> + index = SDXC_CLK_50M_DDR_8BIT;
> + } else {
> + index = SDXC_CLK_50M_DDR;
> + }
> + } else {
> + return -EINVAL;
> + }
> +
> + clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
> + clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
> +
> + return 0;
> +}
> +
>  static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
>                                    struct mmc_ios *ios)
>  {
> - const struct sunxi_mmc_clk_delay *clk_delays = host->cfg->clk_delays;
> - u32 rate, oclk_dly, rval, sclk_dly;
> - u32 clock = ios->clock;
> + u32 rate, rval, clock = ios->clock;
>          int ret;
>
>          /* 8 bit DDR requires a higher module clock */
> @@ -697,31 +724,9 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
>          }
>          mmc_writel(host, REG_CLKCR, rval);
>
> - /* determine delays */
> - if (rate <= 400000) {
> - oclk_dly = clk_delays[SDXC_CLK_400K].output;
> - sclk_dly = clk_delays[SDXC_CLK_400K].sample;
> - } else if (rate <= 25000000) {
> - oclk_dly = clk_delays[SDXC_CLK_25M].output;
> - sclk_dly = clk_delays[SDXC_CLK_25M].sample;
> - } else if (rate <= 52000000) {
> - if (ios->timing != MMC_TIMING_UHS_DDR50 &&
> - ios->timing != MMC_TIMING_MMC_DDR52) {
> - oclk_dly = clk_delays[SDXC_CLK_50M].output;
> - sclk_dly = clk_delays[SDXC_CLK_50M].sample;
> - } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
> - oclk_dly = clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
> - sclk_dly = clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
> - } else {
> - oclk_dly = clk_delays[SDXC_CLK_50M_DDR].output;
> - sclk_dly = clk_delays[SDXC_CLK_50M_DDR].sample;
> - }
> - } else {
> - return -EINVAL;
> - }
> -
> - clk_set_phase(host->clk_sample, sclk_dly);
> - clk_set_phase(host->clk_output, oclk_dly);
> + ret = sunxi_mmc_clk_set_phase(host, ios, rate);
> + if (ret)
> + return ret;
>
>          return sunxi_mmc_oclk_onoff(host, 1);
>  }
> --
> 2.7.4

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[PATCH v2 4/5] mmc: sunxi: sun4i / sun5i do not have sample clocks

[Hans de Goede]

It turns out that sun4i (A10) and sun5i (A13 & co) do not have sample
clocks, so add a new sun7i-a20-mmc compatible and do not try to use
sample clocks on sun4i / sun5i.

Since sun4i / sun5i do not have sample clocks, they cannot (reliably) do
DDR rates, so only set MMC_CAP_1_8V_DDR when we do have sample clks.

Note this patch leaves the clk_prepare_enable() / clk_disable_unprepare()
calls to the sample clks as-is, without adding checks for them being
NULL. All the clk_foo calls accept a NULL clk and will return success when
called with a NULL clk.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
-Add a new sun7i-a20-compatible for SoCs with sample clks, rather then
 making them optional
---
 .../devicetree/bindings/mmc/sunxi-mmc.txt          |  6 +++-
 drivers/mmc/host/sunxi-mmc.c                       | 35 +++++++++++++++-------
 2 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 4bf41d8..904ff9f 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -8,7 +8,11 @@ as the speed of SD standard 3.0.
 Absolute maximum transfer rate is 200MB/s
 
 Required properties:
- - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc"
+ - compatible : should be one of:
+   * "allwinner,sun4i-a10-mmc"
+   * "allwinner,sun5i-a13-mmc"
+   * "allwinner,sun7i-a20-mmc"
+   * "allwinner,sun9i-a80-mmc"
  - reg : mmc controller base registers
  - clocks : a list with 4 phandle + clock specifier pairs
  - clock-names : must contain "ahb", "mmc", "output" and "sample"
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index b631b5c..dcc208c 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -662,6 +662,9 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
 {
 	int index;
 
+	if (!host->cfg->clk_delays)
+		return 0;
+
 	/* determine delays */
 	if (rate <= 400000) {
 		index = SDXC_CLK_400K;
@@ -978,11 +981,16 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
 
 static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
 	.idma_des_size_bits = 13,
-	.clk_delays = sunxi_mmc_clk_delays,
+	.clk_delays = NULL,
 };
 
 static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
 	.idma_des_size_bits = 16,
+	.clk_delays = NULL,
+};
+
+static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
+	.idma_des_size_bits = 16,
 	.clk_delays = sunxi_mmc_clk_delays,
 };
 
@@ -994,6 +1002,7 @@ static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
 static const struct of_device_id sunxi_mmc_of_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
+	{ .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
 	{ .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
 	{ /* sentinel */ }
 };
@@ -1032,16 +1041,18 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
 		return PTR_ERR(host->clk_mmc);
 	}
 
-	host->clk_output = devm_clk_get(&pdev->dev, "output");
-	if (IS_ERR(host->clk_output)) {
-		dev_err(&pdev->dev, "Could not get output clock\n");
-		return PTR_ERR(host->clk_output);
-	}
+	if (host->cfg->clk_delays) {
+		host->clk_output = devm_clk_get(&pdev->dev, "output");
+		if (IS_ERR(host->clk_output)) {
+			dev_err(&pdev->dev, "Could not get output clock\n");
+			return PTR_ERR(host->clk_output);
+		}
 
-	host->clk_sample = devm_clk_get(&pdev->dev, "sample");
-	if (IS_ERR(host->clk_sample)) {
-		dev_err(&pdev->dev, "Could not get sample clock\n");
-		return PTR_ERR(host->clk_sample);
+		host->clk_sample = devm_clk_get(&pdev->dev, "sample");
+		if (IS_ERR(host->clk_sample)) {
+			dev_err(&pdev->dev, "Could not get sample clock\n");
+			return PTR_ERR(host->clk_sample);
+		}
 	}
 
 	host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
@@ -1144,9 +1155,11 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 	mmc->f_min		=   400000;
 	mmc->f_max		= 52000000;
 	mmc->caps	       |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-				  MMC_CAP_1_8V_DDR |
 				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
 
+	if (host->cfg->clk_delays)
+		mmc->caps      |= MMC_CAP_1_8V_DDR;
+
 	ret = mmc_of_parse(mmc);
 	if (ret)
 		goto error_free_dma;
-- 
2.7.4

Re: [PATCH v2 4/5] mmc: sunxi: sun4i / sun5i do not have sample clocks

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 896 bytes --]

On Sat, Jul 30, 2016 at 04:25:47PM +0200, Hans de Goede wrote:
> It turns out that sun4i (A10) and sun5i (A13 & co) do not have sample
> clocks, so add a new sun7i-a20-mmc compatible and do not try to use
> sample clocks on sun4i / sun5i.
> 
> Since sun4i / sun5i do not have sample clocks, they cannot (reliably) do
> DDR rates, so only set MMC_CAP_1_8V_DDR when we do have sample clks.
> 
> Note this patch leaves the clk_prepare_enable() / clk_disable_unprepare()
> calls to the sample clks as-is, without adding checks for them being
> NULL. All the clk_foo calls accept a NULL clk and will return success when
> called with a NULL clk.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v2 4/5] mmc: sunxi: sun4i / sun5i do not have sample clocks

[Rob Herring]

On Sat, Jul 30, 2016 at 04:25:47PM +0200, Hans de Goede wrote:
> It turns out that sun4i (A10) and sun5i (A13 & co) do not have sample
> clocks, so add a new sun7i-a20-mmc compatible and do not try to use
> sample clocks on sun4i / sun5i.
> 
> Since sun4i / sun5i do not have sample clocks, they cannot (reliably) do
> DDR rates, so only set MMC_CAP_1_8V_DDR when we do have sample clks.
> 
> Note this patch leaves the clk_prepare_enable() / clk_disable_unprepare()
> calls to the sample clks as-is, without adding checks for them being
> NULL. All the clk_foo calls accept a NULL clk and will return success when
> called with a NULL clk.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> Changes in v2:
> -Add a new sun7i-a20-compatible for SoCs with sample clks, rather then
>  making them optional
> ---
>  .../devicetree/bindings/mmc/sunxi-mmc.txt          |  6 +++-

I find the subject a bit strange as it should describe the change, not 
the problem. Otherwise,

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/mmc/host/sunxi-mmc.c                       | 35 +++++++++++++++-------
>  2 files changed, 29 insertions(+), 12 deletions(-)

[PATCH v2 5/5] ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newer

[Hans de Goede]

Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
and newer.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
-New patch in v2 of this patch-set
---
 arch/arm/boot/dts/sun6i-a31.dtsi     | 8 ++++----
 arch/arm/boot/dts/sun7i-a20.dtsi     | 8 ++++----
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 +++---
 arch/arm/boot/dts/sun8i-h3.dtsi      | 6 +++---
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 1867af2..0d24f10 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -469,7 +469,7 @@
 		};
 
 		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&ahb1_gates 8>,
 				 <&mmc0_clk 0>,
@@ -488,7 +488,7 @@
 		};
 
 		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&ahb1_gates 9>,
 				 <&mmc1_clk 0>,
@@ -507,7 +507,7 @@
 		};
 
 		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&ahb1_gates 10>,
 				 <&mmc2_clk 0>,
@@ -526,7 +526,7 @@
 		};
 
 		mmc3: mmc@01c12000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c12000 0x1000>;
 			clocks = <&ahb1_gates 11>,
 				 <&mmc3_clk 0>,
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index bd0c476..94cf5a1 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -905,7 +905,7 @@
 		};
 
 		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&ahb_gates 8>,
 				 <&mmc0_clk 0>,
@@ -922,7 +922,7 @@
 		};
 
 		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&ahb_gates 9>,
 				 <&mmc1_clk 0>,
@@ -939,7 +939,7 @@
 		};
 
 		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&ahb_gates 10>,
 				 <&mmc2_clk 0>,
@@ -956,7 +956,7 @@
 		};
 
 		mmc3: mmc@01c12000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c12000 0x1000>;
 			clocks = <&ahb_gates 11>,
 				 <&mmc3_clk 0>,
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7e05e09..e3b196e 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -266,7 +266,7 @@
 		};
 
 		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&ahb1_gates 8>,
 				 <&mmc0_clk 0>,
@@ -285,7 +285,7 @@
 		};
 
 		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&ahb1_gates 9>,
 				 <&mmc1_clk 0>,
@@ -304,7 +304,7 @@
 		};
 
 		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&ahb1_gates 10>,
 				 <&mmc2_clk 0>,
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 93c88f3..b5cc2dc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -154,7 +154,7 @@
 		};
 
 		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC0>,
 				 <&ccu CLK_MMC0>,
@@ -173,7 +173,7 @@
 		};
 
 		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC1>,
 				 <&ccu CLK_MMC1>,
@@ -192,7 +192,7 @@
 		};
 
 		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun7i-a20-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&ccu CLK_BUS_MMC2>,
 				 <&ccu CLK_MMC2>,
-- 
2.7.4

Re: [PATCH v2 5/5] ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newer

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 527 bytes --]

On Sat, Jul 30, 2016 at 04:25:48PM +0200, Hans de Goede wrote:
> Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
> and newer.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

This should probably go through Ulf tree together with the rest of
that serie to maintain the bisectability.

Thanks a lot for this work,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #1.2: signature.asc --]
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Re: [PATCH v2 5/5] ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newer

[Hans de Goede]

Hi,

On 30-07-16 17:16, Maxime Ripard wrote:
> On Sat, Jul 30, 2016 at 04:25:48PM +0200, Hans de Goede wrote:
>> Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
>> and newer.
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> This should probably go through Ulf tree together with the rest of
> that serie to maintain the bisectability.

This going through Ulf's tree is fine with me, and indeed seems best, ack.

Regards,

Hans

Re: [PATCH v2 5/5] ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newer

[Andre Przywara]

Hi Hans,

On 30/07/16 15:25, Hans de Goede wrote:
> Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
> and newer.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
> Changes in v2:
> -New patch in v2 of this patch-set
> ---
>  arch/arm/boot/dts/sun6i-a31.dtsi     | 8 ++++----
>  arch/arm/boot/dts/sun7i-a20.dtsi     | 8 ++++----
>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 +++---
>  arch/arm/boot/dts/sun8i-h3.dtsi      | 6 +++---
>  4 files changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index 1867af2..0d24f10 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -469,7 +469,7 @@
>  		};
>  
>  		mmc0: mmc@01c0f000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";

But that breaks systems with newer DTs on older kernels, which do not
know about sun7i-a20-mmc. I assume this somehow worked before(?), so why
not use:
	compatible = "allwinner,sun7i-a20-mmc",
		     "allwinner,sun5i-a13-mmc";

So newer kernels would pick up the new name and behaviour, while older
kernels would revert to the old name and use the existing driver.

Cheers,
Andre.

>  			reg = <0x01c0f000 0x1000>;
>  			clocks = <&ahb1_gates 8>,
>  				 <&mmc0_clk 0>,
> @@ -488,7 +488,7 @@
>  		};
>  
>  		mmc1: mmc@01c10000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c10000 0x1000>;
>  			clocks = <&ahb1_gates 9>,
>  				 <&mmc1_clk 0>,
> @@ -507,7 +507,7 @@
>  		};
>  
>  		mmc2: mmc@01c11000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c11000 0x1000>;
>  			clocks = <&ahb1_gates 10>,
>  				 <&mmc2_clk 0>,
> @@ -526,7 +526,7 @@
>  		};
>  
>  		mmc3: mmc@01c12000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c12000 0x1000>;
>  			clocks = <&ahb1_gates 11>,
>  				 <&mmc3_clk 0>,
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index bd0c476..94cf5a1 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -905,7 +905,7 @@
>  		};
>  
>  		mmc0: mmc@01c0f000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c0f000 0x1000>;
>  			clocks = <&ahb_gates 8>,
>  				 <&mmc0_clk 0>,
> @@ -922,7 +922,7 @@
>  		};
>  
>  		mmc1: mmc@01c10000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c10000 0x1000>;
>  			clocks = <&ahb_gates 9>,
>  				 <&mmc1_clk 0>,
> @@ -939,7 +939,7 @@
>  		};
>  
>  		mmc2: mmc@01c11000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c11000 0x1000>;
>  			clocks = <&ahb_gates 10>,
>  				 <&mmc2_clk 0>,
> @@ -956,7 +956,7 @@
>  		};
>  
>  		mmc3: mmc@01c12000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c12000 0x1000>;
>  			clocks = <&ahb_gates 11>,
>  				 <&mmc3_clk 0>,
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index 7e05e09..e3b196e 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -266,7 +266,7 @@
>  		};
>  
>  		mmc0: mmc@01c0f000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c0f000 0x1000>;
>  			clocks = <&ahb1_gates 8>,
>  				 <&mmc0_clk 0>,
> @@ -285,7 +285,7 @@
>  		};
>  
>  		mmc1: mmc@01c10000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c10000 0x1000>;
>  			clocks = <&ahb1_gates 9>,
>  				 <&mmc1_clk 0>,
> @@ -304,7 +304,7 @@
>  		};
>  
>  		mmc2: mmc@01c11000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c11000 0x1000>;
>  			clocks = <&ahb1_gates 10>,
>  				 <&mmc2_clk 0>,
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 93c88f3..b5cc2dc 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -154,7 +154,7 @@
>  		};
>  
>  		mmc0: mmc@01c0f000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c0f000 0x1000>;
>  			clocks = <&ccu CLK_BUS_MMC0>,
>  				 <&ccu CLK_MMC0>,
> @@ -173,7 +173,7 @@
>  		};
>  
>  		mmc1: mmc@01c10000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c10000 0x1000>;
>  			clocks = <&ccu CLK_BUS_MMC1>,
>  				 <&ccu CLK_MMC1>,
> @@ -192,7 +192,7 @@
>  		};
>  
>  		mmc2: mmc@01c11000 {
> -			compatible = "allwinner,sun5i-a13-mmc";
> +			compatible = "allwinner,sun7i-a20-mmc";
>  			reg = <0x01c11000 0x1000>;
>  			clocks = <&ccu CLK_BUS_MMC2>,
>  				 <&ccu CLK_MMC2>,
> 

Re: [PATCH v2 5/5] ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newer

[Hans de Goede]

Hi,

On 01-08-16 15:11, Andre Przywara wrote:
> Hi Hans,
>
> On 30/07/16 15:25, Hans de Goede wrote:
>> Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
>> and newer.
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> Changes in v2:
>> -New patch in v2 of this patch-set
>> ---
>>  arch/arm/boot/dts/sun6i-a31.dtsi     | 8 ++++----
>>  arch/arm/boot/dts/sun7i-a20.dtsi     | 8 ++++----
>>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 +++---
>>  arch/arm/boot/dts/sun8i-h3.dtsi      | 6 +++---
>>  4 files changed, 14 insertions(+), 14 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
>> index 1867af2..0d24f10 100644
>> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
>> @@ -469,7 +469,7 @@
>>  		};
>>
>>  		mmc0: mmc@01c0f000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>
> But that breaks systems with newer DTs on older kernels, which do not
> know about sun7i-a20-mmc. I assume this somehow worked before(?), so why
> not use:
> 	compatible = "allwinner,sun7i-a20-mmc",
> 		     "allwinner,sun5i-a13-mmc";
>
> So newer kernels would pick up the new name and behaviour, while older
> kernels would revert to the old name and use the existing driver.

Good idea, I'll send a v3 with this change.

Regards,

Hans



>
> Cheers,
> Andre.
>
>>  			reg = <0x01c0f000 0x1000>;
>>  			clocks = <&ahb1_gates 8>,
>>  				 <&mmc0_clk 0>,
>> @@ -488,7 +488,7 @@
>>  		};
>>
>>  		mmc1: mmc@01c10000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c10000 0x1000>;
>>  			clocks = <&ahb1_gates 9>,
>>  				 <&mmc1_clk 0>,
>> @@ -507,7 +507,7 @@
>>  		};
>>
>>  		mmc2: mmc@01c11000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c11000 0x1000>;
>>  			clocks = <&ahb1_gates 10>,
>>  				 <&mmc2_clk 0>,
>> @@ -526,7 +526,7 @@
>>  		};
>>
>>  		mmc3: mmc@01c12000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c12000 0x1000>;
>>  			clocks = <&ahb1_gates 11>,
>>  				 <&mmc3_clk 0>,
>> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
>> index bd0c476..94cf5a1 100644
>> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
>> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
>> @@ -905,7 +905,7 @@
>>  		};
>>
>>  		mmc0: mmc@01c0f000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c0f000 0x1000>;
>>  			clocks = <&ahb_gates 8>,
>>  				 <&mmc0_clk 0>,
>> @@ -922,7 +922,7 @@
>>  		};
>>
>>  		mmc1: mmc@01c10000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c10000 0x1000>;
>>  			clocks = <&ahb_gates 9>,
>>  				 <&mmc1_clk 0>,
>> @@ -939,7 +939,7 @@
>>  		};
>>
>>  		mmc2: mmc@01c11000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c11000 0x1000>;
>>  			clocks = <&ahb_gates 10>,
>>  				 <&mmc2_clk 0>,
>> @@ -956,7 +956,7 @@
>>  		};
>>
>>  		mmc3: mmc@01c12000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c12000 0x1000>;
>>  			clocks = <&ahb_gates 11>,
>>  				 <&mmc3_clk 0>,
>> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> index 7e05e09..e3b196e 100644
>> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> @@ -266,7 +266,7 @@
>>  		};
>>
>>  		mmc0: mmc@01c0f000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c0f000 0x1000>;
>>  			clocks = <&ahb1_gates 8>,
>>  				 <&mmc0_clk 0>,
>> @@ -285,7 +285,7 @@
>>  		};
>>
>>  		mmc1: mmc@01c10000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c10000 0x1000>;
>>  			clocks = <&ahb1_gates 9>,
>>  				 <&mmc1_clk 0>,
>> @@ -304,7 +304,7 @@
>>  		};
>>
>>  		mmc2: mmc@01c11000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c11000 0x1000>;
>>  			clocks = <&ahb1_gates 10>,
>>  				 <&mmc2_clk 0>,
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>> index 93c88f3..b5cc2dc 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -154,7 +154,7 @@
>>  		};
>>
>>  		mmc0: mmc@01c0f000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c0f000 0x1000>;
>>  			clocks = <&ccu CLK_BUS_MMC0>,
>>  				 <&ccu CLK_MMC0>,
>> @@ -173,7 +173,7 @@
>>  		};
>>
>>  		mmc1: mmc@01c10000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c10000 0x1000>;
>>  			clocks = <&ccu CLK_BUS_MMC1>,
>>  				 <&ccu CLK_MMC1>,
>> @@ -192,7 +192,7 @@
>>  		};
>>
>>  		mmc2: mmc@01c11000 {
>> -			compatible = "allwinner,sun5i-a13-mmc";
>> +			compatible = "allwinner,sun7i-a20-mmc";
>>  			reg = <0x01c11000 0x1000>;
>>  			clocks = <&ccu CLK_BUS_MMC2>,
>>  				 <&ccu CLK_MMC2>,
>>

Re: [PATCH v2 5/5] ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newer

[Maxime Ripard]

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On Mon, Aug 01, 2016 at 02:11:09PM +0100, Andre Przywara wrote:
> Hi Hans,
> 
> On 30/07/16 15:25, Hans de Goede wrote:
> > Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
> > and newer.
> > 
> > Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> > ---
> > Changes in v2:
> > -New patch in v2 of this patch-set
> > ---
> >  arch/arm/boot/dts/sun6i-a31.dtsi     | 8 ++++----
> >  arch/arm/boot/dts/sun7i-a20.dtsi     | 8 ++++----
> >  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 +++---
> >  arch/arm/boot/dts/sun8i-h3.dtsi      | 6 +++---
> >  4 files changed, 14 insertions(+), 14 deletions(-)
> > 
> > diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> > index 1867af2..0d24f10 100644
> > --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> > +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> > @@ -469,7 +469,7 @@
> >  		};
> >  
> >  		mmc0: mmc@01c0f000 {
> > -			compatible = "allwinner,sun5i-a13-mmc";
> > +			compatible = "allwinner,sun7i-a20-mmc";
> 
> But that breaks systems with newer DTs on older kernels, which do not
> know about sun7i-a20-mmc.

That's not backward compatibility. That's the forward one, and that
has never been something we supported.

See https://www.kernel.org/doc/Documentation/devicetree/bindings/ABI.txt

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH v2 5/5] ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newer

[Andre Przywara]

Hi,

On 22/08/16 08:54, Maxime Ripard wrote:
> On Mon, Aug 01, 2016 at 02:11:09PM +0100, Andre Przywara wrote:
>> Hi Hans,
>>
>> On 30/07/16 15:25, Hans de Goede wrote:
>>> Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
>>> and newer.
>>>
>>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>> ---
>>> Changes in v2:
>>> -New patch in v2 of this patch-set
>>> ---
>>>  arch/arm/boot/dts/sun6i-a31.dtsi     | 8 ++++----
>>>  arch/arm/boot/dts/sun7i-a20.dtsi     | 8 ++++----
>>>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 +++---
>>>  arch/arm/boot/dts/sun8i-h3.dtsi      | 6 +++---
>>>  4 files changed, 14 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
>>> index 1867af2..0d24f10 100644
>>> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
>>> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
>>> @@ -469,7 +469,7 @@
>>>  		};
>>>  
>>>  		mmc0: mmc@01c0f000 {
>>> -			compatible = "allwinner,sun5i-a13-mmc";
>>> +			compatible = "allwinner,sun7i-a20-mmc";
>>
>> But that breaks systems with newer DTs on older kernels, which do not
>> know about sun7i-a20-mmc.
> 
> That's not backward compatibility. That's the forward one, and that
> has never been something we supported.

I know, but it's unfortunate anyway and easy to fix with the above
mentioned fallback scheme.
So isn't that something that we can support anyway, despite it being not
strictly necessary? For instance I tend to load different kernels now
and then (different distro kernels, older versions for regression
checks, ...) and really like the fact that I can go with _one_ known
best DT.
I understand that that's not always possible, but on the other hand I
wouldn't give up so easily, especially if there is a nice way to achieve
compatibility without hurting anyone.

Cheers,
Andre.

> See https://www.kernel.org/doc/Documentation/devicetree/bindings/ABI.txt
> 
> Maxime
> 
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Re: [PATCH v2 0/5] mmc: sunxi: sun4i / sun5i do not have sample clocks

[Ulf Hansson]

On 30 July 2016 at 16:25, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi Ulf, Maxime and Chen-Yu,
>
> Here is v2 of my patch set to deal with sun4i / sun5i not having
> mmc sample clocks, this time introducing a new sun7i-a20-mmc
> compatible for the models which do have sample clks, as discussed
> in the review of v1 of this set.
>
> Ulf, can you please add patches 1-4 to your tree for 4.9, and
> Maxime can you please pick up patch 5 ?
>
> Thanks & Regards,
>
> Hans

Thanks, applied for next!

Note that I picked the v2 of patch 5/5 and not the v3.

Kind regards
Uffe