From: Brendan Jackman <brendan.jackman@arm.com>
To: Lina Iyer <lina.iyer@linaro.org>
Cc: Sudeep Holla <sudeep.holla@arm.com>,
linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
ulf.hansson@linaro.org, khilman@kernel.org, rjw@rjwysocki.net,
andy.gross@linaro.org, sboyd@codeaurora.org,
linux-arm-msm@vger.kernel.org,
Axel Haslam <ahaslam+renesas@baylibre.com>,
devicetree@vger.kernel.org,
Marc Titinger <mtitinger+renesas@baylibre.com>,
Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
Juri Lelli <Juri.Lelli@arm.com>
Subject: Re: [PATCH v3 02/15] dt/bindings: Update binding for PM domain idle states
Date: Fri, 12 Aug 2016 13:35:17 +0100 [thread overview]
Message-ID: <20160812123516.GA24194@brendan-thinkstation> (raw)
In-Reply-To: <20160811211023.GC1401@linaro.org>
Hi Lina,
Apologies, I sent this reply before and automatically included an "IMPORTANT
NOTICE" footer, please disregard that email, here's the same thing without the
footer.
On Thu, Aug 11, 2016 at 03:10:23PM -0600, Lina Iyer wrote:
> On Wed, Aug 10 2016 at 12:09 -0600, Sudeep Holla wrote:
> >
> >
> >On 10/08/16 17:40, Lina Iyer wrote:
> >>Hi Sudeep,
> >>
> >>On Wed, Aug 10 2016 at 09:15 -0600, Sudeep Holla wrote:
> >>>Hi Lina,
> >>>
> >>>I have few concerns mainly due to the lack of description and not the
> >>>binding per say.
> >
> >[...]
> >
> >>It is pretty clear that CPUs cannot not define the domain idle states.
> >>Domains define their own idle states. Just as you mention above. CPU is
> >>just a single component in its domain. There may be other devices like
> >>PMUs, Coresights etc that also may have a say in the idle state the
> >>domain may be put in, when the devices are idle. As such, adding domain
> >>idle states to the CPU's idle state property is not appropriate.
> >>
> >
> >No I am not saying we need to add domain idle states to the CPU's idle
> >state property. I am saying we need to remove cpu-idle-states or ignore
> >it when PD is present. And get all the idle state information for PD.
> >
> >I am objecting the split we are creating across CPU and higher level
> >power domains. And this binding document is incomplete as it skips all
> >those details. We just need PD handle in CPU and no idle state
> >information there. Create PD hierarchy and have all idle state
> >information at one place.
> >
> Let me think about this a bit and see what I can come up with.
>
> >>Our kernel has runtime PM for devices and then there is CPUidle, both
> >>are diverging without one knowing about the other. We have to start
> >>unifying them inorder to have better holistic power management in the
> >>SoC. To that regard, we have to start imagining CPUs as just another
> >>device, albeit a special device. But for our purposes in determining
> >>domain idle state, it will just be a device attached to the domain.
> >>
> >
> >Absolutely agree on that. No arguments. I am asking to go a step ahead
> >to include even cpu/core level power domains not just cluster/higher
> >level domains.
> >
> >>>We need to have all the idle state information at one place and in this
> >>>case PD seems more appropriate instead of splitting them across.
> >>>
> >>That approach isn't correct. Where will we put the idle states of other
> >>devices that are also part of the domain? We are thinking about a model,
> >>where every device defines its own idle states and we define
> >>relationships between those idle states and their parents' idle states.
> >
> >Yes I understand. You confused me here. Won't that be one-to-one
> >relationship ? If not, how is that dealt in the current bindings ?
> >
> >>Ofcourse, devices don't have idle states today, but that is something we
> >>have been pondering over.
> >>
> >
> >Yes we these binding should be easily extensible, I don't see any issue.
> >
> >>>We can also keep the code clean and not break compatibility. Whenever
> >>>both PD and CPU contains idle-states, PD must take precedence.
> >>>
> >>Why?
> >>The CPU and PD states are orthogonal. While the PD state is dependent on
> >>the CPU state, the latter is not true. Devices determine their own
> >>states. Based on the individual device states, we then determine the
> >>state of the parent and bubble up on the hierarchy.
> >>
> >
> >I may be missing something. Now with your example in the binding, if
> >another device shares the cluster PD, can it have different idle states?
> >If so how does it map ?
> >
> >
> >In general whatever binding we come up must not just address OS
> >coordinated mode. Also I was thinking to have better coverage in
> >the description by having a bit more complex system like:
> >
> >cluster0
> > CLUSTER_RET(Retention)
> > CLUSTER_PG(Power Gate)
> > core0
> > CORE_RET
> > CORE_PG
> > core1
> > CORE_RET
> > CORE_PG
> >
> >cluster1
> > CLUSTER_RET
> > CLUSTER_PG
> > core0
> > CORE_RET
> > CORE_PG
> > core1
> > CORE_RET
> > CORE_PG
> >
> >Platform Co-ordinate supports the following states and we should
> >be able to determine that from the binding:
> >
> >CORE_RET
> >CORE_PG
> >CORE_RET + CLUSTER_RET
>
> The problem that we have to sove here is knowing that CORE_RET +
> CLUSTER_PG (hypothetically) an invalid combination. Kevin and
> I debated it in the earlier RFC and we dont have a good way to solve
> this generically for all devices.
>
This is interesting. I had been working on the assumption that a parent
power domain cannot enter any idle state until its children were all in
their deepest idle state. I now realise that it's easy to imagine
platforms where this isn't the case.
However, I don't understand how your current bindings solve this issue
and why using domain-power-states for all states (i.e. ignoring
cpu-idle-states and putting CPU idle states in the domain-idle-states of
a per-CPU power domain - I believe this is what Sudeep is suggesting)
makes it any more difficult.
Could you link to this previous discussion you mentioned? I'm having
trouble finding it (R.I.P Gmane).
> >CORE_PG + CLUSTER_RET
> >CORE_PG + CLUSTER_PG
> >
Cheers,
Brendan
next prev parent reply other threads:[~2016-08-12 12:35 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1470351902-43103-1-git-send-email-lina.iyer@linaro.org>
2016-08-04 23:04 ` [PATCH v3 02/15] dt/bindings: Update binding for PM domain idle states Lina Iyer
2016-08-09 23:55 ` Rob Herring
2016-08-10 15:14 ` Sudeep Holla
2016-08-10 16:40 ` Lina Iyer
[not found] ` <20160810164034.GA1401-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-08-10 18:09 ` Sudeep Holla
2016-08-10 18:13 ` Sudeep Holla
[not found] ` <5e59874c-bbb7-270a-199c-da1ff5932554-5wv7dgnIgG8@public.gmane.org>
2016-08-11 21:10 ` Lina Iyer
[not found] ` <20160811211023.GC1401-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-08-12 9:47 ` Brendan Jackman
2016-08-12 10:08 ` Sudeep Holla
2016-08-15 16:08 ` Lina Iyer
2016-08-15 16:14 ` Sudeep Holla
2016-08-15 22:40 ` Lina Iyer
[not found] ` <20160815224014.GF1401-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-08-16 8:34 ` Brendan Jackman
2016-08-16 8:41 ` Brendan Jackman
2016-08-16 9:19 ` Sudeep Holla
2016-08-12 12:35 ` Brendan Jackman [this message]
2016-08-15 16:06 ` Lina Iyer
2016-08-19 18:10 ` Kevin Hilman
2016-08-24 14:07 ` Sudeep Holla
[not found] ` <1470351902-43103-3-git-send-email-lina.iyer-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-08-24 13:48 ` [RFC 0/6] Illustration of using domain-idle-states for CPU " Brendan Jackman
2016-08-24 13:48 ` [RFC 1/6] cpuidle: Rename cpuidle_get_{cpu->dev}_driver Brendan Jackman
2016-08-24 13:48 ` [RFC 2/6] cpuidle: Add public funcion to get driver from CPU index Brendan Jackman
2016-08-24 13:48 ` [RFC 4/6] cpuidle: dt: Add support for reading states from power domains Brendan Jackman
2016-08-24 13:48 ` [RFC 5/6] arm64: dts: Add Juno r0 CPU power domain tree Brendan Jackman
[not found] ` <20160824134822.3591-1-brendan.jackman-5wv7dgnIgG8@public.gmane.org>
2016-08-24 13:48 ` [RFC 3/6] cpuidle: Add device_node pointer in cpuidle_state Brendan Jackman
2016-08-24 13:48 ` [RFC 6/6] arm64: dts: Add domain-idle-states for Juno r0 power domains Brendan Jackman
2016-08-04 23:05 ` [PATCH v3 14/15] ARM64: dts: Add PSCI cpuidle support for MSM8916 Lina Iyer
[not found] ` <1470351902-43103-1-git-send-email-lina.iyer-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-08-04 23:05 ` [PATCH v3 15/15] ARM64: dts: Define CPU power domain " Lina Iyer
2016-08-10 15:27 ` Sudeep Holla
2016-08-10 17:35 ` Lina Iyer
2016-08-11 9:30 ` Sudeep Holla
[not found] ` <1470351902-43103-14-git-send-email-lina.iyer@linaro.org>
2016-08-05 14:44 ` [PATCH v3 13/15] dt/bindings: Add PSCI OS-Initiated PM Domains bindings Lina Iyer
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