[PATCH 0/3] ARM: K2G: Add support for TI-SCI Clocks

[PATCH 0/3] ARM: K2G: Add support for TI-SCI Clocks

[Nishanth Menon]

Texas Instruments' Keystone generation System on Chips (SoC)
starting with 66AK2G02[1], now include a dedicated SoC System Control
entity called PMMC(Power Management Micro Controller) in line with
ARM architecture recommendations. The function of this module is
to integrate all system operations in a centralized location.
Communication with the SoC System Control entity from various
processing units like ARM/DSP occurs over Message Manager hardware
block.

This series adds the base support for clock control using generic
power domain framework over the TI System Control Interface (TI-SCI)
protocol[2][3][4].

Overall architecture is very similar to SCPI[5] as follows:
+--------------+  +-------------+   +------------+
| TI SCI GENPD |  |TISCI Clk(*) |   |TISCI reset |
+------+-------+  +----+--------+   +----+-------+
       |               |                 |
       |          +----v--------------+  |
       +----------> TISCI Protocol    <--+
                  +----+--------------+
                       |
                   +---v-----------+
                   | MAILBOX  FWK  |
                   +---+-----------+
                       |
                   +---v-----------+
                   |  TI MSGMGR    |-> TISCI hardware block
                   +---------------+

(*) This series.

Baseline: v4.8-rc1 + [3] + [4] (the dependency is due to MAINTAINERS update, API, data)
Bootlog: http://pastebin.ubuntu.com/23071879/ (with the addition of couple of mach patches + dts)
Integrated series is available:
https://github.com/nmenon/linux-2.6-playground/commits/upstream/v4.9/tisci-clk-v1

This is the last of the three major blocks to provide functionality for K2G SoC.
TISCI reset series is a follow on series to enable DSP remoteproc and few other
peripherals.

NOTE: Tero is currently on vacation(till Aug 28) and the series
is being send on his behalf to provide a complete baseline series
for review. Obviously, all dependencies must be merged prior to
this series being merged, but any additional feedback will be much
appreciated.

Tero Kristo (3):
  Documentation: dt: Add TI SCI clock driver
  dt-binding: clock: Add k2g clock definitions
  clk: keystone: Add sci-clk driver support

[1] http://www.ti.com/product/66ak2g02
[2] http://processors.wiki.ti.com/index.php/TISCI
[3] https://lkml.org/lkml/2016/8/19/768
[4] https://lkml.org/lkml/2016/8/19/790
[5] Documentation/devicetree/bindings/arm/arm,scpi.txt

 .../devicetree/bindings/clock/ti,sci-clk.txt       |  51 ++
 MAINTAINERS                                        |   3 +
 drivers/clk/Kconfig                                |  13 +
 drivers/clk/keystone/Makefile                      |   1 +
 drivers/clk/keystone/sci-clk.c                     | 539 +++++++++++++++++++++
 include/dt-bindings/clock/k2g.h                    | 234 +++++++++
 6 files changed, 841 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ti,sci-clk.txt
 create mode 100644 drivers/clk/keystone/sci-clk.c
 create mode 100644 include/dt-bindings/clock/k2g.h

-- 
2.9.1.200.gb1ec08f

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[PATCH 1/3] Documentation: dt: Add TI SCI clock driver

[Nishanth Menon]

From: Tero Kristo <t-kristo@ti.com>

Add a clock implementation, TI SCI clock, that will hook to the common
clock framework, and allow each clock to be controlled via TI SCI
protocol.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 .../devicetree/bindings/clock/ti,sci-clk.txt       | 51 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ti,sci-clk.txt

diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt b/Documentation/devicetree/bindings/clock/ti,sci-clk.txt
new file mode 100644
index 000000000000..231cb80a058e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti,sci-clk.txt
@@ -0,0 +1,51 @@
+Texas Instruments TI-SCI Clocks
+===============================
+
+All clocks on Texas Instruments' SoCs that contain a System Controller,
+are only controlled by this entity. Communication between a host processor
+running an OS and the System Controller happens through a protocol known
+as TI-SCI[1]. This clock implementation plugs into the common clock
+framework and makes use of the TI-SCI protocol on clock API requests.
+
+[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
+
+Required properties:
+-------------------
+- compatible: Must be "ti,sci-clk"
+- #clock-cells: Shall be 2.
+  In clock consumers, this cell represents the device ID and clock ID
+  exposed by the PM firmware. The assignments can be found in the header
+  files <dt-bindings/genpd/<soc>.h> (which covers the device IDs) and
+  <dt-bindings/clock/<soc>.h> (which covers the clock IDs), where <soc>
+  is the SoC involved, for example 'k2g'.
+- ti,sci: Phandle to the TI SCI device to use for managing the clocks
+
+Optional properties:
+-------------------
+- ti,ssc-clocks: Array of phandle clocks that shall enable spread spectrum
+		 clocking while enabled
+- ti,allow-freq-change-clocks: Array of phandle clocks that shall allow
+			       dynamic clock frequency changes by firmware
+- ti,input-term-clocks: Array of phandle clocks that shall enable input
+			termination
+
+Examples:
+--------
+
+k2g_clks: k2g_clks {
+	compatible = "ti,sci-clk";
+	ti,sci = <&pmmc>;
+	#clock-cells = <2>;
+};
+
+dummy_node@1234 {
+	clocks = <&k2g_clks K2G_DEV_DUMMY K2G_DEV_DUMMY_FCK>;
+};
+
+dummy_node2@2345 {
+	clocks = <&k2g_clks K2G_DEV_DUMMY2 K2G_DEV_DUMMY_X1_CLK>;
+};
+
+&k2g_clks {
+	ti,ssc-clocks = <&k2g_clks K2G_DEV_DUMMY K2G_DEV_DUMMY_FCK>;
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 448f6801bd78..1837b98d96a9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11576,6 +11576,7 @@ F:	include/linux/soc/ti/ti_sci_protocol.h
 F:	Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
 F:	include/dt-bindings/genpd/k2g.h
 F:	drivers/soc/ti/ti_sci_pm_domains.c
+F:	Documentation/devicetree/bindings/clock/ti,sci-clk.txt
 
 THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
 M:	Hans Verkuil <hverkuil@xs4all.nl>
-- 
2.9.1.200.gb1ec08f

[PATCH 2/3] dt-binding: clock: Add k2g clock definitions

[Nishanth Menon]

From: Tero Kristo <t-kristo@ti.com>

Add identifiers for the K2G clocks managed by the PMMC.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 MAINTAINERS                     |   1 +
 include/dt-bindings/clock/k2g.h | 234 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 235 insertions(+)
 create mode 100644 include/dt-bindings/clock/k2g.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 1837b98d96a9..f24aa97f845c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11577,6 +11577,7 @@ F:	Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
 F:	include/dt-bindings/genpd/k2g.h
 F:	drivers/soc/ti/ti_sci_pm_domains.c
 F:	Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+F:	include/dt-bindings/clock/k2g.h
 
 THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
 M:	Hans Verkuil <hverkuil@xs4all.nl>
diff --git a/include/dt-bindings/clock/k2g.h b/include/dt-bindings/clock/k2g.h
new file mode 100644
index 000000000000..cddffc360a13
--- /dev/null
+++ b/include/dt-bindings/clock/k2g.h
@@ -0,0 +1,234 @@
+/*
+ * TI K2G SoC clock definitions
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLOCK_K2G_H__
+#define __DT_BINDINGS_CLOCK_K2G_H__
+
+/*
+ * The clock IDs listed in this file are describing the clocks at IP's
+ * boundaries. The firmware is not exposing any of the generic clocks
+ * from the system, those are handled internally by the firmware.
+ */
+#define K2G_DEV_PMMC_MPM_VBUS_CLK		0
+#define K2G_DEV_PMMC_MPM_FUNC_32K_CLK		1
+#define K2G_DEV_PMMC_MPM_FUNC_OSC_CLK		2
+#define K2G_DEV_PMMC_MPM_DAP_CLK		3
+
+#define K2G_DEV_MLB_MLB_SYS_CLK			0
+#define K2G_DEV_MLB_MLB_SHB_OCP_CLK		1
+#define K2G_DEV_MLB_MLB_SPB_OCP_CLK		2
+#define K2G_DEV_MLB_MLB_IO_CLK			3
+#define K2G_DEV_MLB_MLBP_IO_CLK			4
+
+#define K2G_DEV_DSS_PI_DSS_OCP_CLK		0
+#define K2G_DEV_DSS_PI_DSS_VP_CLK		1
+
+#define K2G_DEV_MCBSP_VBUS_CLK			0
+#define K2G_DEV_MCBSP_CLKS			1
+#define K2G_DEV_MCBSP_CLKS_PARENT_AUDIO_OSC	2
+#define K2G_DEV_MCBSP_CLKS_PARENT_MLB_IO_CLK	3
+#define K2G_DEV_MCBSP_CLKS_PARENT_MLBP_IO_CLK	4
+#define K2G_DEV_MCBSP_CLKS_PARENT_SYS_OSCCLK	5
+#define K2G_DEV_MCBSP_CLKS_PARENT_XREFCLK	6
+#define K2G_DEV_MCBSP_CLKS_PARENT_UART_PLL	7
+
+#define K2G_DEV_MCASP_VBUS_CLK			0
+#define K2G_DEV_MCASP_AUX_CLK			1
+#define K2G_DEV_MCASP_AUX_CLK_PARENT_AUDIO_OSC		2
+#define K2G_DEV_MCASP_AUX_CLK_PARENT_MLB_IO_CLK		3
+#define K2G_DEV_MCASP_AUX_CLK_PARENT_MLBP_IO_CLK	4
+#define K2G_DEV_MCASP_AUX_CLK_PARENT_SYS_OSCCLK		5
+#define K2G_DEV_MCASP_AUX_CLK_PARENT_XREFCLK		6
+#define K2G_DEV_MCASP_AUX_CLK_PARENT_UART_PLL		7
+
+#define K2G_DEV_DCAN_VBUS_CLK			0
+#define K2G_DEV_DCAN_CAN_CLK			1
+
+#define K2G_DEV_EMIF_V_CLK			0
+#define K2G_DEV_EMIF_M_CLK			1
+#define K2G_DEV_EMIF_DFT_LOCAL_CLK		2
+#define K2G_DEV_EMIF_PUB_CTL_CLK		3
+#define K2G_DEV_EMIF_PHY_CTL_CLK		4
+#define K2G_DEV_EMIF_VBUSP_CLK			5
+
+#define K2G_DEV_MMCHS_VBUS_CLK			0
+#define K2G_DEV_MMCHS_CLK_ADPI			1
+#define K2G_DEV_MMCHS_CLK32K			2
+
+#define K2G_DEV_GPMC_GPMC_FCLK			0
+
+#define K2G_DEV_ELM_CLK				0
+
+#define K2G_DEV_SPI_VBUSP_CLK			0
+
+#define K2G_DEV_ICSS_VCLK_CLK			0
+#define K2G_DEV_ICSS_CORE_CLK			1
+#define K2G_DEV_ICSS_CORE_CLK_PARENT_ICSS_PLL	2
+#define K2G_DEV_ICSS_CORE_CLK_PARENT_NSS_PLL	3
+#define K2G_DEV_ICSS_UCLK_CLK			4
+#define K2G_DEV_ICSS_IEPCLK_CLK			5
+
+#define K2G_DEV_USB_BUS_CLK			0
+#define K2G_DEV_USB_PHYMMR_CLK			1
+#define K2G_DEV_USB_SUSP_CLK			2
+#define K2G_DEV_USB_REF_CLK			3
+#define K2G_DEV_USB_DFT_ULPI_CLK		4
+#define K2G_DEV_USB_DFT_UTMI_CLK		5
+#define K2G_DEV_USB_CLKCORE			6
+
+#define K2G_DEV_NSS_VCLK			0
+#define K2G_DEV_NSS_SA_UL_CLK			1
+#define K2G_DEV_NSS_SA_UL_X1_CLK		2
+#define K2G_DEV_NSS_ESW_CLK			3
+/*
+ * Mux register is internal to the CPTS, so we must allow NSS to control it.
+ * CPTS_REFCLK_P/N is a direct input to this mux, so ignore it is ignored
+ * in the SoC clock tree.
+ */
+#define K2G_DEV_NSS_CPTS_CHIP_CLK1_2		4
+#define K2G_DEV_NSS_CPTS_CHIP_CLK1_3		5
+#define K2G_DEV_NSS_CPTS_TIMI0			6
+#define K2G_DEV_NSS_CPTS_TIMI1			7
+#define K2G_DEV_NSS_CPTS_NSS_PLL		8
+#define K2G_DEV_NSS_GMII_RFTCLK			9
+#define K2G_DEV_NSS_RGMII_MHZ_5_CLK		10
+#define K2G_DEV_NSS_RGMII_MHZ_50_CLK		11
+#define K2G_DEV_NSS_RGMII_MHZ_250_CLK		12
+#define K2G_DEV_NSS_RMII_MHZ_50_CLK		13
+
+#define K2G_DEV_PCIE_VBUS_CLK			0
+
+#define K2G_DEV_OTP_VBUS_CLK			0
+
+#define K2G_DEV_GPIO_VBUS_CLK			0
+
+#define K2G_DEV_TIMER64_VBUS_CLK		0
+#define K2G_DEV_TIMER64_TINL			1
+#define K2G_DEV_TIMER64_TINL_PARENT_TIMI0	2
+#define K2G_DEV_TIMER64_TINL_PARENT_TIMI1	3
+#define K2G_DEV_TIMER64_TINH			4
+#define K2G_DEV_TIMER64_TINH_PARENT_TIMI0	5
+#define K2G_DEV_TIMER64_TINH_PARENT_TIMI1	6
+#define K2G_DEV_TIMER64_TOUTL			7
+#define K2G_DEV_TIMER64_TOUTH			8
+
+#define K2G_DEV_SEC_MGR_SEC_CLK_PI		0
+
+#define K2G_DEV_MSGMGR_VBUS_CLK			0
+
+#define K2G_DEV_BOOTCFG_VBUS_CLK		0
+
+#define K2G_DEV_ARM_BOOTROM_VBUS_CLK		0
+
+#define K2G_DEV_DSP_BOOTROM_VBUS_CLK		0
+
+#define K2G_DEV_DEBUGSS_VBUSP_CTTBRCLK_CLK	0
+#define K2G_DEV_DEBUGSS_VBUSP_STMD0_CLK		1
+#define K2G_DEV_DEBUGSS_VBUSP_SLAVE_CLK		2
+#define K2G_DEV_DEBUGSS_VBUSP_MASTER_CLK	3
+#define K2G_DEV_DEBUGSS_TCK			4
+#define K2G_DEV_DEBUGSS_CS_TRCEXPT_CLK		5
+#define K2G_DEV_DEBUGSS_DSP_TRACECLK		6
+#define K2G_DEV_DEBUGSS_STMXPT_CLK		7
+
+#define K2G_DEV_UART_CBA_CLK_PI			0
+
+#define K2G_DEV_EHRPWM_VBUS_CLK			0
+
+#define K2G_DEV_EQEP_VBUS_CLK			0
+
+#define K2G_DEV_ECAP_VBUS_CLK			0
+
+#define K2G_DEV_I2C_VBUS_CLK			0
+
+#define K2G_DEV_CP_TRACER_CP_TRACER_CLK		0
+
+#define K2G_DEV_EDMA_TPTC_CLK			0
+#define K2G_DEV_EDMA_TPCC_CLK			1
+
+#define K2G_DEV_SEMAPHORE_VBUS_CLK		0
+
+#define K2G_DEV_INTC_VBUS_CLK			0
+
+#define K2G_DEV_GIC_VBUS_CLK			0
+
+#define K2G_DEV_QSPI_QSPI_CLK			0
+#define K2G_DEV_QSPI_DATA_BUS_CLK		1
+#define K2G_DEV_QSPI_CFG_BUS_CLK		2
+#define K2G_DEV_QSPI_QSPI_CLK_O			3
+#define K2G_DEV_QSPI_QSPI_CLK_I			4
+
+#define K2G_DEV_ARM_64B_COUNTER_CLK_INPUT	0
+#define K2G_DEV_ARM_64B_COUNTER_VBUSP_CLK	1
+
+#define K2G_DEV_TETRIS_CORE_CLK			0
+#define K2G_DEV_TETRIS_SUBSYS_CLK		1
+
+#define K2G_DEV_CGEM_CORE_CLK			0
+#define K2G_DEV_CGEM_TRACE_CLK			1
+
+#define K2G_DEV_MSMC_VBUS_CLK			0
+
+#define K2G_DEV_DFT_SS_VBUS_CLK			0
+#define K2G_DEV_DFT_SS_TCK			1
+
+#define K2G_DEV_CBASS_VBUS_CLK			0
+
+#define K2G_DEV_SMARTREFLEX_SCLK_CLK		0
+#define K2G_DEV_SMARTREFLEX_REFCLK1_CLK		1
+#define K2G_DEV_SMARTREFLEX_TEMPMCLK_CLK	2
+
+#define K2G_DEV_EFUSE_VBUS_CLK			0
+
+/* Outputs from board (inputs to SoC) */
+#define K2G_DEV_BOARD_SYS_OSCIN			0
+#define K2G_DEV_BOARD_SYS_CLK			1
+#define K2G_DEV_BOARD_AUDIO_OSCIN		2
+#define K2G_DEV_BOARD_DDR			3
+#define K2G_DEV_BOARD_MLBCLK			4
+#define K2G_DEV_BOARD_MLBPCLK			5
+#define K2G_DEV_BOARD_XREFCLK			6
+#define K2G_DEV_BOARD_TIMI0			7
+#define K2G_DEV_BOARD_TIMI1			8
+
+/* Inputs to board (outputs from SoC) */
+#define K2G_DEV_BOARD_SYSCLKOUT			10
+#define K2G_DEV_BOARD_OBSCLK			11
+#define K2G_DEV_BOARD_OBSCLK_PARENT_MAIN_PLL	12
+#define K2G_DEV_BOARD_OBSCLK_PARENT_DSS_PLL	13
+#define K2G_DEV_BOARD_OBSCLK_PARENT_ARM_PLL	14
+#define K2G_DEV_BOARD_OBSCLK_PARENT_UART_PLL	15
+#define K2G_DEV_BOARD_OBSCLK_PARENT_ICSS_PLL	16
+#define K2G_DEV_BOARD_OBSCLK_PARENT_DDR_PLL	17
+#define K2G_DEV_BOARD_OBSCLK_PARENT_PLL_CTRL	18
+#define K2G_DEV_BOARD_OBSCLK_PARENT_NSS_PLL	19
+#define K2G_DEV_BOARD_OBSCLK_PARENT_SYSOSC	20
+#define K2G_DEV_BOARD_MII_CLKOUT		21
+#define K2G_DEV_BOARD_TIMO0			22
+#define K2G_DEV_BOARD_TIMO1			23
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_0L	24
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_0H	25
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_1L	26
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_1H	27
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_2L	28
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_2H	29
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_3L	30
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_3H	31
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_4L	32
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_4H	33
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_5L	34
+#define K2G_DEV_BOARD_TIMO_PARENT_TIMER64_5H	35
+
+#endif
-- 
2.9.1.200.gb1ec08f

[PATCH 3/3] clk: keystone: Add sci-clk driver support

[Nishanth Menon]

From: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>

In K2G, the clock handling is done through firmware executing on a
separate core. Linux kernel needs to communicate to the firmware
through TI system control interface to access any power management
related resources, including clocks.

The keystone sci-clk driver does this, by communicating to the
firmware through the TI SCI driver. The driver adds support for
registering clocks through DT, and basic required clock operations
like prepare/get_rate, etc.

Signed-off-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
Tested-by: Dave Gerlach <d-gerlach-l0cyMroinI0@public.gmane.org>
Signed-off-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
---
 MAINTAINERS                    |   1 +
 drivers/clk/Kconfig            |  13 +
 drivers/clk/keystone/Makefile  |   1 +
 drivers/clk/keystone/sci-clk.c | 539 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 554 insertions(+)
 create mode 100644 drivers/clk/keystone/sci-clk.c

diff --git a/MAINTAINERS b/MAINTAINERS
index f24aa97f845c..af06f022b725 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11578,6 +11578,7 @@ F:	include/dt-bindings/genpd/k2g.h
 F:	drivers/soc/ti/ti_sci_pm_domains.c
 F:	Documentation/devicetree/bindings/clock/ti,sci-clk.txt
 F:	include/dt-bindings/clock/k2g.h
+F:	drivers/clk/keystone/sci-clk.c
 
 THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
 M:	Hans Verkuil <hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index e2d9bd760c84..d1724999be78 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -179,6 +179,19 @@ config COMMON_CLK_NXP
 	---help---
 	  Support for clock providers on NXP platforms.
 
+if COMMON_CLK_KEYSTONE
+
+config TI_SCI_CLK
+	tristate "TI System Control Interface clock drivers"
+	depends on TI_SCI_PROTOCOL || COMPILE_TEST
+	default y
+	help
+	  This adds the clock driver support over TI System Control Interface.
+	  If you wish to use clock resources from the PMMC firmware, say Y.
+	  Otherwise, say N.
+
+endif # COMMON_CLK_KEYSTONE
+
 config COMMON_CLK_PALMAS
 	tristate "Clock driver for TI Palmas devices"
 	depends on MFD_PALMAS
diff --git a/drivers/clk/keystone/Makefile b/drivers/clk/keystone/Makefile
index 0477cf63f132..0e7993d2c09a 100644
--- a/drivers/clk/keystone/Makefile
+++ b/drivers/clk/keystone/Makefile
@@ -1 +1,2 @@
 obj-y			+= pll.o gate.o
+obj-$(CONFIG_TI_SCI_CLK)	+= sci-clk.o
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
new file mode 100644
index 000000000000..6c43e097e6d6
--- /dev/null
+++ b/drivers/clk/keystone/sci-clk.c
@@ -0,0 +1,539 @@
+/*
+ * SCI Clock driver for keystone based devices
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *	Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+
+#define SCI_CLK_SSC_ENABLE		BIT(0)
+#define SCI_CLK_ALLOW_FREQ_CHANGE	BIT(1)
+#define SCI_CLK_INPUT_TERMINATION	BIT(2)
+
+/**
+ * struct sci_clk_provider - TI SCI clock provider representation
+ * @sci:    Handle to the System Control Interface protocol handler
+ * @ops:    Pointer to the SCI ops to be used by the clocks
+ * @dev:    Device pointer for the clock provider
+ * @clocks: List of all registered clocks
+ * @lock:   Mutex for locking access to the @clocks list
+ */
+struct sci_clk_provider {
+	const struct ti_sci_handle *sci;
+	const struct ti_sci_clk_ops *ops;
+	struct device *dev;
+	struct list_head clocks;
+	struct mutex lock; /* Protects access to the @clocks list */
+};
+
+/**
+ * struct sci_clk - TI SCI clock representation
+ * @hw:		 Hardware clock cookie for common clock framework
+ * @dev_id:	 Device index
+ * @clk_id:	 Clock index
+ * @node:	 Clocks list link
+ * @provider:	 Master clock provider
+ * @flags:	 Flags for the clock
+ */
+struct sci_clk {
+	struct clk_hw hw;
+	u16 dev_id;
+	u8 clk_id;
+	struct list_head node;
+	struct sci_clk_provider *provider;
+	u8 flags;
+};
+
+#define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw)
+
+/**
+ * sci_clk_prepare - Prepare (enable) a TI SCI clock
+ * @hw: clock to prepare
+ *
+ * Prepares a clock to be actively used. Returns the SCI protocol status.
+ */
+static int sci_clk_prepare(struct clk_hw *hw)
+{
+	struct sci_clk *clk = to_sci_clk(hw);
+	bool enable_ssc = clk->flags & SCI_CLK_SSC_ENABLE;
+	bool allow_freq_change = clk->flags & SCI_CLK_ALLOW_FREQ_CHANGE;
+	bool input_termination = clk->flags & SCI_CLK_INPUT_TERMINATION;
+
+	return clk->provider->ops->get_clock(clk->provider->sci, clk->dev_id,
+					     clk->clk_id, enable_ssc,
+					     allow_freq_change,
+					     input_termination);
+}
+
+/**
+ * sci_clk_unprepare - Un-prepares (disables) a TI SCI clock
+ * @hw: clock to unprepare
+ *
+ * Un-prepares a clock from active state.
+ */
+static void sci_clk_unprepare(struct clk_hw *hw)
+{
+	struct sci_clk *clk = to_sci_clk(hw);
+	int ret;
+
+	ret = clk->provider->ops->put_clock(clk->provider->sci, clk->dev_id,
+					    clk->clk_id);
+	if (ret)
+		dev_err(clk->provider->dev,
+			"unprepare failed for dev=%d, clk=%d, ret=%d\n",
+			clk->dev_id, clk->clk_id, ret);
+}
+
+/**
+ * sci_clk_is_prepared - Check if a TI SCI clock is prepared or not
+ * @hw: clock to check status for
+ *
+ * Checks if a clock is prepared (enabled) in hardware. Returns non-zero
+ * value if clock is enabled, zero otherwise.
+ */
+static int sci_clk_is_prepared(struct clk_hw *hw)
+{
+	struct sci_clk *clk = to_sci_clk(hw);
+	bool req_state, current_state;
+	int ret;
+
+	ret = clk->provider->ops->is_on(clk->provider->sci, clk->dev_id,
+					clk->clk_id, &req_state,
+					&current_state);
+	if (ret) {
+		dev_err(clk->provider->dev,
+			"prepare failed for dev=%d, clk=%d, ret=%d\n",
+			clk->dev_id, clk->clk_id, ret);
+		return 0;
+	}
+
+	return req_state;
+}
+
+/**
+ * sci_clk_recalc_rate - Get clock rate for a TI SCI clock
+ * @hw: clock to get rate for
+ * @parent_rate: parent rate provided by common clock framework, not used
+ *
+ * Gets the current clock rate of a TI SCI clock. Returns the current
+ * clock rate, or zero in failure.
+ */
+static unsigned long sci_clk_recalc_rate(struct clk_hw *hw,
+					 unsigned long parent_rate)
+{
+	struct sci_clk *clk = to_sci_clk(hw);
+	u64 freq;
+	int ret;
+
+	ret = clk->provider->ops->get_freq(clk->provider->sci, clk->dev_id,
+					   clk->clk_id, &freq);
+	if (ret) {
+		dev_err(clk->provider->dev,
+			"recalc-rate failed for dev=%d, clk=%d, ret=%d\n",
+			clk->dev_id, clk->clk_id, ret);
+		return 0;
+	}
+
+	return (u32)freq;
+}
+
+/**
+ * sci_clk_determine_rate - Determines a clock rate a clock can be set to
+ * @hw: clock to change rate for
+ * @req: requested rate configuration for the clock
+ *
+ * Determines a suitable clock rate and parent for a TI SCI clock.
+ * The parent handling is un-used, as generally the parent clock rates
+ * are not known by the kernel; instead these are internally handled
+ * by the firmware. Returns the new clock rate that can be set for the
+ * clock, or 0 in failure.
+ */
+static int sci_clk_determine_rate(struct clk_hw *hw,
+				  struct clk_rate_request *req)
+{
+	struct sci_clk *clk = to_sci_clk(hw);
+	u64 new_rate;
+	int ret;
+
+	ret = clk->provider->ops->get_best_match_freq(clk->provider->sci,
+						      clk->dev_id,
+						      clk->clk_id,
+						      req->min_rate,
+						      req->rate,
+						      req->max_rate,
+						      &new_rate);
+	if (ret) {
+		dev_err(clk->provider->dev,
+			"determine-rate failed for dev=%d, clk=%d, ret=%d\n",
+			clk->dev_id, clk->clk_id, ret);
+		return 0;
+	}
+
+	return (int)new_rate;
+}
+
+/**
+ * sci_clk_set_rate - Set rate for a TI SCI clock
+ * @hw: clock to change rate for
+ * @rate: target rate for the clock
+ * @parent_rate: rate of the clock parent, not used for TI SCI clocks
+ *
+ * Sets a clock frequency for a TI SCI clock. Returns the TI SCI
+ * protocol status.
+ */
+static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+			    unsigned long parent_rate)
+{
+	struct sci_clk *clk = to_sci_clk(hw);
+	u64 freq = rate;
+
+	return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
+					    clk->clk_id, freq, freq, freq);
+}
+
+/**
+ * sci_clk_get_parent - Get the current parent of a TI SCI clock
+ * @hw: clock to get parent for
+ *
+ * Returns the index of the currently selected parent for a TI SCI clock.
+ */
+static u8 sci_clk_get_parent(struct clk_hw *hw)
+{
+	struct sci_clk *clk = to_sci_clk(hw);
+	u8 parent_id;
+	int ret;
+
+	ret = clk->provider->ops->get_parent(clk->provider->sci, clk->dev_id,
+					     clk->clk_id, &parent_id);
+	if (ret) {
+		dev_err(clk->provider->dev,
+			"get-parent failed for dev=%d, clk=%d, ret=%d\n",
+			clk->dev_id, clk->clk_id, ret);
+		return 0;
+	}
+
+	parent_id = parent_id - clk->clk_id - 1;
+
+	return parent_id;
+}
+
+/**
+ * sci_clk_set_parent - Set the parent of a TI SCI clock
+ * @hw: clock to set parent for
+ * @index: new parent index for the clock
+ *
+ * Sets the parent of a TI SCI clock. Return TI SCI protocol status.
+ */
+static int sci_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+	struct sci_clk *clk = to_sci_clk(hw);
+
+	return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
+					      clk->clk_id,
+					      index + 1 + clk->clk_id);
+}
+
+static const struct clk_ops sci_clk_ops = {
+	.prepare = sci_clk_prepare,
+	.unprepare = sci_clk_unprepare,
+	.is_prepared = sci_clk_is_prepared,
+	.recalc_rate = sci_clk_recalc_rate,
+	.determine_rate = sci_clk_determine_rate,
+	.set_rate = sci_clk_set_rate,
+	.get_parent = sci_clk_get_parent,
+	.set_parent = sci_clk_set_parent,
+};
+
+/**
+ * _sci_clk_get - Gets a handle for an SCI clock
+ * @provider: Handle to SCI clock provider
+ * @dev_id: device ID for the clock to register
+ * @clk_id: clock ID for the clock to register
+ * @parse_parents: indicator whether parents for this clock should be handled
+ *
+ * Gets a handle to an existing TI SCI clock, or builds a new clock
+ * entry and registers it with the common clock framework. Called from
+ * the common clock framework, when a corresponding of_clk_get call is
+ * executed, or recursively from itself when parsing parent clocks.
+ * Returns a pointer to the clock struct, or ERR_PTR value in failure.
+ */
+static struct clk *_sci_clk_get(struct sci_clk_provider *provider,
+				u16 dev_id, u8 clk_id, bool parse_parents)
+{
+	struct clk_init_data init = { NULL };
+	struct clk *clk;
+	struct sci_clk *sci_clk = NULL;
+	char name[20];
+	char **parent_names = NULL;
+	int i;
+	int ret;
+
+	list_for_each_entry(sci_clk, &provider->clocks, node)
+		if (sci_clk->dev_id == dev_id && sci_clk->clk_id == clk_id)
+			return sci_clk->hw.clk;
+
+	sci_clk = devm_kzalloc(provider->dev, sizeof(*sci_clk), GFP_KERNEL);
+	if (!sci_clk) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	sci_clk->dev_id = dev_id;
+	sci_clk->clk_id = clk_id;
+	sci_clk->provider = provider;
+
+	if (parse_parents) {
+		ret = provider->ops->get_num_parents(provider->sci, dev_id,
+						     clk_id,
+						     &init.num_parents);
+		if (ret)
+			goto err;
+	}
+
+	snprintf(name, 20, "%s:%d:%d", dev_name(provider->dev), sci_clk->dev_id,
+		 sci_clk->clk_id);
+
+	init.name = name;
+
+	if (init.num_parents < 2)
+		init.num_parents = 0;
+
+	if (init.num_parents) {
+		parent_names = devm_kcalloc(provider->dev, init.num_parents,
+					    sizeof(char *), GFP_KERNEL);
+
+		if (!parent_names) {
+			ret = -ENOMEM;
+			goto err;
+		}
+
+		for (i = 0; i < init.num_parents; i++) {
+			char *parent_name;
+
+			parent_name = devm_kzalloc(provider->dev, 20,
+						   GFP_KERNEL);
+			if (!parent_name) {
+				ret = -ENOMEM;
+				goto err;
+			}
+			snprintf(parent_name, 20, "%s:%d:%d",
+				 dev_name(provider->dev), sci_clk->dev_id,
+				 sci_clk->clk_id + 1 + i);
+			parent_names[i] = parent_name;
+
+			_sci_clk_get(provider, dev_id, clk_id + 1 + i, false);
+		}
+		init.parent_names = (const char * const *)parent_names;
+	}
+
+	init.ops = &sci_clk_ops;
+	sci_clk->hw.init = &init;
+
+	clk = devm_clk_register(provider->dev, &sci_clk->hw);
+
+	if (IS_ERR(clk)) {
+		ret = PTR_ERR(clk);
+		dev_err(provider->dev, "failed clk register with %d\n", ret);
+		goto err;
+	} else {
+		list_add(&sci_clk->node, &provider->clocks);
+	}
+
+	return clk;
+
+err:
+	if (parent_names) {
+		for (i = 0; i < init.num_parents; i++)
+			devm_kfree(provider->dev, parent_names[i]);
+
+		devm_kfree(provider->dev, parent_names);
+	}
+
+	devm_kfree(provider->dev, sci_clk);
+
+	return ERR_PTR(ret);
+}
+
+/**
+ * sci_clk_get - Xlate function for getting clock handles
+ * @clkspec: device tree clock specifier
+ * @data: pointer to the clock provider
+ *
+ * Xlate function for retrieving clock TI SCI clock handles based on
+ * device tree clock specifier. Called from the common clock framework,
+ * when a corresponding of_clk_get call is executed. Returns a pointer
+ * to the TI SCI clock struct, or ERR_PTR value in failure.
+ */
+static struct clk *sci_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct sci_clk_provider *provider = data;
+	struct clk *clk;
+	u16 dev_id;
+	u8 clk_id;
+
+	if (clkspec->args_count != 2)
+		return ERR_PTR(-EINVAL);
+
+	mutex_lock(&provider->lock);
+
+	dev_id = clkspec->args[0];
+	clk_id = clkspec->args[1];
+
+	clk = _sci_clk_get(provider, dev_id, clk_id, true);
+
+	mutex_unlock(&provider->lock);
+
+	return clk;
+}
+
+static const struct of_device_id ti_sci_clk_of_match[] = {
+	{ .compatible = "ti,sci-clk" },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ti_sci_clk_of_match);
+
+/**
+ * ti_sci_clk_parse_flags - Helper function to parse clock flag arrays
+ * @dev: clock provider device
+ * @np: device node pointer for the clock provider
+ * @list_name: property name containing the clocks list
+ * @flag: flag to apply to the list of clocks
+ *
+ * Parses a DT list based on the provided data, and applies the flag value
+ * for each of the clocks identified by the list. Return 0 for success,
+ * negative error value for failure.
+ */
+static int ti_sci_clk_parse_flags(struct device *dev, struct device_node *np,
+				  const char *list_name, u8 flag)
+{
+	int num_clks;
+	int i;
+
+	num_clks = of_count_phandle_with_args(np, list_name, "#clock-cells");
+
+	for (i = 0; i < num_clks; i++) {
+		struct of_phandle_args clkspec;
+		struct clk_hw *hw;
+		struct sci_clk *sci_clk;
+		struct clk *clk;
+		int ret;
+
+		ret = of_parse_phandle_with_args(np, list_name, "#clock-cells",
+						 i, &clkspec);
+		if (ret) {
+			dev_err(dev, "Failed to parse %s[%d] = %d\n", list_name,
+				i, ret);
+			return ret;
+		}
+		clk = of_clk_get_from_provider(&clkspec);
+		if (IS_ERR(clk)) {
+			dev_err(dev, "clk_get failed for %s[%d] = %ld\n",
+				list_name, i, PTR_ERR(clk));
+			return PTR_ERR(clk);
+		}
+		hw = __clk_get_hw(clk);
+		sci_clk = to_sci_clk(hw);
+
+		sci_clk->flags |= flag;
+	}
+
+	return 0;
+}
+
+/**
+ * ti_sci_clk_probe - Probe function for the TI SCI clock driver
+ * @pdev: platform device pointer to be probed
+ *
+ * Probes the TI SCI clock device. Allocates a new clock provider
+ * and registers this to the common clock framework. Also applies
+ * any required flags to the identified clocks via clock lists
+ * supplied from DT. Returns 0 for success, negative error value
+ * for failure.
+ */
+static int ti_sci_clk_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct sci_clk_provider *provider;
+	const struct ti_sci_handle *handle;
+
+	if (!np) {
+		dev_err(dev, "OF data missing\n");
+		return -EINVAL;
+	}
+
+	handle = devm_ti_sci_get_handle(dev);
+	if (IS_ERR(handle))
+		return PTR_ERR(handle);
+
+	provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
+	if (!provider)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&provider->clocks);
+	mutex_init(&provider->lock);
+
+	provider->sci = handle;
+	provider->ops = &handle->ops.clk_ops;
+	provider->dev = dev;
+
+	of_clk_add_provider(np, sci_clk_get, provider);
+
+	ti_sci_clk_parse_flags(dev, np, "ti,ssc-clocks", SCI_CLK_SSC_ENABLE);
+	ti_sci_clk_parse_flags(dev, np, "ti,allow-freq-change-clocks",
+			       SCI_CLK_ALLOW_FREQ_CHANGE);
+	ti_sci_clk_parse_flags(dev, np, "ti,input-term-clocks",
+			       SCI_CLK_INPUT_TERMINATION);
+
+	dev_info(dev, "initialized.\n");
+
+	return 0;
+}
+
+/**
+ * ti_sci_clk_remove - Remove TI SCI clock device
+ * @pdev: platform device pointer for the device to be removed
+ *
+ * Removes the TI SCI device. Unregisters the clock provider registered
+ * via common clock framework. Any memory allocated for the device will
+ * be free'd silently via the devm framework. Returns 0 always.
+ */
+static int ti_sci_clk_remove(struct platform_device *pdev)
+{
+	of_clk_del_provider(pdev->dev.of_node);
+
+	return 0;
+}
+
+static struct platform_driver ti_sci_clk_driver = {
+	.probe = ti_sci_clk_probe,
+	.remove = ti_sci_clk_remove,
+	.driver = {
+		.name = "ti-sci-clk",
+		.of_match_table = of_match_ptr(ti_sci_clk_of_match),
+	},
+};
+module_platform_driver(ti_sci_clk_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("TI System Control Interface(SCI) Clock driver");
+MODULE_AUTHOR("Tero Kristo");
+MODULE_ALIAS("platform:ti-sci-clk");
-- 
2.9.1.200.gb1ec08f

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Re: [PATCH 3/3] clk: keystone: Add sci-clk driver support

[Stephen Boyd]

On 08/19, Nishanth Menon wrote:
>  THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
>  M:	Hans Verkuil <hverkuil@xs4all.nl>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index e2d9bd760c84..d1724999be78 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -179,6 +179,19 @@ config COMMON_CLK_NXP
>  	---help---
>  	  Support for clock providers on NXP platforms.
>  
> +if COMMON_CLK_KEYSTONE

Why not depends on COMMON_CLK_KEYSTONE? Or make the tristate have
an if COMMON_CLK_KEYSTONE after it? So far an if <CONFIG> hasn't
happened in this file. And is anything inside
drivers/clk/keystone used by this driver? Maybe this if statement
can just be dropped entirely and then the keystone/Makefile
updated?

> +
> +config TI_SCI_CLK
> +	tristate "TI System Control Interface clock drivers"
> +	depends on TI_SCI_PROTOCOL || COMPILE_TEST
> +	default y

default TI_SCI_PROTOCOL?

> +	help
> +	  This adds the clock driver support over TI System Control Interface.
> +	  If you wish to use clock resources from the PMMC firmware, say Y.
> +	  Otherwise, say N.
> +
> +endif # COMMON_CLK_KEYSTONE
> +
>  config COMMON_CLK_PALMAS
>  	tristate "Clock driver for TI Palmas devices"
>  	depends on MFD_PALMAS
> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
> new file mode 100644
> index 000000000000..6c43e097e6d6
> --- /dev/null
> +++ b/drivers/clk/keystone/sci-clk.c
> @@ -0,0 +1,539 @@
> +/*
> + * SCI Clock driver for keystone based devices
> + *
> + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
> + *	Tero Kristo <t-kristo@ti.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#include <linux/clk.h>

Is this include used?

> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/soc/ti/ti_sci_protocol.h>
> +
> +#define SCI_CLK_SSC_ENABLE		BIT(0)
> +#define SCI_CLK_ALLOW_FREQ_CHANGE	BIT(1)
> +#define SCI_CLK_INPUT_TERMINATION	BIT(2)
> +
> +/**
> + * struct sci_clk_provider - TI SCI clock provider representation
> + * @sci:    Handle to the System Control Interface protocol handler
> + * @ops:    Pointer to the SCI ops to be used by the clocks
> + * @dev:    Device pointer for the clock provider
> + * @clocks: List of all registered clocks
> + * @lock:   Mutex for locking access to the @clocks list
> + */
> +struct sci_clk_provider {
> +	const struct ti_sci_handle *sci;
> +	const struct ti_sci_clk_ops *ops;
> +	struct device *dev;
> +	struct list_head clocks;
> +	struct mutex lock; /* Protects access to the @clocks list */
> +};
> +
> +/**
> + * struct sci_clk - TI SCI clock representation
> + * @hw:		 Hardware clock cookie for common clock framework
> + * @dev_id:	 Device index
> + * @clk_id:	 Clock index
> + * @node:	 Clocks list link
> + * @provider:	 Master clock provider
> + * @flags:	 Flags for the clock
> + */
> +struct sci_clk {
> +	struct clk_hw hw;
> +	u16 dev_id;
> +	u8 clk_id;
> +	struct list_head node;
> +	struct sci_clk_provider *provider;
> +	u8 flags;
> +};
> +
> +#define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw)
> +
> +/**
> + * sci_clk_prepare - Prepare (enable) a TI SCI clock
> + * @hw: clock to prepare
> + *
> + * Prepares a clock to be actively used. Returns the SCI protocol status.
> + */
> +static int sci_clk_prepare(struct clk_hw *hw)
> +{
> +	struct sci_clk *clk = to_sci_clk(hw);
> +	bool enable_ssc = clk->flags & SCI_CLK_SSC_ENABLE;
> +	bool allow_freq_change = clk->flags & SCI_CLK_ALLOW_FREQ_CHANGE;
> +	bool input_termination = clk->flags & SCI_CLK_INPUT_TERMINATION;
> +
> +	return clk->provider->ops->get_clock(clk->provider->sci, clk->dev_id,
> +					     clk->clk_id, enable_ssc,
> +					     allow_freq_change,
> +					     input_termination);
> +}
> +
> +/**
> + * sci_clk_unprepare - Un-prepares (disables) a TI SCI clock
> + * @hw: clock to unprepare
> + *
> + * Un-prepares a clock from active state.
> + */
> +static void sci_clk_unprepare(struct clk_hw *hw)
> +{
> +	struct sci_clk *clk = to_sci_clk(hw);
> +	int ret;
> +
> +	ret = clk->provider->ops->put_clock(clk->provider->sci, clk->dev_id,
> +					    clk->clk_id);
> +	if (ret)
> +		dev_err(clk->provider->dev,
> +			"unprepare failed for dev=%d, clk=%d, ret=%d\n",
> +			clk->dev_id, clk->clk_id, ret);
> +}
> +
> +/**
> + * sci_clk_is_prepared - Check if a TI SCI clock is prepared or not
> + * @hw: clock to check status for
> + *
> + * Checks if a clock is prepared (enabled) in hardware. Returns non-zero
> + * value if clock is enabled, zero otherwise.
> + */
> +static int sci_clk_is_prepared(struct clk_hw *hw)
> +{
> +	struct sci_clk *clk = to_sci_clk(hw);
> +	bool req_state, current_state;
> +	int ret;
> +
> +	ret = clk->provider->ops->is_on(clk->provider->sci, clk->dev_id,
> +					clk->clk_id, &req_state,
> +					&current_state);
> +	if (ret) {
> +		dev_err(clk->provider->dev,
> +			"prepare failed for dev=%d, clk=%d, ret=%d\n",

s/prepare/is_prepared/ ?

> +			clk->dev_id, clk->clk_id, ret);
> +		return 0;
> +	}
> +
> +	return req_state;
> +}
> +
> +/**
> + * sci_clk_recalc_rate - Get clock rate for a TI SCI clock
> + * @hw: clock to get rate for
> + * @parent_rate: parent rate provided by common clock framework, not used
> + *
> + * Gets the current clock rate of a TI SCI clock. Returns the current
> + * clock rate, or zero in failure.
> + */
> +static unsigned long sci_clk_recalc_rate(struct clk_hw *hw,
> +					 unsigned long parent_rate)
> +{
> +	struct sci_clk *clk = to_sci_clk(hw);
> +	u64 freq;
> +	int ret;
> +
> +	ret = clk->provider->ops->get_freq(clk->provider->sci, clk->dev_id,
> +					   clk->clk_id, &freq);
> +	if (ret) {
> +		dev_err(clk->provider->dev,
> +			"recalc-rate failed for dev=%d, clk=%d, ret=%d\n",
> +			clk->dev_id, clk->clk_id, ret);
> +		return 0;
> +	}
> +
> +	return (u32)freq;
> +}
> +
> +/**
> + * sci_clk_determine_rate - Determines a clock rate a clock can be set to
> + * @hw: clock to change rate for
> + * @req: requested rate configuration for the clock
> + *
> + * Determines a suitable clock rate and parent for a TI SCI clock.
> + * The parent handling is un-used, as generally the parent clock rates
> + * are not known by the kernel; instead these are internally handled
> + * by the firmware. Returns the new clock rate that can be set for the
> + * clock, or 0 in failure.
> + */
> +static int sci_clk_determine_rate(struct clk_hw *hw,
> +				  struct clk_rate_request *req)
> +{
> +	struct sci_clk *clk = to_sci_clk(hw);
> +	u64 new_rate;
> +	int ret;
> +
> +	ret = clk->provider->ops->get_best_match_freq(clk->provider->sci,
> +						      clk->dev_id,
> +						      clk->clk_id,
> +						      req->min_rate,
> +						      req->rate,
> +						      req->max_rate,
> +						      &new_rate);
> +	if (ret) {
> +		dev_err(clk->provider->dev,
> +			"determine-rate failed for dev=%d, clk=%d, ret=%d\n",
> +			clk->dev_id, clk->clk_id, ret);
> +		return 0;
> +	}
> +
> +	return (int)new_rate;

determine rate should return a negative number on failure and 0
on success. The actual rate that was found should go into
req->rate. This looks broken.

> +}
> +
> +/**
> + * sci_clk_set_rate - Set rate for a TI SCI clock
> + * @hw: clock to change rate for
> + * @rate: target rate for the clock
> + * @parent_rate: rate of the clock parent, not used for TI SCI clocks
> + *
> + * Sets a clock frequency for a TI SCI clock. Returns the TI SCI
> + * protocol status.
> + */
> +static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> +			    unsigned long parent_rate)
> +{
> +	struct sci_clk *clk = to_sci_clk(hw);
> +	u64 freq = rate;

We can't just pass rate three times?

> +
> +	return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
> +					    clk->clk_id, freq, freq, freq);
> +}
> +
> +/**
> + * sci_clk_get_parent - Get the current parent of a TI SCI clock
> + * @hw: clock to get parent for
> + *
> + * Returns the index of the currently selected parent for a TI SCI clock.
> + */
> +static u8 sci_clk_get_parent(struct clk_hw *hw)
> +{
> +	struct sci_clk *clk = to_sci_clk(hw);
> +	u8 parent_id;
> +	int ret;
> +
> +	ret = clk->provider->ops->get_parent(clk->provider->sci, clk->dev_id,
> +					     clk->clk_id, &parent_id);
> +	if (ret) {
> +		dev_err(clk->provider->dev,
> +			"get-parent failed for dev=%d, clk=%d, ret=%d\n",
> +			clk->dev_id, clk->clk_id, ret);
> +		return 0;
> +	}
> +
> +	parent_id = parent_id - clk->clk_id - 1;
> +
> +	return parent_id;

Why not just return parent_id - clk->clk_id - 1?

> +}
> +
> +/**
> + * sci_clk_set_parent - Set the parent of a TI SCI clock
> + * @hw: clock to set parent for
> + * @index: new parent index for the clock
> + *
> + * Sets the parent of a TI SCI clock. Return TI SCI protocol status.
> + */
> +static int sci_clk_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	struct sci_clk *clk = to_sci_clk(hw);
> +
> +	return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
> +					      clk->clk_id,
> +					      index + 1 + clk->clk_id);
> +}
> +
> +static const struct clk_ops sci_clk_ops = {
> +	.prepare = sci_clk_prepare,
> +	.unprepare = sci_clk_unprepare,
> +	.is_prepared = sci_clk_is_prepared,
> +	.recalc_rate = sci_clk_recalc_rate,
> +	.determine_rate = sci_clk_determine_rate,
> +	.set_rate = sci_clk_set_rate,
> +	.get_parent = sci_clk_get_parent,
> +	.set_parent = sci_clk_set_parent,
> +};
> +
> +/**
> + * _sci_clk_get - Gets a handle for an SCI clock
> + * @provider: Handle to SCI clock provider
> + * @dev_id: device ID for the clock to register
> + * @clk_id: clock ID for the clock to register
> + * @parse_parents: indicator whether parents for this clock should be handled
> + *
> + * Gets a handle to an existing TI SCI clock, or builds a new clock
> + * entry and registers it with the common clock framework. Called from
> + * the common clock framework, when a corresponding of_clk_get call is
> + * executed, or recursively from itself when parsing parent clocks.
> + * Returns a pointer to the clock struct, or ERR_PTR value in failure.
> + */

Please move this driver to clk_hw_register() and friends. This on
the fly clk generation is scary considering how we hold locks
while the provider is asked to give us the pointer, so allocating
and registering clks (basically reentering the CCF again) could
lead to a locking nightmare. Best to avoid that.

> +static struct clk *_sci_clk_get(struct sci_clk_provider *provider,
> +				u16 dev_id, u8 clk_id, bool parse_parents)
> +{
> +	struct clk_init_data init = { NULL };
> +	struct clk *clk;
> +	struct sci_clk *sci_clk = NULL;
> +	char name[20];
> +	char **parent_names = NULL;
> +	int i;
> +	int ret;
> +
> +	list_for_each_entry(sci_clk, &provider->clocks, node)
> +		if (sci_clk->dev_id == dev_id && sci_clk->clk_id == clk_id)
> +			return sci_clk->hw.clk;
> +
> +	sci_clk = devm_kzalloc(provider->dev, sizeof(*sci_clk), GFP_KERNEL);
> +	if (!sci_clk) {
> +		ret = -ENOMEM;
> +		goto err;
> +	}
> +
> +	sci_clk->dev_id = dev_id;
> +	sci_clk->clk_id = clk_id;
> +	sci_clk->provider = provider;
> +
> +	if (parse_parents) {
> +		ret = provider->ops->get_num_parents(provider->sci, dev_id,
> +						     clk_id,
> +						     &init.num_parents);
> +		if (ret)
> +			goto err;
> +	}
> +
> +	snprintf(name, 20, "%s:%d:%d", dev_name(provider->dev), sci_clk->dev_id,
> +		 sci_clk->clk_id);

I hope we don't make dev_name() longer than 20 characters

> +
> +	init.name = name;
> +
> +	if (init.num_parents < 2)
> +		init.num_parents = 0;
> +
> +	if (init.num_parents) {
> +		parent_names = devm_kcalloc(provider->dev, init.num_parents,
> +					    sizeof(char *), GFP_KERNEL);
> +
> +		if (!parent_names) {
> +			ret = -ENOMEM;
> +			goto err;
> +		}
> +
> +		for (i = 0; i < init.num_parents; i++) {
> +			char *parent_name;
> +
> +			parent_name = devm_kzalloc(provider->dev, 20,
> +						   GFP_KERNEL);
> +			if (!parent_name) {
> +				ret = -ENOMEM;
> +				goto err;
> +			}
> +			snprintf(parent_name, 20, "%s:%d:%d",
> +				 dev_name(provider->dev), sci_clk->dev_id,
> +				 sci_clk->clk_id + 1 + i);
> +			parent_names[i] = parent_name;
> +
> +			_sci_clk_get(provider, dev_id, clk_id + 1 + i, false);
> +		}
> +		init.parent_names = (const char * const *)parent_names;
> +	}
> +
> +	init.ops = &sci_clk_ops;
> +	sci_clk->hw.init = &init;
> +
> +	clk = devm_clk_register(provider->dev, &sci_clk->hw);
> +
> +	if (IS_ERR(clk)) {
> +		ret = PTR_ERR(clk);
> +		dev_err(provider->dev, "failed clk register with %d\n", ret);
> +		goto err;
> +	} else {
> +		list_add(&sci_clk->node, &provider->clocks);
> +	}
> +
> +	return clk;
> +
> +err:
> +	if (parent_names) {
> +		for (i = 0; i < init.num_parents; i++)
> +			devm_kfree(provider->dev, parent_names[i]);
> +
> +		devm_kfree(provider->dev, parent_names);
> +	}
> +
> +	devm_kfree(provider->dev, sci_clk);
> +
> +	return ERR_PTR(ret);
> +}
> +
> +/**
> + * sci_clk_get - Xlate function for getting clock handles
> + * @clkspec: device tree clock specifier
> + * @data: pointer to the clock provider
> + *
> + * Xlate function for retrieving clock TI SCI clock handles based on
> + * device tree clock specifier. Called from the common clock framework,
> + * when a corresponding of_clk_get call is executed. Returns a pointer
> + * to the TI SCI clock struct, or ERR_PTR value in failure.
> + */
> +static struct clk *sci_clk_get(struct of_phandle_args *clkspec, void *data)
> +{
> +	struct sci_clk_provider *provider = data;
> +	struct clk *clk;
> +	u16 dev_id;
> +	u8 clk_id;
> +
> +	if (clkspec->args_count != 2)
> +		return ERR_PTR(-EINVAL);
> +
> +	mutex_lock(&provider->lock);
> +
> +	dev_id = clkspec->args[0];
> +	clk_id = clkspec->args[1];
> +
> +	clk = _sci_clk_get(provider, dev_id, clk_id, true);
> +
> +	mutex_unlock(&provider->lock);
> +
> +	return clk;
> +}
> +
> +static const struct of_device_id ti_sci_clk_of_match[] = {
> +	{ .compatible = "ti,sci-clk" },
> +	{ /* Sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, ti_sci_clk_of_match);
> +
> +/**
> + * ti_sci_clk_parse_flags - Helper function to parse clock flag arrays
> + * @dev: clock provider device
> + * @np: device node pointer for the clock provider
> + * @list_name: property name containing the clocks list
> + * @flag: flag to apply to the list of clocks
> + *
> + * Parses a DT list based on the provided data, and applies the flag value
> + * for each of the clocks identified by the list. Return 0 for success,
> + * negative error value for failure.
> + */
> +static int ti_sci_clk_parse_flags(struct device *dev, struct device_node *np,
> +				  const char *list_name, u8 flag)
> +{
> +	int num_clks;
> +	int i;
> +
> +	num_clks = of_count_phandle_with_args(np, list_name, "#clock-cells");
> +
> +	for (i = 0; i < num_clks; i++) {
> +		struct of_phandle_args clkspec;
> +		struct clk_hw *hw;
> +		struct sci_clk *sci_clk;
> +		struct clk *clk;
> +		int ret;
> +
> +		ret = of_parse_phandle_with_args(np, list_name, "#clock-cells",
> +						 i, &clkspec);

Do we really need to parse the phandle and get a clk from the
provider that is our own driver? We should be able to get a hw
pointer by calling our xlate_hw function with the two cells
instead and completely bypass generating a clk structure.

> +		if (ret) {
> +			dev_err(dev, "Failed to parse %s[%d] = %d\n", list_name,
> +				i, ret);
> +			return ret;
> +		}
> +		clk = of_clk_get_from_provider(&clkspec);
> +		if (IS_ERR(clk)) {
> +			dev_err(dev, "clk_get failed for %s[%d] = %ld\n",
> +				list_name, i, PTR_ERR(clk));
> +			return PTR_ERR(clk);
> +		}
> +		hw = __clk_get_hw(clk);
> +		sci_clk = to_sci_clk(hw);
> +
> +		sci_clk->flags |= flag;
> +	}
> +
> +	return 0;
> +}
> +
> +/**
> + * ti_sci_clk_probe - Probe function for the TI SCI clock driver
> + * @pdev: platform device pointer to be probed
> + *
> + * Probes the TI SCI clock device. Allocates a new clock provider
> + * and registers this to the common clock framework. Also applies
> + * any required flags to the identified clocks via clock lists
> + * supplied from DT. Returns 0 for success, negative error value
> + * for failure.
> + */
> +static int ti_sci_clk_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *np = dev->of_node;
> +	struct sci_clk_provider *provider;
> +	const struct ti_sci_handle *handle;
> +
> +	if (!np) {
> +		dev_err(dev, "OF data missing\n");
> +		return -EINVAL;
> +	}

Is this ever true? Seems useless.

> +
> +	handle = devm_ti_sci_get_handle(dev);
> +	if (IS_ERR(handle))
> +		return PTR_ERR(handle);
> +
> +	provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
> +	if (!provider)
> +		return -ENOMEM;
> +
> +	INIT_LIST_HEAD(&provider->clocks);
> +	mutex_init(&provider->lock);
> +
> +	provider->sci = handle;
> +	provider->ops = &handle->ops.clk_ops;
> +	provider->dev = dev;
> +
> +	of_clk_add_provider(np, sci_clk_get, provider);

This could fail.

> +
> +	ti_sci_clk_parse_flags(dev, np, "ti,ssc-clocks", SCI_CLK_SSC_ENABLE);
> +	ti_sci_clk_parse_flags(dev, np, "ti,allow-freq-change-clocks",
> +			       SCI_CLK_ALLOW_FREQ_CHANGE);
> +	ti_sci_clk_parse_flags(dev, np, "ti,input-term-clocks",
> +			       SCI_CLK_INPUT_TERMINATION);
> +
> +	dev_info(dev, "initialized.\n");

debug noise?

> +
> +	return 0;
> +}
> +
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 3/3] clk: keystone: Add sci-clk driver support

[Tero Kristo]

Hi Stephen,

Thanks for comments, inlined replies below.

On 24/08/16 11:34, Stephen Boyd wrote:
> On 08/19, Nishanth Menon wrote:
>>  THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
>>  M:	Hans Verkuil <hverkuil@xs4all.nl>
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index e2d9bd760c84..d1724999be78 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -179,6 +179,19 @@ config COMMON_CLK_NXP
>>  	---help---
>>  	  Support for clock providers on NXP platforms.
>>
>> +if COMMON_CLK_KEYSTONE
>
> Why not depends on COMMON_CLK_KEYSTONE? Or make the tristate have
> an if COMMON_CLK_KEYSTONE after it? So far an if <CONFIG> hasn't
> happened in this file. And is anything inside
> drivers/clk/keystone used by this driver? Maybe this if statement
> can just be dropped entirely and then the keystone/Makefile
> updated?

Yea will fix that.

>
>> +
>> +config TI_SCI_CLK
>> +	tristate "TI System Control Interface clock drivers"
>> +	depends on TI_SCI_PROTOCOL || COMPILE_TEST
>> +	default y
>
> default TI_SCI_PROTOCOL?

That too.

>
>> +	help
>> +	  This adds the clock driver support over TI System Control Interface.
>> +	  If you wish to use clock resources from the PMMC firmware, say Y.
>> +	  Otherwise, say N.
>> +
>> +endif # COMMON_CLK_KEYSTONE
>> +
>>  config COMMON_CLK_PALMAS
>>  	tristate "Clock driver for TI Palmas devices"
>>  	depends on MFD_PALMAS
>> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
>> new file mode 100644
>> index 000000000000..6c43e097e6d6
>> --- /dev/null
>> +++ b/drivers/clk/keystone/sci-clk.c
>> @@ -0,0 +1,539 @@
>> +/*
>> + * SCI Clock driver for keystone based devices
>> + *
>> + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
>> + *	Tero Kristo <t-kristo@ti.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +#include <linux/clk.h>
>
> Is this include used?

Yes, it seems I get a compile fail if this is not included:

   CC      drivers/clk/keystone/sci-clk.o
drivers/clk/keystone/sci-clk.c: In function 'ti_sci_clk_parse_flags':
drivers/clk/keystone/sci-clk.c:444:3: error: implicit declaration of 
function 'of_clk_get_from_provider' [-Werror=implicit-function-declaration]
    clk = of_clk_get_from_provider(&clkspec);

However, as there is the new API for clk_hw xlate, not sure if this is 
needed once I convert the driver to use that. Will check.

>
>> +#include <linux/clk-provider.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +#include <linux/soc/ti/ti_sci_protocol.h>
>> +
>> +#define SCI_CLK_SSC_ENABLE		BIT(0)
>> +#define SCI_CLK_ALLOW_FREQ_CHANGE	BIT(1)
>> +#define SCI_CLK_INPUT_TERMINATION	BIT(2)
>> +
>> +/**
>> + * struct sci_clk_provider - TI SCI clock provider representation
>> + * @sci:    Handle to the System Control Interface protocol handler
>> + * @ops:    Pointer to the SCI ops to be used by the clocks
>> + * @dev:    Device pointer for the clock provider
>> + * @clocks: List of all registered clocks
>> + * @lock:   Mutex for locking access to the @clocks list
>> + */
>> +struct sci_clk_provider {
>> +	const struct ti_sci_handle *sci;
>> +	const struct ti_sci_clk_ops *ops;
>> +	struct device *dev;
>> +	struct list_head clocks;
>> +	struct mutex lock; /* Protects access to the @clocks list */
>> +};
>> +
>> +/**
>> + * struct sci_clk - TI SCI clock representation
>> + * @hw:		 Hardware clock cookie for common clock framework
>> + * @dev_id:	 Device index
>> + * @clk_id:	 Clock index
>> + * @node:	 Clocks list link
>> + * @provider:	 Master clock provider
>> + * @flags:	 Flags for the clock
>> + */
>> +struct sci_clk {
>> +	struct clk_hw hw;
>> +	u16 dev_id;
>> +	u8 clk_id;
>> +	struct list_head node;
>> +	struct sci_clk_provider *provider;
>> +	u8 flags;
>> +};
>> +
>> +#define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw)
>> +
>> +/**
>> + * sci_clk_prepare - Prepare (enable) a TI SCI clock
>> + * @hw: clock to prepare
>> + *
>> + * Prepares a clock to be actively used. Returns the SCI protocol status.
>> + */
>> +static int sci_clk_prepare(struct clk_hw *hw)
>> +{
>> +	struct sci_clk *clk = to_sci_clk(hw);
>> +	bool enable_ssc = clk->flags & SCI_CLK_SSC_ENABLE;
>> +	bool allow_freq_change = clk->flags & SCI_CLK_ALLOW_FREQ_CHANGE;
>> +	bool input_termination = clk->flags & SCI_CLK_INPUT_TERMINATION;
>> +
>> +	return clk->provider->ops->get_clock(clk->provider->sci, clk->dev_id,
>> +					     clk->clk_id, enable_ssc,
>> +					     allow_freq_change,
>> +					     input_termination);
>> +}
>> +
>> +/**
>> + * sci_clk_unprepare - Un-prepares (disables) a TI SCI clock
>> + * @hw: clock to unprepare
>> + *
>> + * Un-prepares a clock from active state.
>> + */
>> +static void sci_clk_unprepare(struct clk_hw *hw)
>> +{
>> +	struct sci_clk *clk = to_sci_clk(hw);
>> +	int ret;
>> +
>> +	ret = clk->provider->ops->put_clock(clk->provider->sci, clk->dev_id,
>> +					    clk->clk_id);
>> +	if (ret)
>> +		dev_err(clk->provider->dev,
>> +			"unprepare failed for dev=%d, clk=%d, ret=%d\n",
>> +			clk->dev_id, clk->clk_id, ret);
>> +}
>> +
>> +/**
>> + * sci_clk_is_prepared - Check if a TI SCI clock is prepared or not
>> + * @hw: clock to check status for
>> + *
>> + * Checks if a clock is prepared (enabled) in hardware. Returns non-zero
>> + * value if clock is enabled, zero otherwise.
>> + */
>> +static int sci_clk_is_prepared(struct clk_hw *hw)
>> +{
>> +	struct sci_clk *clk = to_sci_clk(hw);
>> +	bool req_state, current_state;
>> +	int ret;
>> +
>> +	ret = clk->provider->ops->is_on(clk->provider->sci, clk->dev_id,
>> +					clk->clk_id, &req_state,
>> +					&current_state);
>> +	if (ret) {
>> +		dev_err(clk->provider->dev,
>> +			"prepare failed for dev=%d, clk=%d, ret=%d\n",
>
> s/prepare/is_prepared/ ?

Will fix.

>
>> +			clk->dev_id, clk->clk_id, ret);
>> +		return 0;
>> +	}
>> +
>> +	return req_state;
>> +}
>> +
>> +/**
>> + * sci_clk_recalc_rate - Get clock rate for a TI SCI clock
>> + * @hw: clock to get rate for
>> + * @parent_rate: parent rate provided by common clock framework, not used
>> + *
>> + * Gets the current clock rate of a TI SCI clock. Returns the current
>> + * clock rate, or zero in failure.
>> + */
>> +static unsigned long sci_clk_recalc_rate(struct clk_hw *hw,
>> +					 unsigned long parent_rate)
>> +{
>> +	struct sci_clk *clk = to_sci_clk(hw);
>> +	u64 freq;
>> +	int ret;
>> +
>> +	ret = clk->provider->ops->get_freq(clk->provider->sci, clk->dev_id,
>> +					   clk->clk_id, &freq);
>> +	if (ret) {
>> +		dev_err(clk->provider->dev,
>> +			"recalc-rate failed for dev=%d, clk=%d, ret=%d\n",
>> +			clk->dev_id, clk->clk_id, ret);
>> +		return 0;
>> +	}
>> +
>> +	return (u32)freq;
>> +}
>> +
>> +/**
>> + * sci_clk_determine_rate - Determines a clock rate a clock can be set to
>> + * @hw: clock to change rate for
>> + * @req: requested rate configuration for the clock
>> + *
>> + * Determines a suitable clock rate and parent for a TI SCI clock.
>> + * The parent handling is un-used, as generally the parent clock rates
>> + * are not known by the kernel; instead these are internally handled
>> + * by the firmware. Returns the new clock rate that can be set for the
>> + * clock, or 0 in failure.
>> + */
>> +static int sci_clk_determine_rate(struct clk_hw *hw,
>> +				  struct clk_rate_request *req)
>> +{
>> +	struct sci_clk *clk = to_sci_clk(hw);
>> +	u64 new_rate;
>> +	int ret;
>> +
>> +	ret = clk->provider->ops->get_best_match_freq(clk->provider->sci,
>> +						      clk->dev_id,
>> +						      clk->clk_id,
>> +						      req->min_rate,
>> +						      req->rate,
>> +						      req->max_rate,
>> +						      &new_rate);
>> +	if (ret) {
>> +		dev_err(clk->provider->dev,
>> +			"determine-rate failed for dev=%d, clk=%d, ret=%d\n",
>> +			clk->dev_id, clk->clk_id, ret);
>> +		return 0;
>> +	}
>> +
>> +	return (int)new_rate;
>
> determine rate should return a negative number on failure and 0
> on success. The actual rate that was found should go into
> req->rate. This looks broken.

Yea it seems broken, I wonder how we haven't seen any issues with this 
in testing.... Apparently positive return values from this are 
interpreted as success. Having a quick look at clk.c seems to confirm this.

Anyway, will fix.

>
>> +}
>> +
>> +/**
>> + * sci_clk_set_rate - Set rate for a TI SCI clock
>> + * @hw: clock to change rate for
>> + * @rate: target rate for the clock
>> + * @parent_rate: rate of the clock parent, not used for TI SCI clocks
>> + *
>> + * Sets a clock frequency for a TI SCI clock. Returns the TI SCI
>> + * protocol status.
>> + */
>> +static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>> +			    unsigned long parent_rate)
>> +{
>> +	struct sci_clk *clk = to_sci_clk(hw);
>> +	u64 freq = rate;
>
> We can't just pass rate three times?

I believe we can, will fix.

>
>> +
>> +	return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
>> +					    clk->clk_id, freq, freq, freq);
>> +}
>> +
>> +/**
>> + * sci_clk_get_parent - Get the current parent of a TI SCI clock
>> + * @hw: clock to get parent for
>> + *
>> + * Returns the index of the currently selected parent for a TI SCI clock.
>> + */
>> +static u8 sci_clk_get_parent(struct clk_hw *hw)
>> +{
>> +	struct sci_clk *clk = to_sci_clk(hw);
>> +	u8 parent_id;
>> +	int ret;
>> +
>> +	ret = clk->provider->ops->get_parent(clk->provider->sci, clk->dev_id,
>> +					     clk->clk_id, &parent_id);
>> +	if (ret) {
>> +		dev_err(clk->provider->dev,
>> +			"get-parent failed for dev=%d, clk=%d, ret=%d\n",
>> +			clk->dev_id, clk->clk_id, ret);
>> +		return 0;
>> +	}
>> +
>> +	parent_id = parent_id - clk->clk_id - 1;
>> +
>> +	return parent_id;
>
> Why not just return parent_id - clk->clk_id - 1?

Yea will fix that. Looks like a remnant of debugging code (like many 
other mishaps in the driver actually.)

>
>> +}
>> +
>> +/**
>> + * sci_clk_set_parent - Set the parent of a TI SCI clock
>> + * @hw: clock to set parent for
>> + * @index: new parent index for the clock
>> + *
>> + * Sets the parent of a TI SCI clock. Return TI SCI protocol status.
>> + */
>> +static int sci_clk_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> +	struct sci_clk *clk = to_sci_clk(hw);
>> +
>> +	return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
>> +					      clk->clk_id,
>> +					      index + 1 + clk->clk_id);
>> +}
>> +
>> +static const struct clk_ops sci_clk_ops = {
>> +	.prepare = sci_clk_prepare,
>> +	.unprepare = sci_clk_unprepare,
>> +	.is_prepared = sci_clk_is_prepared,
>> +	.recalc_rate = sci_clk_recalc_rate,
>> +	.determine_rate = sci_clk_determine_rate,
>> +	.set_rate = sci_clk_set_rate,
>> +	.get_parent = sci_clk_get_parent,
>> +	.set_parent = sci_clk_set_parent,
>> +};
>> +
>> +/**
>> + * _sci_clk_get - Gets a handle for an SCI clock
>> + * @provider: Handle to SCI clock provider
>> + * @dev_id: device ID for the clock to register
>> + * @clk_id: clock ID for the clock to register
>> + * @parse_parents: indicator whether parents for this clock should be handled
>> + *
>> + * Gets a handle to an existing TI SCI clock, or builds a new clock
>> + * entry and registers it with the common clock framework. Called from
>> + * the common clock framework, when a corresponding of_clk_get call is
>> + * executed, or recursively from itself when parsing parent clocks.
>> + * Returns a pointer to the clock struct, or ERR_PTR value in failure.
>> + */
>
> Please move this driver to clk_hw_register() and friends. This on
> the fly clk generation is scary considering how we hold locks
> while the provider is asked to give us the pointer, so allocating
> and registering clks (basically reentering the CCF again) could
> lead to a locking nightmare. Best to avoid that.

Ok, so just converting the driver to use provider->get_hw should be 
enough? This seems to be a relatively new API in the CCF. Will look at that.

>
>> +static struct clk *_sci_clk_get(struct sci_clk_provider *provider,
>> +				u16 dev_id, u8 clk_id, bool parse_parents)
>> +{
>> +	struct clk_init_data init = { NULL };
>> +	struct clk *clk;
>> +	struct sci_clk *sci_clk = NULL;
>> +	char name[20];
>> +	char **parent_names = NULL;
>> +	int i;
>> +	int ret;
>> +
>> +	list_for_each_entry(sci_clk, &provider->clocks, node)
>> +		if (sci_clk->dev_id == dev_id && sci_clk->clk_id == clk_id)
>> +			return sci_clk->hw.clk;
>> +
>> +	sci_clk = devm_kzalloc(provider->dev, sizeof(*sci_clk), GFP_KERNEL);
>> +	if (!sci_clk) {
>> +		ret = -ENOMEM;
>> +		goto err;
>> +	}
>> +
>> +	sci_clk->dev_id = dev_id;
>> +	sci_clk->clk_id = clk_id;
>> +	sci_clk->provider = provider;
>> +
>> +	if (parse_parents) {
>> +		ret = provider->ops->get_num_parents(provider->sci, dev_id,
>> +						     clk_id,
>> +						     &init.num_parents);
>> +		if (ret)
>> +			goto err;
>> +	}
>> +
>> +	snprintf(name, 20, "%s:%d:%d", dev_name(provider->dev), sci_clk->dev_id,
>> +		 sci_clk->clk_id);
>
> I hope we don't make dev_name() longer than 20 characters

Shall I just increase the size of the buffer and add a length check? 
Using kmalloc or something here seems overkill, as the name gets copied 
by CCF anyway.

>
>> +
>> +	init.name = name;
>> +
>> +	if (init.num_parents < 2)
>> +		init.num_parents = 0;
>> +
>> +	if (init.num_parents) {
>> +		parent_names = devm_kcalloc(provider->dev, init.num_parents,
>> +					    sizeof(char *), GFP_KERNEL);
>> +
>> +		if (!parent_names) {
>> +			ret = -ENOMEM;
>> +			goto err;
>> +		}
>> +
>> +		for (i = 0; i < init.num_parents; i++) {
>> +			char *parent_name;
>> +
>> +			parent_name = devm_kzalloc(provider->dev, 20,
>> +						   GFP_KERNEL);
>> +			if (!parent_name) {
>> +				ret = -ENOMEM;
>> +				goto err;
>> +			}
>> +			snprintf(parent_name, 20, "%s:%d:%d",
>> +				 dev_name(provider->dev), sci_clk->dev_id,
>> +				 sci_clk->clk_id + 1 + i);
>> +			parent_names[i] = parent_name;
>> +
>> +			_sci_clk_get(provider, dev_id, clk_id + 1 + i, false);
>> +		}
>> +		init.parent_names = (const char * const *)parent_names;
>> +	}
>> +
>> +	init.ops = &sci_clk_ops;
>> +	sci_clk->hw.init = &init;
>> +
>> +	clk = devm_clk_register(provider->dev, &sci_clk->hw);
>> +
>> +	if (IS_ERR(clk)) {
>> +		ret = PTR_ERR(clk);
>> +		dev_err(provider->dev, "failed clk register with %d\n", ret);
>> +		goto err;
>> +	} else {
>> +		list_add(&sci_clk->node, &provider->clocks);
>> +	}
>> +
>> +	return clk;
>> +
>> +err:
>> +	if (parent_names) {
>> +		for (i = 0; i < init.num_parents; i++)
>> +			devm_kfree(provider->dev, parent_names[i]);
>> +
>> +		devm_kfree(provider->dev, parent_names);
>> +	}
>> +
>> +	devm_kfree(provider->dev, sci_clk);
>> +
>> +	return ERR_PTR(ret);
>> +}
>> +
>> +/**
>> + * sci_clk_get - Xlate function for getting clock handles
>> + * @clkspec: device tree clock specifier
>> + * @data: pointer to the clock provider
>> + *
>> + * Xlate function for retrieving clock TI SCI clock handles based on
>> + * device tree clock specifier. Called from the common clock framework,
>> + * when a corresponding of_clk_get call is executed. Returns a pointer
>> + * to the TI SCI clock struct, or ERR_PTR value in failure.
>> + */
>> +static struct clk *sci_clk_get(struct of_phandle_args *clkspec, void *data)
>> +{
>> +	struct sci_clk_provider *provider = data;
>> +	struct clk *clk;
>> +	u16 dev_id;
>> +	u8 clk_id;
>> +
>> +	if (clkspec->args_count != 2)
>> +		return ERR_PTR(-EINVAL);
>> +
>> +	mutex_lock(&provider->lock);
>> +
>> +	dev_id = clkspec->args[0];
>> +	clk_id = clkspec->args[1];
>> +
>> +	clk = _sci_clk_get(provider, dev_id, clk_id, true);
>> +
>> +	mutex_unlock(&provider->lock);
>> +
>> +	return clk;
>> +}
>> +
>> +static const struct of_device_id ti_sci_clk_of_match[] = {
>> +	{ .compatible = "ti,sci-clk" },
>> +	{ /* Sentinel */ },
>> +};
>> +MODULE_DEVICE_TABLE(of, ti_sci_clk_of_match);
>> +
>> +/**
>> + * ti_sci_clk_parse_flags - Helper function to parse clock flag arrays
>> + * @dev: clock provider device
>> + * @np: device node pointer for the clock provider
>> + * @list_name: property name containing the clocks list
>> + * @flag: flag to apply to the list of clocks
>> + *
>> + * Parses a DT list based on the provided data, and applies the flag value
>> + * for each of the clocks identified by the list. Return 0 for success,
>> + * negative error value for failure.
>> + */
>> +static int ti_sci_clk_parse_flags(struct device *dev, struct device_node *np,
>> +				  const char *list_name, u8 flag)
>> +{
>> +	int num_clks;
>> +	int i;
>> +
>> +	num_clks = of_count_phandle_with_args(np, list_name, "#clock-cells");
>> +
>> +	for (i = 0; i < num_clks; i++) {
>> +		struct of_phandle_args clkspec;
>> +		struct clk_hw *hw;
>> +		struct sci_clk *sci_clk;
>> +		struct clk *clk;
>> +		int ret;
>> +
>> +		ret = of_parse_phandle_with_args(np, list_name, "#clock-cells",
>> +						 i, &clkspec);
>
> Do we really need to parse the phandle and get a clk from the
> provider that is our own driver? We should be able to get a hw
> pointer by calling our xlate_hw function with the two cells
> instead and completely bypass generating a clk structure.

Will investigate this, but you are probably right. Generating the clk 
structure can be bypassed at least with transition to provider->get_hw.

>
>> +		if (ret) {
>> +			dev_err(dev, "Failed to parse %s[%d] = %d\n", list_name,
>> +				i, ret);
>> +			return ret;
>> +		}
>> +		clk = of_clk_get_from_provider(&clkspec);
>> +		if (IS_ERR(clk)) {
>> +			dev_err(dev, "clk_get failed for %s[%d] = %ld\n",
>> +				list_name, i, PTR_ERR(clk));
>> +			return PTR_ERR(clk);
>> +		}
>> +		hw = __clk_get_hw(clk);
>> +		sci_clk = to_sci_clk(hw);
>> +
>> +		sci_clk->flags |= flag;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +/**
>> + * ti_sci_clk_probe - Probe function for the TI SCI clock driver
>> + * @pdev: platform device pointer to be probed
>> + *
>> + * Probes the TI SCI clock device. Allocates a new clock provider
>> + * and registers this to the common clock framework. Also applies
>> + * any required flags to the identified clocks via clock lists
>> + * supplied from DT. Returns 0 for success, negative error value
>> + * for failure.
>> + */
>> +static int ti_sci_clk_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct device_node *np = dev->of_node;
>> +	struct sci_clk_provider *provider;
>> +	const struct ti_sci_handle *handle;
>> +
>> +	if (!np) {
>> +		dev_err(dev, "OF data missing\n");
>> +		return -EINVAL;
>> +	}
>
> Is this ever true? Seems useless.

Probably not, the SoC this code is run on is always DT. Will drop this.

>
>> +
>> +	handle = devm_ti_sci_get_handle(dev);
>> +	if (IS_ERR(handle))
>> +		return PTR_ERR(handle);
>> +
>> +	provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
>> +	if (!provider)
>> +		return -ENOMEM;
>> +
>> +	INIT_LIST_HEAD(&provider->clocks);
>> +	mutex_init(&provider->lock);
>> +
>> +	provider->sci = handle;
>> +	provider->ops = &handle->ops.clk_ops;
>> +	provider->dev = dev;
>> +
>> +	of_clk_add_provider(np, sci_clk_get, provider);
>
> This could fail.

Yea, will add error handling.

>
>> +
>> +	ti_sci_clk_parse_flags(dev, np, "ti,ssc-clocks", SCI_CLK_SSC_ENABLE);
>> +	ti_sci_clk_parse_flags(dev, np, "ti,allow-freq-change-clocks",
>> +			       SCI_CLK_ALLOW_FREQ_CHANGE);
>> +	ti_sci_clk_parse_flags(dev, np, "ti,input-term-clocks",
>> +			       SCI_CLK_INPUT_TERMINATION);
>> +
>> +	dev_info(dev, "initialized.\n");
>
> debug noise?

True, will drop.

>
>> +
>> +	return 0;
>> +}
>> +

Re: [PATCH 3/3] clk: keystone: Add sci-clk driver support

[Stephen Boyd]

On 08/31, Tero Kristo wrote:
> On 24/08/16 11:34, Stephen Boyd wrote:
> >On 08/19, Nishanth Menon wrote:
> >>diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
> >>new file mode 100644
> >>index 000000000000..6c43e097e6d6
> >>--- /dev/null
> >>+++ b/drivers/clk/keystone/sci-clk.c
> >>@@ -0,0 +1,539 @@
> >>+	return (int)new_rate;
> >
> >determine rate should return a negative number on failure and 0
> >on success. The actual rate that was found should go into
> >req->rate. This looks broken.
> 
> Yea it seems broken, I wonder how we haven't seen any issues with
> this in testing.... Apparently positive return values from this are
> interpreted as success. Having a quick look at clk.c seems to
> confirm this.
> 
> Anyway, will fix.

True, perhaps we should fix that so we don't use a long to hold
the int return value either.

> >>+ *
> >>+ * Gets a handle to an existing TI SCI clock, or builds a new clock
> >>+ * entry and registers it with the common clock framework. Called from
> >>+ * the common clock framework, when a corresponding of_clk_get call is
> >>+ * executed, or recursively from itself when parsing parent clocks.
> >>+ * Returns a pointer to the clock struct, or ERR_PTR value in failure.
> >>+ */
> >
> >Please move this driver to clk_hw_register() and friends. This on
> >the fly clk generation is scary considering how we hold locks
> >while the provider is asked to give us the pointer, so allocating
> >and registering clks (basically reentering the CCF again) could
> >lead to a locking nightmare. Best to avoid that.
> 
> Ok, so just converting the driver to use provider->get_hw should be
> enough? This seems to be a relatively new API in the CCF. Will look
> at that.

Hopefully it will simplify things greatly.

> 
> >>+	}
> >>+
> >>+	snprintf(name, 20, "%s:%d:%d", dev_name(provider->dev), sci_clk->dev_id,
> >>+		 sci_clk->clk_id);
> >
> >I hope we don't make dev_name() longer than 20 characters
> 
> Shall I just increase the size of the buffer and add a length check?
> Using kmalloc or something here seems overkill, as the name gets
> copied by CCF anyway.

There's kasprintf() which would always make it long enough. I
don't know if it really matters though.

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Re: [PATCH 3/3] clk: keystone: Add sci-clk driver support

[Tero Kristo]

On 01/09/16 01:31, Stephen Boyd wrote:
> On 08/31, Tero Kristo wrote:
>> On 24/08/16 11:34, Stephen Boyd wrote:
>>> On 08/19, Nishanth Menon wrote:
>>>> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
>>>> new file mode 100644
>>>> index 000000000000..6c43e097e6d6
>>>> --- /dev/null
>>>> +++ b/drivers/clk/keystone/sci-clk.c
>>>> @@ -0,0 +1,539 @@
>>>> +	return (int)new_rate;
>>>
>>> determine rate should return a negative number on failure and 0
>>> on success. The actual rate that was found should go into
>>> req->rate. This looks broken.
>>
>> Yea it seems broken, I wonder how we haven't seen any issues with
>> this in testing.... Apparently positive return values from this are
>> interpreted as success. Having a quick look at clk.c seems to
>> confirm this.
>>
>> Anyway, will fix.
>
> True, perhaps we should fix that so we don't use a long to hold
> the int return value either.
>
>>>> + *
>>>> + * Gets a handle to an existing TI SCI clock, or builds a new clock
>>>> + * entry and registers it with the common clock framework. Called from
>>>> + * the common clock framework, when a corresponding of_clk_get call is
>>>> + * executed, or recursively from itself when parsing parent clocks.
>>>> + * Returns a pointer to the clock struct, or ERR_PTR value in failure.
>>>> + */
>>>
>>> Please move this driver to clk_hw_register() and friends. This on
>>> the fly clk generation is scary considering how we hold locks
>>> while the provider is asked to give us the pointer, so allocating
>>> and registering clks (basically reentering the CCF again) could
>>> lead to a locking nightmare. Best to avoid that.
>>
>> Ok, so just converting the driver to use provider->get_hw should be
>> enough? This seems to be a relatively new API in the CCF. Will look
>> at that.
>
> Hopefully it will simplify things greatly.

Well, it didn't simplify things greatly, but somewhat. I still need to 
use of_parse_phandle_with_args with one of the helpers for example. Will 
send out v2 in a bit.

>
>>
>>>> +	}
>>>> +
>>>> +	snprintf(name, 20, "%s:%d:%d", dev_name(provider->dev), sci_clk->dev_id,
>>>> +		 sci_clk->clk_id);
>>>
>>> I hope we don't make dev_name() longer than 20 characters
>>
>> Shall I just increase the size of the buffer and add a length check?
>> Using kmalloc or something here seems overkill, as the name gets
>> copied by CCF anyway.
>
> There's kasprintf() which would always make it long enough. I
> don't know if it really matters though.

Ok, I will use this one.

-Tero