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From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 1/5] clk: sunxi-ng: mux: Add support for mux tables
Date: Tue, 23 Aug 2016 10:53:05 +0200	[thread overview]
Message-ID: <20160823085305.GB2598@lukather> (raw)
In-Reply-To: <1471248795-17951-2-git-send-email-wens@csie.org>

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On Mon, Aug 15, 2016 at 04:13:11PM +0800, Chen-Yu Tsai wrote:
> Some clock muxes have holes, i.e. invalid or unconnected inputs,
> between parent mux values.
> 
> Add support for specifying a mux table to map clock parents to
> mux values.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> Changes since v1: none
> ---
>  drivers/clk/sunxi-ng/ccu_mux.c | 12 ++++++++++++
>  drivers/clk/sunxi-ng/ccu_mux.h | 12 ++++++++++--
>  2 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
> index 1329b9ab481e..68b32f168a74 100644
> --- a/drivers/clk/sunxi-ng/ccu_mux.c
> +++ b/drivers/clk/sunxi-ng/ccu_mux.c
> @@ -107,6 +107,15 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common,
>  	parent = reg >> cm->shift;
>  	parent &= (1 << cm->width) - 1;
>  
> +	if (cm->table) {
> +		int num_parents = clk_hw_get_num_parents(&common->hw);
> +		int i;
> +
> +		for (i = 0; i < num_parents; i++)
> +			if (cm->table[i] == parent)
> +				return i;
> +	}
> +
>  	return parent;
>  }
>  
> @@ -117,6 +126,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
>  	unsigned long flags;
>  	u32 reg;
>  
> +	if (cm->table)
> +		index = cm->table[index];
> +
>  	spin_lock_irqsave(common->lock, flags);
>  
>  	reg = readl(common->base + common->reg);
> diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
> index d35ce5e93840..f0078de78712 100644
> --- a/drivers/clk/sunxi-ng/ccu_mux.h
> +++ b/drivers/clk/sunxi-ng/ccu_mux.h
> @@ -6,8 +6,9 @@
>  #include "ccu_common.h"
>  
>  struct ccu_mux_internal {
> -	u8	shift;
> -	u8	width;
> +	u8		shift;
> +	u8		width;
> +	const u8	*table;
>  
>  	struct {
>  		u8	index;
> @@ -21,6 +22,13 @@ struct ccu_mux_internal {
>  	} variable_prediv;
>  };
>  
> +#define SUNXI_CLK_MUX_TABLE(_shift, _width, _table)	\
> +	{						\
> +		.shift	= _shift,			\
> +		.width	= _width,			\
> +		.table	= _table,			\
> +	}
> +
>  #define SUNXI_CLK_MUX(_shift, _width)	\
>  	{					\
>  		.shift	= _shift,		\

I'd prefer if you also converted the SUNXI_CLK_MUX to use the MUX
table version.

I've just merged the renaming patch for those macros to be consistent
with the other internal structures macro, so that name will have to be
adjusted..

Thanks,
Maxime

> -- 
> 2.8.1
> 

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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  reply	other threads:[~2016-08-23  8:53 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-15  8:13 [PATCH v2 0/5] clk: sunxi-ng: Support A31/A31s CCU Chen-Yu Tsai
2016-08-15  8:13 ` [PATCH v2 1/5] clk: sunxi-ng: mux: Add support for mux tables Chen-Yu Tsai
2016-08-23  8:53   ` Maxime Ripard [this message]
2016-08-23  9:57     ` Chen-Yu Tsai
2016-08-15  8:13 ` [PATCH v2 2/5] clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents Chen-Yu Tsai
2016-08-23  8:55   ` Maxime Ripard
2016-08-23  9:52     ` Chen-Yu Tsai
2016-08-23  9:57       ` Maxime Ripard
2016-08-15  8:13 ` [PATCH v2 3/5] clk: sunxi-ng: mux: Add clk notifier functions Chen-Yu Tsai
2016-08-15  8:13 ` [PATCH v2 4/5] clk: sunxi-ng: Add A31/A31s clocks Chen-Yu Tsai
     [not found]   ` <1471248795-17951-5-git-send-email-wens-jdAy2FN1RRM@public.gmane.org>
2016-08-15 18:07     ` Jean-Francois Moine
2016-08-15  8:13 ` [PATCH v2 5/5] ARM: dts: sun6i: switch A31/A31s to new CCU clock bindings Chen-Yu Tsai

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