* [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33
@ 2016-08-23 5:58 Icenowy Zheng
2016-08-23 5:58 ` [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33 Icenowy Zheng
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Icenowy Zheng @ 2016-08-23 5:58 UTC (permalink / raw)
To: Russell King, Maxime Ripard, Chen-Yu Tsai, Linus Walleij,
Hans de Goede
Cc: Mark Rutland, devicetree, linux-kernel, linux-gpio, Rob Herring,
Icenowy Zheng, linux-arm-kernel
PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33
datasheets. However, the function is wrongly named "uart2" in the pinctrl
driver. This patch fixes this by modifying them to be named "uart1".
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c | 4 ++--
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
index ce483b0..f9d661e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
@@ -485,12 +485,12 @@ static const struct sunxi_desc_pin sun8i_a23_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
index 3040abe..3131cac 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -407,12 +407,12 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
--
2.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33
2016-08-23 5:58 [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Icenowy Zheng
@ 2016-08-23 5:58 ` Icenowy Zheng
2016-08-23 11:42 ` Maxime Ripard
2016-08-23 6:47 ` [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Maxime Ripard
2016-08-23 10:29 ` Linus Walleij
2 siblings, 1 reply; 10+ messages in thread
From: Icenowy Zheng @ 2016-08-23 5:58 UTC (permalink / raw)
To: Russell King, Maxime Ripard, Chen-Yu Tsai, Linus Walleij,
Hans de Goede
Cc: Mark Rutland, devicetree, linux-kernel, linux-gpio, Rob Herring,
Icenowy Zheng, linux-arm-kernel
A23/33 have 4 UART controllers outside PRCM. However, the devicetree used
to mentioned only UART0's pinmux settings. Some extra UART controllers have
RTS/CTS, and is suitable for using as bluetooth UART controller.
Add the pinmux settings for the UART controller, to make use of the
bluetooth function of some tablets.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 56 ++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/sun8i-a23.dtsi | 7 +++++
2 files changed, 63 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7e05e09..89ea479 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -361,6 +361,62 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ uart1_pins_a: uart1@0 {
+ allwinner,pins = "PD10", "PD11";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins_cts_rts_a: uart1-cts-rts@1 {
+ allwinner,pins = "PD12", "PD13";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins_b: uart1@1 {
+ allwinner,pins = "PG6", "PG7";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins_cts_rts_b: uart1-cts-rts@0 {
+ allwinner,pins = "PG8", "PG9";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_pins_a: uart2@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_pins_cts_rts_a: uart2-cts-rts@1 {
+ allwinner,pins = "PB2", "PB3";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_a: uart3@0 {
+ allwinner,pins = "PH6", "PH7";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_cts_rts_a: uart3-cts-rts@1 {
+ allwinner,pins = "PH8", "PH9";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 92e6616..6b76580 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -123,4 +123,11 @@
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+ uart3_pins_b: uart3@0 {
+ allwinner,pins = "PD8", "PD9";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
--
2.9.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33
2016-08-23 5:58 ` [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33 Icenowy Zheng
@ 2016-08-23 11:42 ` Maxime Ripard
2016-08-23 13:51 ` Icenowy Zheng
0 siblings, 1 reply; 10+ messages in thread
From: Maxime Ripard @ 2016-08-23 11:42 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Mark Rutland, devicetree, linux-gpio, Linus Walleij, Russell King,
linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring,
linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 755 bytes --]
Hi,
On Tue, Aug 23, 2016 at 01:58:26PM +0800, Icenowy Zheng wrote:
> A23/33 have 4 UART controllers outside PRCM. However, the devicetree used
> to mentioned only UART0's pinmux settings. Some extra UART controllers have
> RTS/CTS, and is suitable for using as bluetooth UART controller.
>
> Add the pinmux settings for the UART controller, to make use of the
> bluetooth function of some tablets.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Our policy is that we avoid adding unused pinctrl nodes to not cripple
the DT for no particular reason.
So please add only the nodes you'll need in your tablet.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33
2016-08-23 11:42 ` Maxime Ripard
@ 2016-08-23 13:51 ` Icenowy Zheng
2016-08-26 20:18 ` Maxime Ripard
0 siblings, 1 reply; 10+ messages in thread
From: Icenowy Zheng @ 2016-08-23 13:51 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Linus Walleij, Russell King,
linux-kernel@vger.kernel.org, Hans de Goede, Chen-Yu Tsai,
Rob Herring, linux-arm-kernel@lists.infradead.org
23.08.2016, 19:42, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> Hi,
>
> On Tue, Aug 23, 2016 at 01:58:26PM +0800, Icenowy Zheng wrote:
>> A23/33 have 4 UART controllers outside PRCM. However, the devicetree used
>> to mentioned only UART0's pinmux settings. Some extra UART controllers have
>> RTS/CTS, and is suitable for using as bluetooth UART controller.
>>
>> Add the pinmux settings for the UART controller, to make use of the
>> bluetooth function of some tablets.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> Our policy is that we avoid adding unused pinctrl nodes to not cripple
> the DT for no particular reason.
>
> So please add only the nodes you'll need in your tablet.
Then... if what I needs is the PG group of uart1, should I name it as
uart1_pins_a or uart1_pins_b?
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33
2016-08-23 13:51 ` Icenowy Zheng
@ 2016-08-26 20:18 ` Maxime Ripard
0 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2016-08-26 20:18 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Russell King, Chen-Yu Tsai, Linus Walleij, Hans de Goede,
Rob Herring, Mark Rutland, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org
[-- Attachment #1: Type: text/plain, Size: 1127 bytes --]
Hi,
On Tue, Aug 23, 2016 at 09:51:05PM +0800, Icenowy Zheng wrote:
>
>
> 23.08.2016, 19:42, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > Hi,
> >
> > On Tue, Aug 23, 2016 at 01:58:26PM +0800, Icenowy Zheng wrote:
> >> A23/33 have 4 UART controllers outside PRCM. However, the devicetree used
> >> to mentioned only UART0's pinmux settings. Some extra UART controllers have
> >> RTS/CTS, and is suitable for using as bluetooth UART controller.
> >>
> >> Add the pinmux settings for the UART controller, to make use of the
> >> bluetooth function of some tablets.
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >
> > Our policy is that we avoid adding unused pinctrl nodes to not cripple
> > the DT for no particular reason.
> >
> > So please add only the nodes you'll need in your tablet.
>
> Then... if what I needs is the PG group of uart1, should I name it as
> uart1_pins_a or uart1_pins_b?
We don't have any rules here, whichever comes first wins.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33
2016-08-23 5:58 [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Icenowy Zheng
2016-08-23 5:58 ` [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33 Icenowy Zheng
@ 2016-08-23 6:47 ` Maxime Ripard
2016-08-23 6:50 ` Icenowy Zheng
2016-08-23 9:27 ` Linus Walleij
2016-08-23 10:29 ` Linus Walleij
2 siblings, 2 replies; 10+ messages in thread
From: Maxime Ripard @ 2016-08-23 6:47 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Mark Rutland, devicetree, linux-gpio, Linus Walleij, Russell King,
linux-kernel, Hans de Goede, Chen-Yu Tsai, Rob Herring,
linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 528 bytes --]
Hi,
On Tue, Aug 23, 2016 at 01:58:25PM +0800, Icenowy Zheng wrote:
> PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33
> datasheets. However, the function is wrongly named "uart2" in the pinctrl
> driver. This patch fixes this by modifying them to be named "uart1".
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
This looks good, but could you send it to stable?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #1.2: signature.asc --]
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33
2016-08-23 6:47 ` [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Maxime Ripard
@ 2016-08-23 6:50 ` Icenowy Zheng
2016-08-23 9:27 ` Linus Walleij
1 sibling, 0 replies; 10+ messages in thread
From: Icenowy Zheng @ 2016-08-23 6:50 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Linus Walleij, Russell King,
linux-kernel@vger.kernel.org, Hans de Goede, Chen-Yu Tsai,
Rob Herring, linux-arm-kernel@lists.infradead.org
23.08.2016, 14:47, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> Hi,
>
> On Tue, Aug 23, 2016 at 01:58:25PM +0800, Icenowy Zheng wrote:
>> PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33
>> datasheets. However, the function is wrongly named "uart2" in the pinctrl
>> driver. This patch fixes this by modifying them to be named "uart1".
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> This looks good, but could you send it to stable?
Yes... But currently in mainline kernel, no dt file for A23/33 uses UART1.
(Lots of the tablets is so low-end that they do not ship with BT support, and
then no support for extra UART is needed)
I found the problem when running mainline kernel on my iNet D978 Rev2 board
tablet. It come with a RTL8723BS.
>
> Thanks,
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33
2016-08-23 6:47 ` [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Maxime Ripard
2016-08-23 6:50 ` Icenowy Zheng
@ 2016-08-23 9:27 ` Linus Walleij
2016-08-23 9:54 ` Maxime Ripard
1 sibling, 1 reply; 10+ messages in thread
From: Linus Walleij @ 2016-08-23 9:27 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Russell King,
linux-kernel@vger.kernel.org, Hans de Goede, Chen-Yu Tsai,
Rob Herring, Icenowy Zheng, linux-arm-kernel@lists.infradead.org
On Tue, Aug 23, 2016 at 8:47 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Tue, Aug 23, 2016 at 01:58:25PM +0800, Icenowy Zheng wrote:
>> PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33
>> datasheets. However, the function is wrongly named "uart2" in the pinctrl
>> driver. This patch fixes this by modifying them to be named "uart1".
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>
> This looks good, but could you send it to stable?
If that is an ACK I can tag it for stable when applying.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33
2016-08-23 9:27 ` Linus Walleij
@ 2016-08-23 9:54 ` Maxime Ripard
0 siblings, 0 replies; 10+ messages in thread
From: Maxime Ripard @ 2016-08-23 9:54 UTC (permalink / raw)
To: Linus Walleij
Cc: Mark Rutland, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Russell King,
linux-kernel@vger.kernel.org, Hans de Goede, Chen-Yu Tsai,
Rob Herring, Icenowy Zheng, linux-arm-kernel@lists.infradead.org
[-- Attachment #1.1: Type: text/plain, Size: 787 bytes --]
On Tue, Aug 23, 2016 at 11:27:10AM +0200, Linus Walleij wrote:
> On Tue, Aug 23, 2016 at 8:47 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Tue, Aug 23, 2016 at 01:58:25PM +0800, Icenowy Zheng wrote:
> >> PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33
> >> datasheets. However, the function is wrongly named "uart2" in the pinctrl
> >> driver. This patch fixes this by modifying them to be named "uart1".
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >
> > This looks good, but could you send it to stable?
>
> If that is an ACK I can tag it for stable when applying.
Yes, it's an ACK. Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33
2016-08-23 5:58 [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Icenowy Zheng
2016-08-23 5:58 ` [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33 Icenowy Zheng
2016-08-23 6:47 ` [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Maxime Ripard
@ 2016-08-23 10:29 ` Linus Walleij
2 siblings, 0 replies; 10+ messages in thread
From: Linus Walleij @ 2016-08-23 10:29 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Mark Rutland, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org, Russell King,
linux-kernel@vger.kernel.org, Hans de Goede, Chen-Yu Tsai,
Rob Herring, Maxime Ripard, linux-arm-kernel@lists.infradead.org
On Tue, Aug 23, 2016 at 7:58 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote:
> PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33
> datasheets. However, the function is wrongly named "uart2" in the pinctrl
> driver. This patch fixes this by modifying them to be named "uart1".
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Applied for stable with Maxime's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2016-08-26 20:18 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-08-23 5:58 [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Icenowy Zheng
2016-08-23 5:58 ` [PATCH 2/2] ARM: dts: sun8i: Add extra UART pinmux settings for A23/33 Icenowy Zheng
2016-08-23 11:42 ` Maxime Ripard
2016-08-23 13:51 ` Icenowy Zheng
2016-08-26 20:18 ` Maxime Ripard
2016-08-23 6:47 ` [PATCH 1/2] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 Maxime Ripard
2016-08-23 6:50 ` Icenowy Zheng
2016-08-23 9:27 ` Linus Walleij
2016-08-23 9:54 ` Maxime Ripard
2016-08-23 10:29 ` Linus Walleij
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