* [PATCH v2 00/26] MIPS generic kernels, SEAD-3 & Boston support
@ 2016-08-30 17:29 Paul Burton
2016-08-30 17:29 ` [PATCH v2 11/26] dt-bindings: Document mti,mips-cpc binding Paul Burton
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Paul Burton @ 2016-08-30 17:29 UTC (permalink / raw)
To: linux-mips, Ralf Baechle
Cc: Paul Burton, Paolo Bonzini, Guenter Roeck, John Crispin,
Maciej W. Rozycki, Bjorn Helgaas, Jacek Anaszewski, Jason Cooper,
Robin Murphy, Hans-Christian Noren Egtvedt, James Hogan,
John Crispin, Sergey Ryazanov, Michael Turquette, Qais Yousef,
Valentin Rothberg, Huacai Chen, Kefeng Wang, Thomas Gleixner
This series introduces some infrastructure for building generic kernels
which will run on multiple boards depending upon the device tree
provided to them by the bootloader. It converts SEAD-3 to make use of
this, and adds support for the MIPS Boston development platform.
The Boston support can be tested in QEMU with this patchset applied:
https://lists.gnu.org/archive/html/qemu-devel/2016-08/msg03419.html
To do so, configure the kernel for the generic 64r6el_defconfig & run
QEMU like so:
$ make ARCH=mips 64r6el_defconfig
$ make ARCH=mips CROSS_COMPILE=my-toolchain-
$ qemu-system-mips64el -M boston \
-kernel arch/mips/boot/vmlinux.gz.itb \
serial stdio
The same kernel binary will also boot on a SEAD-3 if using a bootloader
capable of loading the FIT image format (ie. U-Boot). These 2 boards
form the starting point for the generic kernels, with Ci20 & Ci40 able
to be added easily. Malta will require further work, but I've got most
peripherals converted to probe using device tree as a starting point &
will submit that separately.
This series applies atop v4.8-rc3 with my "MIPS: SEAD3 device tree
conversion" series applied first.
Paul Burton (26):
MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC
MIPS: PCI: Make pcibios_set_cache_line_size an initcall
MIPS: PCI: Inline pcibios_assign_all_busses
MIPS: PCI: Split pci.c into pci.c & pci-legacy.c
MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY
MIPS: PCI: Support generic drivers
MIPS: Sanitise coherentio semantics
MIPS: dma-default: Don't check hw_coherentio if device is non-coherent
MIPS: Support per-device DMA coherence
MIPS: Print CM error reports upon bus errors
dt-bindings: Document mti,mips-cpc binding
MIPS: CPC: Provide a default mips_cpc_default_phys_base
dt-bindings: Document mti,mips-cdmm binding
MIPS: CDMM: Allow CDMM base address to be specified via DT
irqchip: mips-cpu: Replace magic 0x100 with IE_SW0
irqchip: mips-cpu: Prepare for non-legacy IRQ domains
irqchip: mips-cpu: Introduce IPI IRQ domain support
MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support
MIPS: Stengthen IPI IRQ domain sanity check
MIPS: Adjust MIPS64 CAC_BASE to reflect Config.K0
MIPS: Support generating Flattened Image Trees (.itb)
MIPS: generic: Introduce generic DT-based board support
MIPS: generic: Convert SEAD-3 to a generic board
dt-bindings: Document img,boston-clock binding
clk: boston: Add a driver for MIPS Boston board clocks
MIPS: generic: Support MIPS Boston development boards
.../devicetree/bindings/clock/img,boston-clock.txt | 27 ++
.../devicetree/bindings/misc/mti,mips-cdmm.txt | 8 +
.../devicetree/bindings/misc/mti,mips-cpc.txt | 8 +
arch/mips/Kbuild.platforms | 2 +-
arch/mips/Kconfig | 105 ++++---
arch/mips/Makefile | 77 +++++-
arch/mips/alchemy/common/setup.c | 6 +-
arch/mips/boot/Makefile | 66 +++++
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/img/Makefile | 7 +
arch/mips/boot/dts/img/boston.dts | 230 ++++++++++++++++
arch/mips/boot/dts/mti/Makefile | 2 +-
arch/mips/boot/dts/mti/sead3.dts | 1 +
arch/mips/configs/generic/32r1.config | 2 +
arch/mips/configs/generic/32r2.config | 3 +
arch/mips/configs/generic/32r6.config | 2 +
arch/mips/configs/generic/64r1.config | 4 +
arch/mips/configs/generic/64r2.config | 5 +
arch/mips/configs/generic/64r6.config | 4 +
arch/mips/configs/generic/board-boston.config | 46 ++++
arch/mips/configs/generic/board-sead-3.config | 32 +++
arch/mips/configs/generic/eb.config | 1 +
arch/mips/configs/generic/el.config | 1 +
arch/mips/configs/generic/micro32r2.config | 4 +
arch/mips/configs/generic_defconfig | 96 +++++++
arch/mips/configs/sead3_defconfig | 129 ---------
arch/mips/configs/sead3micro_defconfig | 122 ---------
arch/mips/generic/Kconfig | 27 ++
arch/mips/generic/Makefile | 15 +
arch/mips/generic/Platform | 14 +
.../sead3-dtshim.c => generic/board-sead3.c} | 106 +++++++-
arch/mips/generic/init.c | 172 ++++++++++++
arch/mips/generic/irq.c | 64 +++++
arch/mips/generic/proc.c | 29 ++
arch/mips/generic/vmlinux.its.S | 56 ++++
arch/mips/include/asm/addrspace.h | 3 +-
arch/mips/include/asm/device.h | 5 +
arch/mips/include/asm/dma-coherence.h | 16 +-
arch/mips/include/asm/dma-mapping.h | 10 +
arch/mips/include/asm/mach-generic/dma-coherence.h | 14 +-
arch/mips/include/asm/mach-generic/spaces.h | 8 +-
arch/mips/include/asm/mach-ip27/spaces.h | 1 +
.../include/asm/mach-sead3/cpu-feature-overrides.h | 72 -----
arch/mips/include/asm/mach-sead3/irq.h | 9 -
.../include/asm/mach-sead3/kernel-entry-init.h | 21 --
arch/mips/include/asm/mach-sead3/sead3-dtshim.h | 29 --
arch/mips/include/asm/mach-sead3/war.h | 24 --
arch/mips/include/asm/machine.h | 63 +++++
arch/mips/include/asm/pci.h | 57 +++-
arch/mips/kernel/mips-cpc.c | 18 ++
arch/mips/kernel/smp-mt.c | 49 +---
arch/mips/kernel/smp.c | 20 +-
arch/mips/kernel/traps.c | 3 +
arch/mips/lantiq/irq.c | 52 ----
arch/mips/lib/iomap-pci.c | 4 +
arch/mips/mm/c-r4k.c | 7 +-
arch/mips/mm/dma-default.c | 16 +-
arch/mips/mti-malta/malta-int.c | 90 +-----
arch/mips/mti-malta/malta-setup.c | 10 +-
arch/mips/mti-sead3/Makefile | 15 -
arch/mips/mti-sead3/Platform | 7 -
arch/mips/mti-sead3/sead3-init.c | 100 -------
arch/mips/mti-sead3/sead3-int.c | 23 --
arch/mips/mti-sead3/sead3-setup.c | 39 ---
arch/mips/mti-sead3/sead3-time.c | 91 -------
arch/mips/pci/Makefile | 2 +
arch/mips/pci/pci-alchemy.c | 3 +-
arch/mips/pci/pci-generic.c | 52 ++++
arch/mips/pci/pci-legacy.c | 302 +++++++++++++++++++++
arch/mips/pci/pci.c | 296 +-------------------
drivers/bus/mips_cdmm.c | 13 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/imgtec/Kconfig | 10 +
drivers/clk/imgtec/Makefile | 1 +
drivers/clk/imgtec/clk-boston.c | 101 +++++++
drivers/irqchip/Kconfig | 2 +
drivers/irqchip/irq-mips-cpu.c | 149 ++++++++--
include/dt-bindings/clock/boston-clock.h | 14 +
79 files changed, 2018 insertions(+), 1279 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/img,boston-clock.txt
create mode 100644 Documentation/devicetree/bindings/misc/mti,mips-cdmm.txt
create mode 100644 Documentation/devicetree/bindings/misc/mti,mips-cpc.txt
create mode 100644 arch/mips/boot/dts/img/Makefile
create mode 100644 arch/mips/boot/dts/img/boston.dts
create mode 100644 arch/mips/configs/generic/32r1.config
create mode 100644 arch/mips/configs/generic/32r2.config
create mode 100644 arch/mips/configs/generic/32r6.config
create mode 100644 arch/mips/configs/generic/64r1.config
create mode 100644 arch/mips/configs/generic/64r2.config
create mode 100644 arch/mips/configs/generic/64r6.config
create mode 100644 arch/mips/configs/generic/board-boston.config
create mode 100644 arch/mips/configs/generic/board-sead-3.config
create mode 100644 arch/mips/configs/generic/eb.config
create mode 100644 arch/mips/configs/generic/el.config
create mode 100644 arch/mips/configs/generic/micro32r2.config
create mode 100644 arch/mips/configs/generic_defconfig
delete mode 100644 arch/mips/configs/sead3_defconfig
delete mode 100644 arch/mips/configs/sead3micro_defconfig
create mode 100644 arch/mips/generic/Kconfig
create mode 100644 arch/mips/generic/Makefile
create mode 100644 arch/mips/generic/Platform
rename arch/mips/{mti-sead3/sead3-dtshim.c => generic/board-sead3.c} (72%)
create mode 100644 arch/mips/generic/init.c
create mode 100644 arch/mips/generic/irq.c
create mode 100644 arch/mips/generic/proc.c
create mode 100644 arch/mips/generic/vmlinux.its.S
delete mode 100644 arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
delete mode 100644 arch/mips/include/asm/mach-sead3/irq.h
delete mode 100644 arch/mips/include/asm/mach-sead3/kernel-entry-init.h
delete mode 100644 arch/mips/include/asm/mach-sead3/sead3-dtshim.h
delete mode 100644 arch/mips/include/asm/mach-sead3/war.h
create mode 100644 arch/mips/include/asm/machine.h
delete mode 100644 arch/mips/mti-sead3/Makefile
delete mode 100644 arch/mips/mti-sead3/Platform
delete mode 100644 arch/mips/mti-sead3/sead3-init.c
delete mode 100644 arch/mips/mti-sead3/sead3-int.c
delete mode 100644 arch/mips/mti-sead3/sead3-setup.c
delete mode 100644 arch/mips/mti-sead3/sead3-time.c
create mode 100644 arch/mips/pci/pci-generic.c
create mode 100644 arch/mips/pci/pci-legacy.c
create mode 100644 drivers/clk/imgtec/Kconfig
create mode 100644 drivers/clk/imgtec/Makefile
create mode 100644 drivers/clk/imgtec/clk-boston.c
create mode 100644 include/dt-bindings/clock/boston-clock.h
--
2.9.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 11/26] dt-bindings: Document mti,mips-cpc binding
2016-08-30 17:29 [PATCH v2 00/26] MIPS generic kernels, SEAD-3 & Boston support Paul Burton
@ 2016-08-30 17:29 ` Paul Burton
2016-08-30 17:29 ` [PATCH v2 13/26] dt-bindings: Document mti,mips-cdmm binding Paul Burton
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Paul Burton @ 2016-08-30 17:29 UTC (permalink / raw)
To: linux-mips, Ralf Baechle
Cc: Paul Burton, devicetree, Mark Rutland, Rob Herring, linux-kernel
Document a binding for the MIPS Cluster Power Controller (CPC) which
simply allows the device tree to specify where the CPC registers should
be mapped.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---
Changes in v2: None
Documentation/devicetree/bindings/misc/mti,mips-cpc.txt | 8 ++++++++
1 file changed, 8 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/mti,mips-cpc.txt
diff --git a/Documentation/devicetree/bindings/misc/mti,mips-cpc.txt b/Documentation/devicetree/bindings/misc/mti,mips-cpc.txt
new file mode 100644
index 0000000..92eb08f
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/mti,mips-cpc.txt
@@ -0,0 +1,8 @@
+Binding for MIPS Cluster Power Controller (CPC).
+
+This binding allows a system to specify where the CPC registers should be
+mapped using device tree.
+
+Required properties:
+compatible : Should be "mti,mips-cpc".
+regs: Should describe the address & size of the CPC register region.
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 13/26] dt-bindings: Document mti,mips-cdmm binding
2016-08-30 17:29 [PATCH v2 00/26] MIPS generic kernels, SEAD-3 & Boston support Paul Burton
2016-08-30 17:29 ` [PATCH v2 11/26] dt-bindings: Document mti,mips-cpc binding Paul Burton
@ 2016-08-30 17:29 ` Paul Burton
2016-08-30 17:29 ` [PATCH v2 23/26] MIPS: generic: Convert SEAD-3 to a generic board Paul Burton
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Paul Burton @ 2016-08-30 17:29 UTC (permalink / raw)
To: linux-mips, Ralf Baechle
Cc: Paul Burton, devicetree, Mark Rutland, Rob Herring, linux-kernel
Document a binding for the MIPS Common Device Memory Map (CDMM) which
simply allows the device tree to specify where the CDMM registers should
be mapped.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---
Changes in v2: None
Documentation/devicetree/bindings/misc/mti,mips-cdmm.txt | 8 ++++++++
1 file changed, 8 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/mti,mips-cdmm.txt
diff --git a/Documentation/devicetree/bindings/misc/mti,mips-cdmm.txt b/Documentation/devicetree/bindings/misc/mti,mips-cdmm.txt
new file mode 100644
index 0000000..5b0fc40
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/mti,mips-cdmm.txt
@@ -0,0 +1,8 @@
+Binding for MIPS Common Device Memory Map (CDMM) bus.
+
+This binding allows a system to specify where the CDMM registers should be
+mapped using device tree.
+
+Required properties:
+compatible : Should be "mti,mips-cdmm".
+regs: Should describe the address & size of the CDMM register region.
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 23/26] MIPS: generic: Convert SEAD-3 to a generic board
2016-08-30 17:29 [PATCH v2 00/26] MIPS generic kernels, SEAD-3 & Boston support Paul Burton
2016-08-30 17:29 ` [PATCH v2 11/26] dt-bindings: Document mti,mips-cpc binding Paul Burton
2016-08-30 17:29 ` [PATCH v2 13/26] dt-bindings: Document mti,mips-cdmm binding Paul Burton
@ 2016-08-30 17:29 ` Paul Burton
2016-08-30 17:29 ` [PATCH v2 24/26] dt-bindings: Document img,boston-clock binding Paul Burton
[not found] ` <20160830172929.16948-1-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
4 siblings, 0 replies; 6+ messages in thread
From: Paul Burton @ 2016-08-30 17:29 UTC (permalink / raw)
To: linux-mips, Ralf Baechle
Cc: Paul Burton, Matt Redfearn, Kefeng Wang, Jacek Anaszewski,
linux-kernel, devicetree, Rob Herring, Mark Rutland
Convert the MIPS SEAD-3 board support to be a generic board, supported
by generic kernels.
Because the SEAD-3 boot protocol was defined long ago and we don't want
to force a switch to the UHI protocol, SEAD-3 is added as a legacy board
which is detected by reading the REVISION register. This may technically
not be a valid memory read & future work will include attempting to
handle that gracefully. In practice since SEAD-3 is the only legacy
board supported by the generic kernel so far the read will only happen
on SEAD-3 boards, and even once Malta is converted the same REVISION
register exists there too. Other boards such as Boston, Ci20 & Ci40 will
use the UHI boot protocol & thus not run any of the legacy board detect
functions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---
Changes in v2: None
arch/mips/Kbuild.platforms | 1 -
arch/mips/Kconfig | 37 +-----
arch/mips/Makefile | 13 +++
arch/mips/boot/dts/mti/Makefile | 2 +-
arch/mips/boot/dts/mti/sead3.dts | 1 +
arch/mips/configs/generic/board-sead-3.config | 32 +++++
arch/mips/configs/sead3_defconfig | 129 ---------------------
arch/mips/configs/sead3micro_defconfig | 122 -------------------
arch/mips/generic/Kconfig | 7 ++
arch/mips/generic/Makefile | 2 +
.../sead3-dtshim.c => generic/board-sead3.c} | 106 +++++++++++++++--
.../include/asm/mach-sead3/cpu-feature-overrides.h | 72 ------------
arch/mips/include/asm/mach-sead3/irq.h | 9 --
.../include/asm/mach-sead3/kernel-entry-init.h | 21 ----
arch/mips/include/asm/mach-sead3/sead3-dtshim.h | 29 -----
arch/mips/include/asm/mach-sead3/war.h | 24 ----
arch/mips/mti-sead3/Makefile | 15 ---
arch/mips/mti-sead3/Platform | 7 --
arch/mips/mti-sead3/sead3-init.c | 100 ----------------
arch/mips/mti-sead3/sead3-int.c | 23 ----
arch/mips/mti-sead3/sead3-setup.c | 39 -------
arch/mips/mti-sead3/sead3-time.c | 91 ---------------
22 files changed, 152 insertions(+), 730 deletions(-)
create mode 100644 arch/mips/configs/generic/board-sead-3.config
delete mode 100644 arch/mips/configs/sead3_defconfig
delete mode 100644 arch/mips/configs/sead3micro_defconfig
rename arch/mips/{mti-sead3/sead3-dtshim.c => generic/board-sead3.c} (72%)
delete mode 100644 arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
delete mode 100644 arch/mips/include/asm/mach-sead3/irq.h
delete mode 100644 arch/mips/include/asm/mach-sead3/kernel-entry-init.h
delete mode 100644 arch/mips/include/asm/mach-sead3/sead3-dtshim.h
delete mode 100644 arch/mips/include/asm/mach-sead3/war.h
delete mode 100644 arch/mips/mti-sead3/Makefile
delete mode 100644 arch/mips/mti-sead3/Platform
delete mode 100644 arch/mips/mti-sead3/sead3-init.c
delete mode 100644 arch/mips/mti-sead3/sead3-int.c
delete mode 100644 arch/mips/mti-sead3/sead3-setup.c
delete mode 100644 arch/mips/mti-sead3/sead3-time.c
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 9c1e8f9..f5f1bdb 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -19,7 +19,6 @@ platforms += lasat
platforms += loongson32
platforms += loongson64
platforms += mti-malta
-platforms += mti-sead3
platforms += netlogic
platforms += paravirt
platforms += pic32
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 92a3e37..7cf522f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -544,41 +544,6 @@ config MACH_PIC32
Microchip PIC32 is a family of general-purpose 32 bit MIPS core
microcontrollers.
-config MIPS_SEAD3
- bool "MIPS SEAD3 board"
- select BOOT_ELF32
- select BOOT_RAW
- select BUILTIN_DTB
- select CEVT_R4K
- select CSRC_R4K
- select CLKSRC_MIPS_GIC
- select COMMON_CLK
- select CPU_MIPSR2_IRQ_VI
- select CPU_MIPSR2_IRQ_EI
- select DMA_NONCOHERENT
- select IRQ_MIPS_CPU
- select MIPS_GIC
- select LIBFDT
- select MIPS_MSC
- select SYS_HAS_CPU_MIPS32_R1
- select SYS_HAS_CPU_MIPS32_R2
- select SYS_HAS_CPU_MIPS32_R6
- select SYS_HAS_CPU_MIPS64_R1
- select SYS_SUPPORTS_32BIT_KERNEL
- select SYS_SUPPORTS_64BIT_KERNEL
- select SYS_SUPPORTS_BIG_ENDIAN
- select SYS_SUPPORTS_LITTLE_ENDIAN
- select SYS_SUPPORTS_SMARTMIPS
- select SYS_SUPPORTS_MICROMIPS
- select SYS_SUPPORTS_MIPS16
- select SYS_SUPPORTS_RELOCATABLE
- select USB_EHCI_BIG_ENDIAN_DESC
- select USB_EHCI_BIG_ENDIAN_MMIO
- select USE_OF
- help
- This enables support for the MIPS Technologies SEAD3 evaluation
- board.
-
config NEC_MARKEINS
bool "NEC EMMA2RH Mark-eins board"
select SOC_EMMA2RH
@@ -2961,7 +2926,7 @@ endchoice
choice
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
- !MIPS_MALTA && !MIPS_SEAD3 && \
+ !MIPS_MALTA && \
!CAVIUM_OCTEON_SOC
default MIPS_CMDLINE_FROM_BOOTLOADER
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index a3e8e4c..a6334a5 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -492,3 +492,16 @@ $(generic_defconfigs):
# Prevent generic merge_config rules attempting to merge single fragments
#
$(generic_config_dir)/%.config: ;
+
+#
+# Legacy defconfig compatibility - these targets used to be real defconfigs but
+# now that the boards have been converted to use the generic kernel they are
+# wrappers around the generic rules above.
+#
+.PHONY: sead3_defconfig
+sead3_defconfig:
+ $(Q)$(MAKE) 32r2el_defconfig BOARDS=sead-3
+
+.PHONY: sead3micro_defconfig
+sead3micro_defconfig:
+ $(Q)$(MAKE) micro32r2el_defconfig BOARDS=sead-3
diff --git a/arch/mips/boot/dts/mti/Makefile b/arch/mips/boot/dts/mti/Makefile
index 144d776..fcabd69 100644
--- a/arch/mips/boot/dts/mti/Makefile
+++ b/arch/mips/boot/dts/mti/Makefile
@@ -1,5 +1,5 @@
dtb-$(CONFIG_MIPS_MALTA) += malta.dtb
-dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
+dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mti/sead3.dts b/arch/mips/boot/dts/mti/sead3.dts
index 2579ca5..b112879 100644
--- a/arch/mips/boot/dts/mti/sead3.dts
+++ b/arch/mips/boot/dts/mti/sead3.dts
@@ -10,6 +10,7 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "mti,sead-3";
+ model = "MIPS SEAD-3";
interrupt-parent = <&gic>;
chosen {
diff --git a/arch/mips/configs/generic/board-sead-3.config b/arch/mips/configs/generic/board-sead-3.config
new file mode 100644
index 0000000..3b5e1ac
--- /dev/null
+++ b/arch/mips/configs/generic/board-sead-3.config
@@ -0,0 +1,32 @@
+CONFIG_LEGACY_BOARD_SEAD3=y
+
+CONFIG_AUXDISPLAY=y
+CONFIG_IMG_ASCII_LCD=y
+
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_SYSCON=y
+
+CONFIG_MMC=y
+CONFIG_MMC_SPI=y
+
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+
+CONFIG_NETDEVICES=y
+CONFIG_SMSC911X=y
+CONFIG_SMSC_PHY=y
+
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/arch/mips/configs/sead3_defconfig b/arch/mips/configs/sead3_defconfig
deleted file mode 100644
index ab4c465..0000000
--- a/arch/mips/configs/sead3_defconfig
+++ /dev/null
@@ -1,129 +0,0 @@
-CONFIG_MIPS_SEAD3=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_HZ_100=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="earlycon"
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_OF=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_ICPLUS_PHY=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_LEGACY_PTY_COUNT=32
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_SPI=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_RESTART=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_SENSORS_ADT7475=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_SPI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_SYSCON=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_M41T80=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_XFS_FS=y
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_QUOTA=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/configs/sead3micro_defconfig b/arch/mips/configs/sead3micro_defconfig
deleted file mode 100644
index cd91a77..0000000
--- a/arch/mips/configs/sead3micro_defconfig
+++ /dev/null
@@ -1,122 +0,0 @@
-CONFIG_MIPS_SEAD3=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MICROMIPS=y
-CONFIG_HZ_100=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=15
-CONFIG_EMBEDDED=y
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_SMSC911X=y
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_ICPLUS_PHY=y
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_LEGACY_PTY_COUNT=32
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_SPI=y
-CONFIG_SENSORS_ADT7475=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-CONFIG_MMC_SPI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_M41T80=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_XFS_FS=y
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_QUOTA=y
-# CONFIG_PRINT_QUOTA_WARNING is not set
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-# CONFIG_FTRACE is not set
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index baddb06..a606b3f 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -9,4 +9,11 @@ config LEGACY_BOARDS
kernel is booted without being provided with an FDT via the UHI
boot protocol.
+config LEGACY_BOARD_SEAD3
+ bool "Support MIPS SEAD-3 boards"
+ select LEGACY_BOARDS
+ help
+ Enable this to include support for booting on MIPS SEAD-3 FPGA-based
+ development boards, which boot using a legacy boot protocol.
+
endif
diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
index 26e6420..7c66494 100644
--- a/arch/mips/generic/Makefile
+++ b/arch/mips/generic/Makefile
@@ -11,3 +11,5 @@
obj-y += init.o
obj-y += irq.o
obj-y += proc.o
+
+obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
diff --git a/arch/mips/mti-sead3/sead3-dtshim.c b/arch/mips/generic/board-sead3.c
similarity index 72%
rename from arch/mips/mti-sead3/sead3-dtshim.c
rename to arch/mips/generic/board-sead3.c
index d6b0708..f4ae058 100644
--- a/arch/mips/mti-sead3/sead3-dtshim.c
+++ b/arch/mips/generic/board-sead3.c
@@ -4,11 +4,11 @@
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
+ * Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
-#define pr_fmt(fmt) "sead3-dtshim: " fmt
+#define pr_fmt(fmt) "sead3: " fmt
#include <linux/errno.h>
#include <linux/libfdt.h>
@@ -16,13 +16,49 @@
#include <asm/fw/fw.h>
#include <asm/io.h>
+#include <asm/machine.h>
#define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
#define SEAD_CONFIG_GIC_PRESENT BIT(1)
-static unsigned char fdt_buf[16 << 10] __initdata;
+#define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
+#define MIPS_REVISION_MACHINE (0xf << 4)
+#define MIPS_REVISION_MACHINE_SEAD3 (0x4 << 4)
-static int append_memory(void *fdt)
+static __init bool sead3_detect(void)
+{
+ uint32_t rev;
+
+ rev = __raw_readl((void *)MIPS_REVISION);
+ return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
+}
+
+static __init int append_cmdline(void *fdt)
+{
+ int err, chosen_off;
+
+ /* find or add chosen node */
+ chosen_off = fdt_path_offset(fdt, "/chosen");
+ if (chosen_off == -FDT_ERR_NOTFOUND)
+ chosen_off = fdt_path_offset(fdt, "/chosen@0");
+ if (chosen_off == -FDT_ERR_NOTFOUND)
+ chosen_off = fdt_add_subnode(fdt, 0, "chosen");
+ if (chosen_off < 0) {
+ pr_err("Unable to find or add DT chosen node: %d\n",
+ chosen_off);
+ return chosen_off;
+ }
+
+ err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
+ if (err) {
+ pr_err("Unable to set bootargs property: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static __init int append_memory(void *fdt)
{
unsigned long phys_memsize, memsize;
__be32 mem_array[2];
@@ -89,7 +125,7 @@ static int append_memory(void *fdt)
return 0;
}
-static int remove_gic(void *fdt)
+static __init int remove_gic(void *fdt)
{
const unsigned int cpu_ehci_int = 2;
const unsigned int cpu_uart_int = 4;
@@ -163,7 +199,7 @@ static int remove_gic(void *fdt)
return err;
}
- ehci_off = fdt_node_offset_by_compatible(fdt, -1, "mti,sead3-ehci");
+ ehci_off = fdt_node_offset_by_compatible(fdt, -1, "generic-ehci");
if (ehci_off < 0) {
pr_err("unable to find EHCI DT node: %d\n", ehci_off);
return ehci_off;
@@ -178,7 +214,7 @@ static int remove_gic(void *fdt)
return 0;
}
-static int serial_config(void *fdt)
+static __init int serial_config(void *fdt)
{
const char *yamontty, *mode_var;
char mode_var_name[9], path[18], parity;
@@ -257,21 +293,28 @@ static int serial_config(void *fdt)
return 0;
}
-void __init *sead3_dt_shim(void *fdt)
+static __init const void *sead3_fixup_fdt(const void *fdt,
+ const void *match_data)
{
+ static unsigned char fdt_buf[16 << 10] __initdata;
int err;
if (fdt_check_header(fdt))
panic("Corrupt DT");
- /* if this isn't SEAD3, leave the DT alone */
- if (fdt_node_check_compatible(fdt, 0, "mti,sead-3"))
- return fdt;
+ /* if this isn't SEAD3, something went wrong */
+ BUG_ON(fdt_node_check_compatible(fdt, 0, "mti,sead-3"));
+
+ fw_init_cmdline();
err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf));
if (err)
panic("Unable to open FDT: %d", err);
+ err = append_cmdline(fdt_buf);
+ if (err)
+ panic("Unable to patch FDT: %d", err);
+
err = append_memory(fdt_buf);
if (err)
panic("Unable to patch FDT: %d", err);
@@ -290,3 +333,44 @@ void __init *sead3_dt_shim(void *fdt)
return fdt_buf;
}
+
+static __init unsigned int sead3_measure_hpt_freq(void)
+{
+ void __iomem *status_reg = (void __iomem *)0xbf000410;
+ unsigned int freq, orig, tick = 0;
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ orig = readl(status_reg) & 0x2; /* get original sample */
+ /* wait for transition */
+ while ((readl(status_reg) & 0x2) == orig)
+ ;
+ orig = orig ^ 0x2; /* flip the bit */
+
+ write_c0_count(0);
+
+ /* wait 1 second (the sampling clock transitions every 10ms) */
+ while (tick < 100) {
+ /* wait for transition */
+ while ((readl(status_reg) & 0x2) == orig)
+ ;
+ orig = orig ^ 0x2; /* flip the bit */
+ tick++;
+ }
+
+ freq = read_c0_count();
+
+ local_irq_restore(flags);
+
+ return freq;
+}
+
+extern char __dtb_sead3_begin[];
+
+MIPS_MACHINE(sead3) = {
+ .fdt = __dtb_sead3_begin,
+ .detect = sead3_detect,
+ .fixup_fdt = sead3_fixup_fdt,
+ .measure_hpt_freq = sead3_measure_hpt_freq,
+};
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
deleted file mode 100644
index bfbd703..0000000
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Chris Dearman
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
-
-
-/*
- * CPU feature overrides for MIPS boards
- */
-#ifdef CONFIG_CPU_MIPS32
-#define cpu_has_tlb 1
-#define cpu_has_4kex 1
-#define cpu_has_4k_cache 1
-/* #define cpu_has_fpu ? */
-/* #define cpu_has_32fpr ? */
-#define cpu_has_counter 1
-/* #define cpu_has_watch ? */
-#define cpu_has_divec 1
-#define cpu_has_vce 0
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-/* #define cpu_has_prefetch ? */
-#define cpu_has_mcheck 1
-/* #define cpu_has_ejtag ? */
-#ifdef CONFIG_CPU_MICROMIPS
-#define cpu_has_llsc 0
-#else
-#define cpu_has_llsc 1
-#endif
-/* #define cpu_has_vtag_icache ? */
-/* #define cpu_has_dc_aliases ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_nofpuex 0
-/* #define cpu_has_64bits ? */
-/* #define cpu_has_64bit_zero_reg ? */
-/* #define cpu_has_inclusive_pcaches ? */
-#define cpu_icache_snoops_remote_store 1
-#endif
-
-#ifdef CONFIG_CPU_MIPS64
-#define cpu_has_tlb 1
-#define cpu_has_4kex 1
-#define cpu_has_4k_cache 1
-/* #define cpu_has_fpu ? */
-/* #define cpu_has_32fpr ? */
-#define cpu_has_counter 1
-/* #define cpu_has_watch ? */
-#define cpu_has_divec 1
-#define cpu_has_vce 0
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-/* #define cpu_has_prefetch ? */
-#define cpu_has_mcheck 1
-/* #define cpu_has_ejtag ? */
-#define cpu_has_llsc 1
-/* #define cpu_has_vtag_icache ? */
-/* #define cpu_has_dc_aliases ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_nofpuex 0
-/* #define cpu_has_64bits ? */
-/* #define cpu_has_64bit_zero_reg ? */
-/* #define cpu_has_inclusive_pcaches ? */
-#define cpu_icache_snoops_remote_store 1
-#endif
-
-#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
deleted file mode 100644
index 5d154cf..0000000
--- a/arch/mips/include/asm/mach-sead3/irq.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __ASM_MACH_MIPS_IRQ_H
-#define __ASM_MACH_MIPS_IRQ_H
-
-#define NR_IRQS 256
-
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
deleted file mode 100644
index 6cccd4d..0000000
--- a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Chris Dearman (chris@mips.com)
- * Copyright (C) 2007 Mips Technologies, Inc.
- */
-#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
-#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
-
- .macro kernel_entry_setup
- .endm
-
-/*
- * Do SMP slave processor setup necessary before we can safely execute C code.
- */
- .macro smp_slave_setup
- .endm
-
-#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-sead3/sead3-dtshim.h b/arch/mips/include/asm/mach-sead3/sead3-dtshim.h
deleted file mode 100644
index f5d7d9c..0000000
--- a/arch/mips/include/asm/mach-sead3/sead3-dtshim.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2016 Imagination Technologies
- * Author: Paul Burton <paul.burton@imgtec.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef __MIPS_SEAD3_DTSHIM_H__
-#define __MIPS_SEAD3_DTSHIM_H__
-
-#include <linux/init.h>
-
-#ifdef CONFIG_MIPS_SEAD3
-
-extern void __init *sead3_dt_shim(void *fdt);
-
-#else /* !CONFIG_MIPS_SEAD3 */
-
-static inline void *sead3_dt_shim(void *fdt)
-{
- return fdt;
-}
-
-#endif /* !CONFIG_MIPS_SEAD3 */
-
-#endif /* __MIPS_SEAD3_DTSHIM_H__ */
diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h
deleted file mode 100644
index d068fc4..0000000
--- a/arch/mips/include/asm/mach-sead3/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
-#define __ASM_MIPS_MACH_MIPS_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
-#define R4600_V1_HIT_CACHEOP_WAR 0
-#define R4600_V2_HIT_CACHEOP_WAR 0
-#define R5432_CP0_INTERRUPT_WAR 0
-#define BCM1250_M3_WAR 0
-#define SIBYTE_1956_WAR 0
-#define MIPS4K_ICACHE_REFILL_WAR 1
-#define MIPS_CACHE_SYNC_WAR 1
-#define TX49XX_ICACHE_INDEX_INV_WAR 0
-#define ICACHE_REFILLS_WORKAROUND_WAR 1
-#define R10000_LLSC_WAR 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/mti-sead3/Makefile b/arch/mips/mti-sead3/Makefile
deleted file mode 100644
index 1674b9c..0000000
--- a/arch/mips/mti-sead3/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Carsten Langgaard, carstenl@mips.com
-# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
-#
-# Copyright (C) 2008 Wind River Systems, Inc.
-# written by Ralf Baechle <ralf@linux-mips.org>
-#
-# Copyright (C) 2012 MIPS Technoligies, Inc. All rights reserved.
-# Steven J. Hill <sjhill@mips.com>
-#
-obj-y := sead3-dtshim.o
-obj-y += sead3-init.o
-obj-y += sead3-int.o
-obj-y += sead3-setup.o
-obj-y += sead3-time.o
diff --git a/arch/mips/mti-sead3/Platform b/arch/mips/mti-sead3/Platform
deleted file mode 100644
index 3870924..0000000
--- a/arch/mips/mti-sead3/Platform
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# MIPS SEAD-3 board
-#
-platform-$(CONFIG_MIPS_SEAD3) += mti-sead3/
-cflags-$(CONFIG_MIPS_SEAD3) += -I$(srctree)/arch/mips/include/asm/mach-sead3
-load-$(CONFIG_MIPS_SEAD3) += 0xffffffff80100000
-all-$(CONFIG_MIPS_SEAD3) := $(COMPRESSION_FNAME).srec
diff --git a/arch/mips/mti-sead3/sead3-init.c b/arch/mips/mti-sead3/sead3-init.c
deleted file mode 100644
index 50f3fcb..0000000
--- a/arch/mips/mti-sead3/sead3-init.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
- */
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/bootinfo.h>
-#include <asm/cacheflush.h>
-#include <asm/traps.h>
-#include <asm/mips-boards/generic.h>
-#include <asm/fw/fw.h>
-
-extern char except_vec_nmi;
-extern char except_vec_ejtag_debug;
-
-static void __init mips_nmi_setup(void)
-{
- void *base;
-
- base = cpu_has_veic ?
- (void *)(CAC_BASE + 0xa80) :
- (void *)(CAC_BASE + 0x380);
-#ifdef CONFIG_CPU_MICROMIPS
- /*
- * Decrement the exception vector address by one for microMIPS.
- */
- memcpy(base, (&except_vec_nmi - 1), 0x80);
-
- /*
- * This is a hack. We do not know if the boot loader was built with
- * microMIPS instructions or not. If it was not, the NMI exception
- * code at 0x80000a80 will be taken in MIPS32 mode. The hand coded
- * assembly below forces us into microMIPS mode if we are a pure
- * microMIPS kernel. The assembly instructions are:
- *
- * 3C1A8000 lui k0,0x8000
- * 375A0381 ori k0,k0,0x381
- * 03400008 jr k0
- * 00000000 nop
- *
- * The mode switch occurs by jumping to the unaligned exception
- * vector address at 0x80000381 which would have been 0x80000380
- * in MIPS32 mode. The jump to the unaligned address transitions
- * us into microMIPS mode.
- */
- if (!cpu_has_veic) {
- void *base2 = (void *)(CAC_BASE + 0xa80);
- *((unsigned int *)base2) = 0x3c1a8000;
- *((unsigned int *)base2 + 1) = 0x375a0381;
- *((unsigned int *)base2 + 2) = 0x03400008;
- *((unsigned int *)base2 + 3) = 0x00000000;
- flush_icache_range((unsigned long)base2,
- (unsigned long)base2 + 0x10);
- }
-#else
- memcpy(base, &except_vec_nmi, 0x80);
-#endif
- flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
-}
-
-static void __init mips_ejtag_setup(void)
-{
- void *base;
-
- base = cpu_has_veic ?
- (void *)(CAC_BASE + 0xa00) :
- (void *)(CAC_BASE + 0x300);
-#ifdef CONFIG_CPU_MICROMIPS
- /* Deja vu... */
- memcpy(base, (&except_vec_ejtag_debug - 1), 0x80);
- if (!cpu_has_veic) {
- void *base2 = (void *)(CAC_BASE + 0xa00);
- *((unsigned int *)base2) = 0x3c1a8000;
- *((unsigned int *)base2 + 1) = 0x375a0301;
- *((unsigned int *)base2 + 2) = 0x03400008;
- *((unsigned int *)base2 + 3) = 0x00000000;
- flush_icache_range((unsigned long)base2,
- (unsigned long)base2 + 0x10);
- }
-#else
- memcpy(base, &except_vec_ejtag_debug, 0x80);
-#endif
- flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
-}
-
-void __init prom_init(void)
-{
- board_nmi_handler_setup = mips_nmi_setup;
- board_ejtag_handler_setup = mips_ejtag_setup;
-
- fw_init_cmdline();
-}
-
-void __init prom_free_prom_memory(void)
-{
-}
diff --git a/arch/mips/mti-sead3/sead3-int.c b/arch/mips/mti-sead3/sead3-int.c
deleted file mode 100644
index 2e6b732..0000000
--- a/arch/mips/mti-sead3/sead3-int.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
- */
-#include <linux/init.h>
-#include <linux/irqchip.h>
-#include <linux/irqchip/mips-gic.h>
-
-#include <asm/cpu-info.h>
-#include <asm/irq.h>
-
-void __init arch_init_irq(void)
-{
- irqchip_init();
-
- pr_info("GIC: %spresent\n", (gic_present) ? "" : "not ");
- pr_info("EIC: %s\n",
- (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off");
-}
-
diff --git a/arch/mips/mti-sead3/sead3-setup.c b/arch/mips/mti-sead3/sead3-setup.c
deleted file mode 100644
index c915e54..0000000
--- a/arch/mips/mti-sead3/sead3-setup.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
- * Copyright (C) 2013 Imagination Technologies Ltd.
- */
-#include <linux/init.h>
-#include <linux/libfdt.h>
-#include <linux/of_fdt.h>
-
-#include <asm/prom.h>
-
-#include <asm/mach-sead3/sead3-dtshim.h>
-#include <asm/mips-boards/generic.h>
-
-const char *get_system_type(void)
-{
- return "MIPS SEAD3";
-}
-
-void __init *plat_get_fdt(void)
-{
- return (void *)__dtb_start;
-}
-
-void __init plat_mem_setup(void)
-{
- void *fdt = plat_get_fdt();
-
- fdt = sead3_dt_shim(fdt);
- __dt_setup_arch(fdt);
-}
-
-void __init device_tree_init(void)
-{
- unflatten_and_copy_device_tree();
-}
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
deleted file mode 100644
index 71feb51..0000000
--- a/arch/mips/mti-sead3/sead3-time.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
- */
-#include <linux/init.h>
-#include <linux/irqchip/mips-gic.h>
-
-#include <asm/cpu.h>
-#include <asm/setup.h>
-#include <asm/time.h>
-#include <asm/irq.h>
-#include <asm/mips-boards/generic.h>
-
-static void __iomem *status_reg = (void __iomem *)0xbf000410;
-
-/*
- * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect.
- */
-static unsigned int __init estimate_cpu_frequency(void)
-{
- unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
- unsigned int tick = 0;
- unsigned int freq;
- unsigned int orig;
- unsigned long flags;
-
- local_irq_save(flags);
-
- orig = readl(status_reg) & 0x2; /* get original sample */
- /* wait for transition */
- while ((readl(status_reg) & 0x2) == orig)
- ;
- orig = orig ^ 0x2; /* flip the bit */
-
- write_c0_count(0);
-
- /* wait 1 second (the sampling clock transitions every 10ms) */
- while (tick < 100) {
- /* wait for transition */
- while ((readl(status_reg) & 0x2) == orig)
- ;
- orig = orig ^ 0x2; /* flip the bit */
- tick++;
- }
-
- freq = read_c0_count();
-
- local_irq_restore(flags);
-
- mips_hpt_frequency = freq;
-
- /* Adjust for processor */
- if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
- (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
- freq *= 2;
-
- freq += 5000; /* rounding */
- freq -= freq%10000;
-
- return freq ;
-}
-
-int get_c0_perfcount_int(void)
-{
- if (gic_present)
- return gic_get_c0_perfcount_int();
- if (cp0_perfcount_irq >= 0)
- return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
- return -1;
-}
-EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
-
-unsigned int get_c0_compare_int(void)
-{
- if (gic_present)
- return gic_get_c0_compare_int();
- return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
-}
-
-void __init plat_time_init(void)
-{
- unsigned int est_freq;
-
- est_freq = estimate_cpu_frequency();
-
- pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
- (est_freq % 1000000) * 100 / 1000000);
-}
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 24/26] dt-bindings: Document img,boston-clock binding
2016-08-30 17:29 [PATCH v2 00/26] MIPS generic kernels, SEAD-3 & Boston support Paul Burton
` (2 preceding siblings ...)
2016-08-30 17:29 ` [PATCH v2 23/26] MIPS: generic: Convert SEAD-3 to a generic board Paul Burton
@ 2016-08-30 17:29 ` Paul Burton
[not found] ` <20160830172929.16948-1-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
4 siblings, 0 replies; 6+ messages in thread
From: Paul Burton @ 2016-08-30 17:29 UTC (permalink / raw)
To: linux-mips, Ralf Baechle
Cc: Paul Burton, devicetree, Michael Turquette, Stephen Boyd,
linux-kernel, Rob Herring, Mark Rutland, linux-clk
Add device tree binding documentation for the clocks provided by the
MIPS Boston development board from Imagination Technologies, and a
header file describing the available clocks for use by device trees &
driver.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---
Changes in v2:
- Add BOSTON_CLK_INPUT to expose the input clock.
.../devicetree/bindings/clock/img,boston-clock.txt | 27 ++++++++++++++++++++++
include/dt-bindings/clock/boston-clock.h | 14 +++++++++++
2 files changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/img,boston-clock.txt
create mode 100644 include/dt-bindings/clock/boston-clock.h
diff --git a/Documentation/devicetree/bindings/clock/img,boston-clock.txt b/Documentation/devicetree/bindings/clock/img,boston-clock.txt
new file mode 100644
index 0000000..c01ea60
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/img,boston-clock.txt
@@ -0,0 +1,27 @@
+Binding for Imagination Technologies MIPS Boston clock sources.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : Should be "img,boston-clock".
+- #clock-cells : Should be set to 1.
+ Values available for clock consumers can be found in the header file:
+ <dt-bindings/clock/boston-clock.h>
+- regmap : Phandle to the Boston platform register system controller.
+ This should contain a phandle to the system controller node covering the
+ platform registers provided by the Boston board.
+
+Example:
+
+ clk_boston: clock {
+ compatible = "img,boston-clock";
+ #clock-cells = <1>;
+ regmap = <&plat_regs>;
+ };
+
+ uart0: uart@17ffe000 {
+ /* ... */
+ clocks = <&clk_boston BOSTON_CLK_SYS>;
+ };
diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h
new file mode 100644
index 0000000..a6f0098
--- /dev/null
+++ b/include/dt-bindings/clock/boston-clock.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+
+#define BOSTON_CLK_INPUT 0
+#define BOSTON_CLK_SYS 1
+#define BOSTON_CLK_CPU 2
+
+#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 26/26] MIPS: generic: Support MIPS Boston development boards
[not found] ` <20160830172929.16948-1-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
@ 2016-08-30 17:29 ` Paul Burton
0 siblings, 0 replies; 6+ messages in thread
From: Paul Burton @ 2016-08-30 17:29 UTC (permalink / raw)
To: linux-mips-6z/3iImG2C8G8FEW9MqTrA, Ralf Baechle
Cc: Paul Burton, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Mark Rutland
Add support for the MIPS Boston development board to generic kernels,
which essentially amounts to:
- Adding the device tree source for the MIPS Boston board.
- Adding a Kconfig fragment which enables the appropriate drivers for
the MIPS Boston board.
With these changes in place generic kernels will support the board by
default, and kernels with only the drivers needed for Boston enabled can
be configured by setting BOARDS=boston during configuration. For
example:
$ make ARCH=mips 64r6el_defconfig BOARDS=boston
Signed-off-by: Paul Burton <paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
---
Changes in v2: None
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/img/Makefile | 7 +
arch/mips/boot/dts/img/boston.dts | 230 ++++++++++++++++++++++++++
arch/mips/configs/generic/board-boston.config | 46 ++++++
arch/mips/generic/Kconfig | 8 +
arch/mips/generic/vmlinux.its.S | 25 +++
6 files changed, 317 insertions(+)
create mode 100644 arch/mips/boot/dts/img/Makefile
create mode 100644 arch/mips/boot/dts/img/boston.dts
create mode 100644 arch/mips/configs/generic/board-boston.config
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index fc7a0a9..b9db492 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -1,5 +1,6 @@
dts-dirs += brcm
dts-dirs += cavium-octeon
+dts-dirs += img
dts-dirs += ingenic
dts-dirs += lantiq
dts-dirs += mti
diff --git a/arch/mips/boot/dts/img/Makefile b/arch/mips/boot/dts/img/Makefile
new file mode 100644
index 0000000..ae119d3
--- /dev/null
+++ b/arch/mips/boot/dts/img/Makefile
@@ -0,0 +1,7 @@
+dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += boston.dtb
+
+# Force kbuild to make empty built-in.o if necessary
+obj- += dummy.o
+
+always := $(dtb-y)
+clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img/boston.dts
new file mode 100644
index 0000000..b357376
--- /dev/null
+++ b/arch/mips/boot/dts/img/boston.dts
@@ -0,0 +1,230 @@
+/dts-v1/;
+
+#include <dt-bindings/clock/boston-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "img,boston";
+
+ chosen {
+ stdout-path = "uart0:115200";
+ };
+
+ aliases {
+ uart0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "img,mips";
+ reg = <0>;
+ clocks = <&clk_boston BOSTON_CLK_CPU>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ pci0: pci@10000000 {
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x10000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x40000000
+ 0x40000000 0 0x40000000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci0_intc 0>,
+ <0 0 0 2 &pci0_intc 1>,
+ <0 0 0 3 &pci0_intc 2>,
+ <0 0 0 4 &pci0_intc 3>;
+
+ pci0_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pci1: pci@12000000 {
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x12000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x20000000
+ 0x20000000 0 0x20000000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci1_intc 0>,
+ <0 0 0 2 &pci1_intc 1>,
+ <0 0 0 3 &pci1_intc 2>,
+ <0 0 0 4 &pci1_intc 3>;
+
+ pci1_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pci2: pci@14000000 {
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ device_type = "pci";
+ reg = <0x14000000 0x2000000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0 0x16000000
+ 0x16000000 0 0x100000>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pci2_intc 0>,
+ <0 0 0 2 &pci2_intc 1>,
+ <0 0 0 3 &pci2_intc 2>,
+ <0 0 0 4 &pci2_intc 3>;
+
+ pci2_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ pci2_root@0,0,0 {
+ compatible = "pci10ee,7021";
+ reg = <0x00000000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ eg20t_bridge@1,0,0 {
+ compatible = "pci8086,8800";
+ reg = <0x00010000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+
+ eg20t_mac@2,0,1 {
+ compatible = "pci8086,8802";
+ reg = <0x00020100 0 0 0 0>;
+ phy-reset-gpios = <&eg20t_gpio 6
+ GPIO_ACTIVE_LOW>;
+ };
+
+ eg20t_gpio: eg20t_gpio@2,0,2 {
+ compatible = "pci8086,8803";
+ reg = <0x00020200 0 0 0 0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ eg20t_i2c@2,12,2 {
+ compatible = "pci8086,8817";
+ reg = <0x00026200 0 0 0 0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@0x68 {
+ compatible = "st,m41t81s";
+ reg = <0x68>;
+ };
+ };
+ };
+ };
+ };
+
+ gic: interrupt-controller@16120000 {
+ compatible = "mti,gic";
+ reg = <0x16120000 0x20000>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&clk_boston BOSTON_CLK_CPU>;
+ };
+ };
+
+ cdmm@16140000 {
+ compatible = "mti,mips-cdmm";
+ reg = <0x16140000 0x8000>;
+ };
+
+ cpc@16200000 {
+ compatible = "mti,mips-cpc";
+ reg = <0x16200000 0x8000>;
+ };
+
+ plat_regs: system-controller@17ffd000 {
+ compatible = "img,boston-platform-regs", "syscon";
+ reg = <0x17ffd000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ clk_boston: clock {
+ compatible = "img,boston-clock";
+ #clock-cells = <1>;
+ regmap = <&plat_regs>;
+ u-boot,dm-pre-reloc;
+ };
+
+ reboot: syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&plat_regs>;
+ offset = <0x10>;
+ mask = <0x10>;
+ };
+
+ uart0: uart@17ffe000 {
+ compatible = "ns16550a";
+ reg = <0x17ffe000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&clk_boston BOSTON_CLK_SYS>;
+
+ u-boot,dm-pre-reloc;
+ };
+
+ lcd: lcd@17fff000 {
+ compatible = "img,boston-lcd";
+ reg = <0x17fff000 0x8>;
+ };
+};
diff --git a/arch/mips/configs/generic/board-boston.config b/arch/mips/configs/generic/board-boston.config
new file mode 100644
index 0000000..09864a4
--- /dev/null
+++ b/arch/mips/configs/generic/board-boston.config
@@ -0,0 +1,46 @@
+CONFIG_FIT_IMAGE_FDT_BOSTON=y
+
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SCSI=y
+
+CONFIG_AUXDISPLAY=y
+CONFIG_IMG_ASCII_LCD=y
+
+CONFIG_COMMON_CLK_BOSTON=y
+
+CONFIG_DMADEVICES=y
+CONFIG_PCH_DMA=y
+
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCH=y
+
+CONFIG_I2C=y
+CONFIG_I2C_EG20T=y
+
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PCI=y
+
+CONFIG_NETDEVICES=y
+CONFIG_PCH_GBE=y
+
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_XILINX=y
+
+CONFIG_PCH_PHUB=y
+
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_M41T80=y
+
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+
+CONFIG_SPI=y
+CONFIG_SPI_TOPCLIFF_PCH=y
+
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index a606b3f..16eb939 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -16,4 +16,12 @@ config LEGACY_BOARD_SEAD3
Enable this to include support for booting on MIPS SEAD-3 FPGA-based
development boards, which boot using a legacy boot protocol.
+config FIT_IMAGE_FDT_BOSTON
+ bool "Include FDT for MIPS Boston boards"
+ help
+ Enable this to include the FDT for the MIPS Boston development board
+ from Imagination Technologies in the FIT kernel image. You should
+ enable this if you wish to boot on a MIPS Boston board, as it is
+ expected by the bootloader.
+
endif
diff --git a/arch/mips/generic/vmlinux.its.S b/arch/mips/generic/vmlinux.its.S
index f67fbf1..3390e2f 100644
--- a/arch/mips/generic/vmlinux.its.S
+++ b/arch/mips/generic/vmlinux.its.S
@@ -29,3 +29,28 @@
};
};
};
+
+#ifdef CONFIG_FIT_IMAGE_FDT_BOSTON
+/ {
+ images {
+ fdt@boston {
+ description = "img,boston Device Tree";
+ data = /incbin/("boot/dts/img/boston.dtb");
+ type = "flat_dt";
+ arch = "mips";
+ compression = "none";
+ hash@0 {
+ algo = "sha1";
+ };
+ };
+ };
+
+ configurations {
+ conf@boston {
+ description = "Boston Linux kernel";
+ kernel = "kernel@0";
+ fdt = "fdt@boston";
+ };
+ };
+};
+#endif /* CONFIG_FIT_IMAGE_FDT_BOSTON */
--
2.9.3
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^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-08-30 17:29 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-08-30 17:29 [PATCH v2 00/26] MIPS generic kernels, SEAD-3 & Boston support Paul Burton
2016-08-30 17:29 ` [PATCH v2 11/26] dt-bindings: Document mti,mips-cpc binding Paul Burton
2016-08-30 17:29 ` [PATCH v2 13/26] dt-bindings: Document mti,mips-cdmm binding Paul Burton
2016-08-30 17:29 ` [PATCH v2 23/26] MIPS: generic: Convert SEAD-3 to a generic board Paul Burton
2016-08-30 17:29 ` [PATCH v2 24/26] dt-bindings: Document img,boston-clock binding Paul Burton
[not found] ` <20160830172929.16948-1-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
2016-08-30 17:29 ` [PATCH v2 26/26] MIPS: generic: Support MIPS Boston development boards Paul Burton
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