From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH 4/8] pinctrl: aspeed-g5: Fix pin association of SPI1 function Date: Mon, 3 Oct 2016 13:57:13 -0500 Message-ID: <20161003185713.GA30227@rob-hp-laptop> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Andrew Jeffery Cc: Linus Walleij , Joel Stanley , Mark Rutland , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, openbmc@lists.ozlabs.org List-Id: devicetree@vger.kernel.org On Wed, Sep 28, 2016 at 12:20:16AM +0930, Andrew Jeffery wrote: > The SPI1 function was associated with the wrong pins: The functions that > those pins provide is either an SPI debug or passthrough function > coupled to SPI1. Make the SPI1 mux function configure the relevant pins > and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins > that were already defined. > > The notation used in the datasheet's multi-function pin table for the SoC is > often creative: in this case the SYS* signals are enabled by a single bit, > which is nothing unusual on its own, but in this case the bit was also > participating in a multi-bit bitfield and therefore represented multiple > functions. This fact was overlooked in the original patch. > > Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) > Signed-off-by: Andrew Jeffery > --- > Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 4 +- Acked-by: Rob Herring > drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 86 ++++++- > 2 files changed, 81 insertions(+), 9 deletions(-)