From: Viresh Kumar <viresh.kumar-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
To: Dave Gerlach <d-gerlach-l0cyMroinI0@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
"Rafael J . Wysocki"
<rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org>,
Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>,
Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
Subject: Re: [PATCH v3 2/3] Documentation: dt: add bindings for ti-cpufreq
Date: Wed, 2 Nov 2016 09:29:41 +0530 [thread overview]
Message-ID: <20161102035941.GA10786@vireshk-i7> (raw)
In-Reply-To: <20161027214131.1725-3-d-gerlach-l0cyMroinI0@public.gmane.org>
On 27-10-16, 16:41, Dave Gerlach wrote:
> Add the device tree bindings document for the TI CPUFreq/OPP driver
> on AM33xx and AM43xx SoCs. The operating-points-v2 binding allows us
> to provide an opp-supported-hw property for each OPP to define when
> it is available. This driver is responsible for reading and parsing
> registers to determine which OPPs can be selectively enabled based
> on the specific SoC in use by matching against the opp-supported-hw
> data.
>
> Signed-off-by: Dave Gerlach <d-gerlach-l0cyMroinI0@public.gmane.org>
> ---
> v2->v3:
> - Move ti,syscon-* properties under opp table instead of cpu node, as
> that is a better location for them.
> - For the opp table do not use platform specific compatible strings
> but instead a operating-points-v2-ti-cpu
>
> .../devicetree/bindings/cpufreq/ti-cpufreq.txt | 132 +++++++++++++++++++++
> 1 file changed, 132 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
> new file mode 100644
> index 000000000000..467ad29c75c9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
> @@ -0,0 +1,132 @@
> +TI CPUFreq and OPP bindings
> +================================
> +
> +Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx
> +families support different OPPs depending on the silicon variant in use.
> +The ti_cpufreq driver can use revision and an efuse value from the SoC to
> +provide the OPP framework with supported hardware information. This is
> +used to determine which OPPs from the operating-points-v2 table get enabled
> +when it is parsed by the OPP framework.
> +
> +Required properties:
> +--------------------
> +In 'cpus' nodes:
> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
> +
> +In 'operating-points-v2' table:
> +- compatible: Should be 'operating-points-v2-ti-cpu' for am335x, am43xx,
> + and dra7xx/am57xx SoCs
> +- ti,syscon-efuse: Syscon phandle, offset to efuse register, efuse register
> + mask, and efuse register shift to get the relevant bits
> + that describe OPP availability.
> +- ti,syscon-rev: Syscon and offset used to look up revision value on SoC.
> +
> +Optional properties:
> +--------------------
> +For each opp entry in 'operating-points-v2' table:
> +- opp-supported-hw: Two bitfields indicating:
> + 1. Which revision of the SoC the OPP is supported by
> + 2. Which eFuse bits indicate this OPP is available
> +
> + A bitwise AND is performed against these values and if any bit
> + matches, the OPP gets enabled. Not providing the property for an
> + entry indicates that an OPP is always supported.
> +
> +Example:
> +--------
> +
> +/* From arch/arm/boot/dts/am33xx.dtsi */
> +cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu@0 {
> + compatible = "arm,cortex-a8";
> + device_type = "cpu";
> + reg = <0>;
> +
> + operating-points-v2 = <&cpu0_opp_table>;
> +
> + clocks = <&dpll_mpu_ck>;
> + clock-names = "cpu";
> +
> + clock-latency = <300000>; /* From omap-cpufreq driver */
> + };
> +};
> +
> +/*
> + * cpu0 has different OPPs depending on SoC revision and some on revisions
> + * 0x2 and 0x4 have eFuse bits that indicate if they are available or not
> + */
> +cpu0_opp_table: opp_table0 {
> + compatible = "operating-points-v2-ti-am3352-cpu";
> + ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
> + ti,syscon-rev = <&scm_conf 0x600>;
> +
> + /*
> + * The three following nodes are marked with opp-suspend
> + * because they can not be enabled simultaneously on a
> + * single SoC.
> + */
> + opp50@300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + opp-microvolt = <950000 931000 969000>;
> + opp-supported-hw = <0x06 0x0010>;
> + opp-suspend;
> + };
> +
> + opp100@275000000 {
> + opp-hz = /bits/ 64 <275000000>;
> + opp-microvolt = <1100000 1078000 1122000>;
> + opp-supported-hw = <0x01 0x00FF>;
> + opp-suspend;
> + };
> +
> + opp100@300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + opp-microvolt = <1100000 1078000 1122000>;
> + opp-supported-hw = <0x06 0x0020>;
> + opp-suspend;
Only one OPP in the table can be marked as suspend OPP.
--
viresh
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2016-11-02 3:59 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-27 21:41 [PATCH v3 0/3] cpufreq: Introduce TI CPUFreq/OPP Driver Dave Gerlach
2016-10-27 21:41 ` [PATCH v3 1/3] PM / OPP: Expose _of_get_opp_desc_node as dev_pm_opp API Dave Gerlach
2016-10-27 23:34 ` kbuild test robot
2016-10-28 4:05 ` Viresh Kumar
2016-10-31 21:03 ` Dave Gerlach
[not found] ` <20161027214131.1725-1-d-gerlach-l0cyMroinI0@public.gmane.org>
2016-10-27 21:41 ` [PATCH v3 2/3] Documentation: dt: add bindings for ti-cpufreq Dave Gerlach
[not found] ` <20161027214131.1725-3-d-gerlach-l0cyMroinI0@public.gmane.org>
2016-11-02 3:59 ` Viresh Kumar [this message]
2016-11-02 16:03 ` Dave Gerlach
[not found] ` <9a185460-a241-4876-2915-6975c57527ca-l0cyMroinI0@public.gmane.org>
2016-11-03 2:14 ` Viresh Kumar
2016-10-27 21:41 ` [PATCH v3 3/3] cpufreq: ti: Add cpufreq driver to determine available OPPs at runtime Dave Gerlach
[not found] ` <20161027214131.1725-4-d-gerlach-l0cyMroinI0@public.gmane.org>
2016-11-02 4:03 ` Viresh Kumar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20161102035941.GA10786@vireshk-i7 \
--to=viresh.kumar-qsej5fyqhm4dnm+yrofe0a@public.gmane.org \
--cc=d-gerlach-l0cyMroinI0@public.gmane.org \
--cc=devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org \
--cc=linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=nm-l0cyMroinI0@public.gmane.org \
--cc=rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org \
--cc=robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org \
--cc=tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).