[PATCH v2 0/9] rockchip: add more power domain and devices dts for rk3399

[PATCH v2 0/9] rockchip: add more power domain and devices dts for rk3399

[Caesar Wang]

Hi all,

Please allow me to integrate these patches.
They are missing or losing for upstream, then there are some patches
are  always depending on them.

The following patches are releated to PD.
git log --oneline
827198c arm64: dts: rockchip: add the usb3 pd for rk3399
95e95b4 arm64: dts: rockchip: support dwc3 USB for rk3399
3ced49c arm64: dts: rockchip: add pd_edp node for rk3399
e19db3f arm64: dts: rockchip: introduce pclk_vio_grf in eDP device node
eb92079 arm64: dts: rockchip: add backlight support for rk3399 evb board
20b8135 arm64: dts: rockchip: add eDP device node for rk3399
480a1bb arm64: dts: rockchip: add VOP and VOP iommu node for rk3399
4964c0a arm64: dts: rockchip: add pd_sd power node for rk3399
c407a4c arm64: dts: rockchip: add eMMC's power domain support for rk3399

----
Hi Heiko & guys,

This series patches support the below PDs.

1) sd & emmc pd
4964c0a arm64: dts: rockchip: add pd_sd power node for rk3399
c407a4c arm64: dts: rockchip: add eMMC's power domain support for rk3399

2) edp pd
3ced49c arm64: dts: rockchip: add pd_edp node for rk3399
e19db3f arm64: dts: rockchip: introduce pclk_vio_grf in eDP device node
eb92079 arm64: dts: rockchip: add backlight support for rk3399 evb board
20b8135 arm64: dts: rockchip: add eDP device node for rk3399
480a1bb arm64: dts: rockchip: add VOP and VOP iommu node for rk3399

3) usb3 pd
827198c arm64: dts: rockchip: add the usb3 pd for rk3399
95e95b4 arm64: dts: rockchip: support dwc3 USB for rk3399

Thanks,
Caesar


Changes in v2:
- Reviewed-on: https://chromium-review.googlesource.com/376558
- Verified on ChromeOS kernel4.4
- v1 on https://patchwork.kernel.org/patch/9322553/
- Reviewed-on: https://chromium-review.googlesource.com/386483
- Verified on ChromeOS kernel4.4
- Yakir posted the original patch on
- https://patchwork.kernel.org/patch/9191777
- the original patches from brian posting on
  https://chromium-review.googlesource.com/343603
- Reviewed-on: https://chromium-review.googlesource.com/384280

Brian Norris (1):
  arm64: dts: rockchip: support dwc3 USB for rk3399

Caesar Wang (1):
  arm64: dts: rockchip: add the usb3 pd for rk3399

Mark Yao (1):
  arm64: dts: rockchip: add VOP and VOP iommu node for rk3399

Yakir Yang (3):
  arm64: dts: rockchip: add eDP device node for rk3399
  arm64: dts: rockchip: add backlight support for rk3399 evb board
  arm64: dts: rockchip: introduce pclk_vio_grf in eDP device node

Ziyuan Xu (1):
  arm64: dts: rockchip: add eMMC's power domain support for rk3399

zhangqing (2):
  arm64: dts: rockchip: add pd_sd power node for rk3399
  arm64: dts: rockchip: add pd_edp node for rk3399

 arch/arm64/boot/dts/rockchip/rk3399-evb.dts |  40 ++++++
 arch/arm64/boot/dts/rockchip/rk3399.dtsi    | 210 ++++++++++++++++++++++++++++
 2 files changed, 250 insertions(+)

-- 
2.7.4

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[PATCH v2 1/9] arm64: dts: rockchip: add eMMC's power domain support for rk3399

[Caesar Wang]

From: Ziyuan Xu <xzy.xu@rock-chips.com>

Control power domain for eMMC via genpd to reduce power consumption.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v2:
- Reviewed-on: https://chromium-review.googlesource.com/376558
- Verified on ChromeOS kernel4.4

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index cbb7f8b..b401176 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -269,6 +269,7 @@
 		#clock-cells = <0>;
 		phys = <&emmc_phy>;
 		phy-names = "phy_arasan";
+		power-domains = <&power RK3399_PD_EMMC>;
 		status = "disabled";
 	};
 
@@ -690,6 +691,11 @@
 		status = "disabled";
 	};
 
+	qos_emmc: qos@ffa58000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa58000 0x0 0x20>;
+	};
+
 	qos_gmac: qos@ffa5c000 {
 		compatible = "syscon";
 		reg = <0x0 0xffa5c000 0x0 0x20>;
@@ -823,6 +829,11 @@
 			};
 
 			/* These power domains are grouped by VD_LOGIC */
+			pd_emmc@RK3399_PD_EMMC {
+				reg = <RK3399_PD_EMMC>;
+				clocks = <&cru ACLK_EMMC>;
+				pm_qos = <&qos_emmc>;
+			};
 			pd_gmac@RK3399_PD_GMAC {
 				reg = <RK3399_PD_GMAC>;
 				clocks = <&cru ACLK_GMAC>;
-- 
2.7.4

Re: [PATCH v2 1/9] arm64: dts: rockchip: add eMMC's power domain support for rk3399

[Shawn Lin]

On 2016/11/9 21:21, Caesar Wang wrote:
> From: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> Control power domain for eMMC via genpd to reduce power consumption.
>
> Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

It was verified on my rk3399 evb with kernel4.4, so
free feel to add my tag,

Tested-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

BTW, it seems my reply is bounced form Yakir's address, so please
remove him from CC list if he changed his mail address.

> ---
>
> Changes in v2:
> - Reviewed-on: https://chromium-review.googlesource.com/376558
> - Verified on ChromeOS kernel4.4
>
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index cbb7f8b..b401176 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -269,6 +269,7 @@
>  		#clock-cells = <0>;
>  		phys = <&emmc_phy>;
>  		phy-names = "phy_arasan";
> +		power-domains = <&power RK3399_PD_EMMC>;
>  		status = "disabled";
>  	};
>
> @@ -690,6 +691,11 @@
>  		status = "disabled";
>  	};
>
> +	qos_emmc: qos@ffa58000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa58000 0x0 0x20>;
> +	};
> +
>  	qos_gmac: qos@ffa5c000 {
>  		compatible = "syscon";
>  		reg = <0x0 0xffa5c000 0x0 0x20>;
> @@ -823,6 +829,11 @@
>  			};
>
>  			/* These power domains are grouped by VD_LOGIC */
> +			pd_emmc@RK3399_PD_EMMC {
> +				reg = <RK3399_PD_EMMC>;
> +				clocks = <&cru ACLK_EMMC>;
> +				pm_qos = <&qos_emmc>;
> +			};
>  			pd_gmac@RK3399_PD_GMAC {
>  				reg = <RK3399_PD_GMAC>;
>  				clocks = <&cru ACLK_GMAC>;
>


-- 
Best Regards
Shawn Lin

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Re: [PATCH v2 1/9] arm64: dts: rockchip: add eMMC's power domain support for rk3399

[Caesar Wang]

On 2016年11月12日 12:22, Shawn Lin wrote:
> On 2016/11/9 21:21, Caesar Wang wrote:
>> From: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>
>> Control power domain for eMMC via genpd to reduce power consumption.
>>
>> Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> It was verified on my rk3399 evb with kernel4.4, so
> free feel to add my tag,
>
> Tested-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>

Thanks the tests.

> BTW, it seems my reply is bounced form Yakir's address, so please
> remove him from CC list if he changed his mail address.

Right, Yakir's (ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org) address had left this world.;-)
But the patman tool is auto sending with the Cc people.

-
Caesar
>
>> ---
>>
>> Changes in v2:
>> - Reviewed-on: https://chromium-review.googlesource.com/376558
>> - Verified on ChromeOS kernel4.4
>>
>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
>> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> index cbb7f8b..b401176 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> @@ -269,6 +269,7 @@
>> #clock-cells = <0>;
>> phys = <&emmc_phy>;
>> phy-names = "phy_arasan";
>> + power-domains = <&power RK3399_PD_EMMC>;
>> status = "disabled";
>> };
>>
>> @@ -690,6 +691,11 @@
>> status = "disabled";
>> };
>>
>> + qos_emmc: qos@ffa58000 {
>> + compatible = "syscon";
>> + reg = <0x0 0xffa58000 0x0 0x20>;
>> + };
>> +
>> qos_gmac: qos@ffa5c000 {
>> compatible = "syscon";
>> reg = <0x0 0xffa5c000 0x0 0x20>;
>> @@ -823,6 +829,11 @@
>> };
>>
>> /* These power domains are grouped by VD_LOGIC */
>> + pd_emmc@RK3399_PD_EMMC {
>> + reg = <RK3399_PD_EMMC>;
>> + clocks = <&cru ACLK_EMMC>;
>> + pm_qos = <&qos_emmc>;
>> + };
>> pd_gmac@RK3399_PD_GMAC {
>> reg = <RK3399_PD_GMAC>;
>> clocks = <&cru ACLK_GMAC>;
>>
>
>


-- 
caesar wang | software engineer | wxt-TNX95d0MmH73oGB3hsPCZA@public.gmane.org


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Re: [PATCH v2 1/9] arm64: dts: rockchip: add eMMC's power domain support for rk3399

[Heiko Stuebner]

Am Mittwoch, 9. November 2016, 21:21:53 CET schrieb Caesar Wang:
> From: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> 
> Control power domain for eMMC via genpd to reduce power consumption.
> 
> Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Authorship / Signed-off mismatch. From above suggest Ziyuan is the author 
while first Signed-off-by indicates Elaine as author. Please clarify.


Thanks
Heiko

> ---
> 
> Changes in v2:
> - Reviewed-on: https://chromium-review.googlesource.com/376558
> - Verified on ChromeOS kernel4.4
> 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cbb7f8b..b401176 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -269,6 +269,7 @@
>  		#clock-cells = <0>;
>  		phys = <&emmc_phy>;
>  		phy-names = "phy_arasan";
> +		power-domains = <&power RK3399_PD_EMMC>;
>  		status = "disabled";
>  	};
> 
> @@ -690,6 +691,11 @@
>  		status = "disabled";
>  	};
> 
> +	qos_emmc: qos@ffa58000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa58000 0x0 0x20>;
> +	};
> +
>  	qos_gmac: qos@ffa5c000 {
>  		compatible = "syscon";
>  		reg = <0x0 0xffa5c000 0x0 0x20>;
> @@ -823,6 +829,11 @@
>  			};
> 
>  			/* These power domains are grouped by VD_LOGIC */
> +			pd_emmc@RK3399_PD_EMMC {
> +				reg = <RK3399_PD_EMMC>;
> +				clocks = <&cru ACLK_EMMC>;
> +				pm_qos = <&qos_emmc>;
> +			};
>  			pd_gmac@RK3399_PD_GMAC {
>  				reg = <RK3399_PD_GMAC>;
>  				clocks = <&cru ACLK_GMAC>;


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Re: [PATCH v2 1/9] arm64: dts: rockchip: add eMMC's power domain support for rk3399

[Caesar Wang]

On 2016年11月14日 22:45, Heiko Stuebner wrote:
> Am Mittwoch, 9. November 2016, 21:21:53 CET schrieb Caesar Wang:
>> From: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>
>> Control power domain for eMMC via genpd to reduce power consumption.
>>
>> Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Authorship / Signed-off mismatch. From above suggest Ziyuan is the author
> while first Signed-off-by indicates Elaine as author. Please clarify.

I believe the Elaine is the first author. Sorry for this kind of 
question to brother you again. :(

-
Caesar
>
> Thanks
> Heiko
>
>> ---
>>
>> Changes in v2:
>> - Reviewed-on: https://chromium-review.googlesource.com/376558
>> - Verified on ChromeOS kernel4.4
>>
>>   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index cbb7f8b..b401176 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> @@ -269,6 +269,7 @@
>>   		#clock-cells = <0>;
>>   		phys = <&emmc_phy>;
>>   		phy-names = "phy_arasan";
>> +		power-domains = <&power RK3399_PD_EMMC>;
>>   		status = "disabled";
>>   	};
>>
>> @@ -690,6 +691,11 @@
>>   		status = "disabled";
>>   	};
>>
>> +	qos_emmc: qos@ffa58000 {
>> +		compatible = "syscon";
>> +		reg = <0x0 0xffa58000 0x0 0x20>;
>> +	};
>> +
>>   	qos_gmac: qos@ffa5c000 {
>>   		compatible = "syscon";
>>   		reg = <0x0 0xffa5c000 0x0 0x20>;
>> @@ -823,6 +829,11 @@
>>   			};
>>
>>   			/* These power domains are grouped by VD_LOGIC */
>> +			pd_emmc@RK3399_PD_EMMC {
>> +				reg = <RK3399_PD_EMMC>;
>> +				clocks = <&cru ACLK_EMMC>;
>> +				pm_qos = <&qos_emmc>;
>> +			};
>>   			pd_gmac@RK3399_PD_GMAC {
>>   				reg = <RK3399_PD_GMAC>;
>>   				clocks = <&cru ACLK_GMAC>;
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
caesar wang | software engineer | wxt-TNX95d0MmH73oGB3hsPCZA@public.gmane.org


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Re: [PATCH v2 1/9] arm64: dts: rockchip: add eMMC's power domain support for rk3399

[Heiko Stuebner]

Am Montag, 14. November 2016, 23:01:27 CET schrieb Caesar Wang:
> On 2016年11月14日 22:45, Heiko Stuebner wrote:
> > Am Mittwoch, 9. November 2016, 21:21:53 CET schrieb Caesar Wang:
> >> From: Ziyuan Xu <xzy.xu@rock-chips.com>
> >> 
> >> Control power domain for eMMC via genpd to reduce power consumption.
> >> 
> >> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
> >> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> > 
> > Authorship / Signed-off mismatch. From above suggest Ziyuan is the author
> > while first Signed-off-by indicates Elaine as author. Please clarify.
> 
> I believe the Elaine is the first author. Sorry for this kind of
> question to brother you again. :(

no problem :-) and thanks for the very fast reply.

Applied to my dts64 branch.


Thanks
Heiko

[PATCH v2 5/9] arm64: dts: rockchip: add backlight support for rk3399 evb board

[Caesar Wang]

From: Yakir Yang <ykk@rock-chips.com>

Add backlight node for evb board, perpare for panel device node.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3399-evb.dts | 40 +++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index 8e82497..c585e93 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -49,6 +49,46 @@
 	compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
 		     "google,rk3399evb-rev2";
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm0 0 25000 0>;
+		brightness-levels = <
+			  0   1   2   3   4   5   6   7
+			  8   9  10  11  12  13  14  15
+			 16  17  18  19  20  21  22  23
+			 24  25  26  27  28  29  30  31
+			 32  33  34  35  36  37  38  39
+			 40  41  42  43  44  45  46  47
+			 48  49  50  51  52  53  54  55
+			 56  57  58  59  60  61  62  63
+			 64  65  66  67  68  69  70  71
+			 72  73  74  75  76  77  78  79
+			 80  81  82  83  84  85  86  87
+			 88  89  90  91  92  93  94  95
+			 96  97  98  99 100 101 102 103
+			104 105 106 107 108 109 110 111
+			112 113 114 115 116 117 118 119
+			120 121 122 123 124 125 126 127
+			128 129 130 131 132 133 134 135
+			136 137 138 139 140 141 142 143
+			144 145 146 147 148 149 150 151
+			152 153 154 155 156 157 158 159
+			160 161 162 163 164 165 166 167
+			168 169 170 171 172 173 174 175
+			176 177 178 179 180 181 182 183
+			184 185 186 187 188 189 190 191
+			192 193 194 195 196 197 198 199
+			200 201 202 203 204 205 206 207
+			208 209 210 211 212 213 214 215
+			216 217 218 219 220 221 222 223
+			224 225 226 227 228 229 230 231
+			232 233 234 235 236 237 238 239
+			240 241 242 243 244 245 246 247
+			248 249 250 251 252 253 254 255>;
+		default-brightness-level = <200>;
+		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	};
+
 	clkin_gmac: external-gmac-clock {
 		compatible = "fixed-clock";
 		clock-frequency = <125000000>;
-- 
2.7.4

Re: [PATCH v2 5/9] arm64: dts: rockchip: add backlight support for rk3399 evb board

[Heiko Stuebner]

Am Mittwoch, 9. November 2016, 21:21:57 CET schrieb Caesar Wang:
> From: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> 
> Add backlight node for evb board, perpare for panel device node.
> 
> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

applied to my dts64 branch


Thanks
Heiko

[PATCH v2 6/9] arm64: dts: rockchip: introduce pclk_vio_grf in eDP device node

[Caesar Wang]

From: Yakir Yang <ykk@rock-chips.com>

The pclk_vio_grf supply power for VIO GRF IOs, if it is disabled, driver
would failed to operate the VIO GRF registers.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 6544910..74deb44 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1356,8 +1356,8 @@
 		compatible = "rockchip,rk3399-edp";
 		reg = <0x0 0xff970000 0x0 0x8000>;
 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
-		clock-names = "dp", "pclk";
+		clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
+		clock-names = "dp", "pclk", "grf";
 		resets = <&cru SRST_P_EDP_CTRL>;
 		reset-names = "dp";
 		rockchip,grf = <&grf>;
-- 
2.7.4

[PATCH v2 7/9] arm64: dts: rockchip: add pd_edp node for rk3399

[Caesar Wang]

From: zhangqing <zhangqing@rock-chips.com>

1. add pd node for RK3399 Soc
2. create power domain tree
3. add qos node for domain
4. add the pd support for edp

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 74deb44..09ebf4e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -835,6 +835,10 @@
 			};
 
 			/* These power domains are grouped by VD_LOGIC */
+			pd_edp@RK3399_PD_EDP {
+				reg = <RK3399_PD_EDP>;
+				clocks = <&cru PCLK_EDP_CTRL>;
+			};
 			pd_emmc@RK3399_PD_EMMC {
 				reg = <RK3399_PD_EMMC>;
 				clocks = <&cru ACLK_EMMC>;
@@ -1364,6 +1368,7 @@
 		status = "disabled";
 		pinctrl-names = "default";
 		pinctrl-0 = <&edp_hpd>;
+		power-domains = <&power RK3399_PD_EDP>;
 
 		ports {
 			#address-cells = <1>;
-- 
2.7.4

Re: [PATCH v2 7/9] arm64: dts: rockchip: add pd_edp node for rk3399

[Doug Anderson]

Caesar,

On Wed, Nov 9, 2016 at 5:21 AM, Caesar Wang <wxt@rock-chips.com> wrote:
> From: zhangqing <zhangqing@rock-chips.com>
>
> 1. add pd node for RK3399 Soc
> 2. create power domain tree
> 3. add qos node for domain

No step #3 since there doesn't appear to be a qos node for eDP.  Your
patch doesn't add one and I can't find one in the TRM.

> 4. add the pd support for edp
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
> Changes in v2: None
>
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 74deb44..09ebf4e 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -835,6 +835,10 @@
>                         };
>
>                         /* These power domains are grouped by VD_LOGIC */
> +                       pd_edp@RK3399_PD_EDP {
> +                               reg = <RK3399_PD_EDP>;
> +                               clocks = <&cru PCLK_EDP_CTRL>;

Are you sure that PCLK_EDP isn't needed as well?  After the super
hard-to-debug problems we just faced with the missing GMAC clock in
the power domains, I figure it's at least worth a check.  ;)

> +                       };
>                         pd_emmc@RK3399_PD_EMMC {
>                                 reg = <RK3399_PD_EMMC>;
>                                 clocks = <&cru ACLK_EMMC>;
> @@ -1364,6 +1368,7 @@
>                 status = "disabled";
>                 pinctrl-names = "default";
>                 pinctrl-0 = <&edp_hpd>;
> +               power-domains = <&power RK3399_PD_EDP>;
>
>                 ports {
>                         #address-cells = <1>;

Other than the question about the clock and the nits about the commit
message, this all looks fine to me.  Feel free to add my Reviewed-by
if you fix those things.


-Doug

[PATCH v2 2/9] arm64: dts: rockchip: add pd_sd power node for rk3399

[Caesar Wang]

From: zhangqing <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

1.add pd node for RK3399 Soc
2.create power domain tree
3.add qos node for domain
4.add the pd_sd consumers node

Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

Changes in v2:
- v1 on https://patchwork.kernel.org/patch/9322553/
- Reviewed-on: https://chromium-review.googlesource.com/386483
- Verified on ChromeOS kernel4.4

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b401176..e5b5b3d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -253,6 +253,7 @@
 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 		fifo-depth = <0x100>;
+		power-domains = <&power RK3399_PD_SD>;
 		status = "disabled";
 	};
 
@@ -691,6 +692,11 @@
 		status = "disabled";
 	};
 
+	qos_sd: qos@ffa74000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa74000 0x0 0x20>;
+	};
+
 	qos_emmc: qos@ffa58000 {
 		compatible = "syscon";
 		reg = <0x0 0xffa58000 0x0 0x20>;
@@ -839,6 +845,12 @@
 				clocks = <&cru ACLK_GMAC>;
 				pm_qos = <&qos_gmac>;
 			};
+			pd_sd@RK3399_PD_SD {
+				reg = <RK3399_PD_SD>;
+				clocks = <&cru HCLK_SDMMC>,
+					 <&cru SCLK_SDMMC>;
+				pm_qos = <&qos_sd>;
+			};
 			pd_vio@RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
 				#address-cells = <1>;
-- 
2.7.4

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Re: [PATCH v2 2/9] arm64: dts: rockchip: add pd_sd power node for rk3399

[Shawn Lin]

Hi Caesar,

On 2016/11/9 21:21, Caesar Wang wrote:
> From: zhangqing <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> 1.add pd node for RK3399 Soc
> 2.create power domain tree
> 3.add qos node for domain
> 4.add the pd_sd consumers node

I'm no sure if it is worth spliting out a seperated
patch as it looks to me that you was doing 4 things within
one patch, but anyway

Tested-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

>
> Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
>
> Changes in v2:
> - v1 on https://patchwork.kernel.org/patch/9322553/
> - Reviewed-on: https://chromium-review.googlesource.com/386483
> - Verified on ChromeOS kernel4.4
>
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index b401176..e5b5b3d 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -253,6 +253,7 @@
>  			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
>  		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
>  		fifo-depth = <0x100>;
> +		power-domains = <&power RK3399_PD_SD>;
>  		status = "disabled";
>  	};
>
> @@ -691,6 +692,11 @@
>  		status = "disabled";
>  	};
>
> +	qos_sd: qos@ffa74000 {
> +		compatible = "syscon";
> +		reg = <0x0 0xffa74000 0x0 0x20>;
> +	};
> +
>  	qos_emmc: qos@ffa58000 {
>  		compatible = "syscon";
>  		reg = <0x0 0xffa58000 0x0 0x20>;
> @@ -839,6 +845,12 @@
>  				clocks = <&cru ACLK_GMAC>;
>  				pm_qos = <&qos_gmac>;
>  			};
> +			pd_sd@RK3399_PD_SD {
> +				reg = <RK3399_PD_SD>;
> +				clocks = <&cru HCLK_SDMMC>,
> +					 <&cru SCLK_SDMMC>;
> +				pm_qos = <&qos_sd>;
> +			};
>  			pd_vio@RK3399_PD_VIO {
>  				reg = <RK3399_PD_VIO>;
>  				#address-cells = <1>;
>


-- 
Best Regards
Shawn Lin

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Re: [PATCH v2 2/9] arm64: dts: rockchip: add pd_sd power node for rk3399

[Heiko Stuebner]

Am Mittwoch, 9. November 2016, 21:21:54 CET schrieb Caesar Wang:
> From: zhangqing <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> 
> 1.add pd node for RK3399 Soc
> 2.create power domain tree
> 3.add qos node for domain
> 4.add the pd_sd consumers node
> 
> Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Applied to my dts64 branch after some tweaks to patch subject and commit 
message.

Thanks
Heiko
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[PATCH v2 3/9] arm64: dts: rockchip: add VOP and VOP iommu node for rk3399

[Caesar Wang]

From: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Add the core display-subsystem node and the two display controllers
available on the rk3399.

Signed-off-by: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 58 ++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index e5b5b3d..f1d289a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1290,6 +1290,64 @@
 		status = "disabled";
 	};
 
+	vopl: vop@ff8f0000 {
+		compatible = "rockchip,rk3399-vop-lit";
+		reg = <0x0 0xff8f0000 0x0 0x3efc>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
+		reset-names = "axi", "ahb", "dclk";
+		iommus = <&vopl_mmu>;
+		status = "disabled";
+
+		vopl_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	vopl_mmu: iommu@ff8f3f00 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff8f3f00 0x0 0x100>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vopl_mmu";
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
+	vopb: vop@ff900000 {
+		compatible = "rockchip,rk3399-vop-big";
+		reg = <0x0 0xff900000 0x0 0x3efc>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
+		reset-names = "axi", "ahb", "dclk";
+		iommus = <&vopb_mmu>;
+		status = "disabled";
+
+		vopb_out: port {
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+
+	vopb_mmu: iommu@ff903f00 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff903f00 0x0 0x100>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vopb_mmu";
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
+	display_subsystem: display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vopl_out>, <&vopb_out>;
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3399-pinctrl";
 		rockchip,grf = <&grf>;
-- 
2.7.4

Re: [PATCH v2 3/9] arm64: dts: rockchip: add VOP and VOP iommu node for rk3399

[Heiko Stuebner]

Am Mittwoch, 9. November 2016, 21:21:55 CET schrieb Caesar Wang:
> From: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> 
> Add the core display-subsystem node and the two display controllers
> available on the rk3399.
> 
> Signed-off-by: Mark Yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> 
> Changes in v2: None
> 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 58
> ++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e5b5b3d..f1d289a 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1290,6 +1290,64 @@
>  		status = "disabled";
>  	};
> 
> +	vopl: vop@ff8f0000 {
> +		compatible = "rockchip,rk3399-vop-lit";
> +		reg = <0x0 0xff8f0000 0x0 0x3efc>;
> +		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;

we're usig 4 irq elements nowadays to accomodate the pmus for separate
clusters, see 

https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?id=210bbd38bb88989ce19208f98e530ff0468f38bd

Same for the edp node.

Also, sadly the rockchip drm seems to need some tweaks still, as I wasn't
able to get any display output yet.

To make the vop at least compile I needed to forward-port
https://github.com/mmind/linux-rockchip/commit/05ad856e54fc1aa1939ad1057897036cedc7fb0b
https://github.com/mmind/linux-rockchip/commit/0edb1f7e1ac77437a17d7966121ee6e10ab5db67

[full branch is https://github.com/mmind/linux-rockchip/commits/tmp/testing_20161109 ]

but I'm not sure if I did that correctly yet and am also still seeing
nothing on the display and get iommu errors when starting X11


Heiko

> +		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
> +		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> +		resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
> +		reset-names = "axi", "ahb", "dclk";
> +		iommus = <&vopl_mmu>;
> +		status = "disabled";
> +
> +		vopl_out: port {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +
> +	vopl_mmu: iommu@ff8f3f00 {
> +		compatible = "rockchip,iommu";
> +		reg = <0x0 0xff8f3f00 0x0 0x100>;
> +		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "vopl_mmu";
> +		#iommu-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	vopb: vop@ff900000 {
> +		compatible = "rockchip,rk3399-vop-big";
> +		reg = <0x0 0xff900000 0x0 0x3efc>;
> +		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
> +		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> +		resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
> +		reset-names = "axi", "ahb", "dclk";
> +		iommus = <&vopb_mmu>;
> +		status = "disabled";
> +
> +		vopb_out: port {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +	};
> +
> +	vopb_mmu: iommu@ff903f00 {
> +		compatible = "rockchip,iommu";
> +		reg = <0x0 0xff903f00 0x0 0x100>;
> +		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "vopb_mmu";
> +		#iommu-cells = <0>;
> +		status = "disabled";
> +	};
> +
> +	display_subsystem: display-subsystem {
> +		compatible = "rockchip,display-subsystem";
> +		ports = <&vopl_out>, <&vopb_out>;
> +		status = "disabled";
> +	};
> +
>  	pinctrl: pinctrl {
>  		compatible = "rockchip,rk3399-pinctrl";
>  		rockchip,grf = <&grf>;


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Re: [PATCH v2 3/9] arm64: dts: rockchip: add VOP and VOP iommu node for rk3399

[Caesar Wang]

在 2016年11月15日 00:05, Heiko Stuebner 写道:
> Am Mittwoch, 9. November 2016, 21:21:55 CET schrieb Caesar Wang:
>> From: Mark Yao <mark.yao@rock-chips.com>
>>
>> Add the core display-subsystem node and the two display controllers
>> available on the rk3399.
>>
>> Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> ---
>>
>> Changes in v2: None
>>
>>   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 58
>> ++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e5b5b3d..f1d289a 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> @@ -1290,6 +1290,64 @@
>>   		status = "disabled";
>>   	};
>>
>> +	vopl: vop@ff8f0000 {
>> +		compatible = "rockchip,rk3399-vop-lit";
>> +		reg = <0x0 0xff8f0000 0x0 0x3efc>;
>> +		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> we're usig 4 irq elements nowadays to accomodate the pmus for separate
> clusters, see
>
> https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?id=210bbd38bb88989ce19208f98e530ff0468f38bd
>
> Same for the edp node.

Ah!  Sorry.

>
> Also, sadly the rockchip drm seems to need some tweaks still, as I wasn't
> able to get any display output yet.
>
> To make the vop at least compile I needed to forward-port
> https://github.com/mmind/linux-rockchip/commit/05ad856e54fc1aa1939ad1057897036cedc7fb0b
> https://github.com/mmind/linux-rockchip/commit/0edb1f7e1ac77437a17d7966121ee6e10ab5db67
>
> [full branch is https://github.com/mmind/linux-rockchip/commits/tmp/testing_20161109 ]

Pls allow me to have a look at it and bring up with ChromeOs, the 
upstream maybe miss some patches for upstream. (DRM or IOMMU or ....)
I will resend the other patches if  I bring up and show display with 
upstream  on 
https://github.com/Caesar-github/rockchip/commits/rk3399/tmp-test

-Caesar
> but I'm not sure if I did that correctly yet and am also still seeing
> nothing on the display and get iommu errors when starting X11
>
>
> Heiko
>
>> +		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
>> +		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
>> +		resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
>> +		reset-names = "axi", "ahb", "dclk";
>> +		iommus = <&vopl_mmu>;
>> +		status = "disabled";
>> +
>> +		vopl_out: port {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +	};
>> +
>> +	vopl_mmu: iommu@ff8f3f00 {
>> +		compatible = "rockchip,iommu";
>> +		reg = <0x0 0xff8f3f00 0x0 0x100>;
>> +		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
>> +		interrupt-names = "vopl_mmu";
>> +		#iommu-cells = <0>;
>> +		status = "disabled";
>> +	};
>> +
>> +	vopb: vop@ff900000 {
>> +		compatible = "rockchip,rk3399-vop-big";
>> +		reg = <0x0 0xff900000 0x0 0x3efc>;
>> +		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
>> +		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
>> +		resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
>> +		reset-names = "axi", "ahb", "dclk";
>> +		iommus = <&vopb_mmu>;
>> +		status = "disabled";
>> +
>> +		vopb_out: port {
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +		};
>> +	};
>> +
>> +	vopb_mmu: iommu@ff903f00 {
>> +		compatible = "rockchip,iommu";
>> +		reg = <0x0 0xff903f00 0x0 0x100>;
>> +		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
>> +		interrupt-names = "vopb_mmu";
>> +		#iommu-cells = <0>;
>> +		status = "disabled";
>> +	};
>> +
>> +	display_subsystem: display-subsystem {
>> +		compatible = "rockchip,display-subsystem";
>> +		ports = <&vopl_out>, <&vopb_out>;
>> +		status = "disabled";
>> +	};
>> +
>>   	pinctrl: pinctrl {
>>   		compatible = "rockchip,rk3399-pinctrl";
>>   		rockchip,grf = <&grf>;
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 4/9] arm64: dts: rockchip: add eDP device node for rk3399

[Caesar Wang]

From: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Add rk3399 eDP device node, and connect to VOP device node with
remote endpoint.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
(Caesar rebase the lastest and solve the conflict)

---

Changes in v2:
- Yakir posted the original patch on
- https://patchwork.kernel.org/patch/9191777

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 52 ++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index f1d289a..6544910 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1304,6 +1304,11 @@
 		vopl_out: port {
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			vopl_out_edp: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&edp_in_vopl>;
+			};
 		};
 	};
 
@@ -1330,6 +1335,11 @@
 		vopb_out: port {
 			#address-cells = <1>;
 			#size-cells = <0>;
+
+			vopb_out_edp: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&edp_in_vopb>;
+			};
 		};
 	};
 
@@ -1342,6 +1352,41 @@
 		status = "disabled";
 	};
 
+	edp: edp@ff970000 {
+		compatible = "rockchip,rk3399-edp";
+		reg = <0x0 0xff970000 0x0 0x8000>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		resets = <&cru SRST_P_EDP_CTRL>;
+		reset-names = "dp";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			edp_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+		};
+	};
+
 	display_subsystem: display-subsystem {
 		compatible = "rockchip,display-subsystem";
 		ports = <&vopl_out>, <&vopb_out>;
@@ -1469,6 +1514,13 @@
 			};
 		};
 
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins =
+					<4 23 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
 		gmac {
 			rgmii_pins: rgmii-pins {
 				rockchip,pins =
-- 
2.7.4

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[PATCH v2 8/9] arm64: dts: rockchip: support dwc3 USB for rk3399

[Caesar Wang]

From: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>

Add the dwc3 usb needed node information for rk3399.

Signed-off-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

Changes in v2:
- the original patches from brian posting on
  https://chromium-review.googlesource.com/343603

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 54 ++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 09ebf4e..3659c56 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -353,6 +353,60 @@
 		status = "disabled";
 	};
 
+	usbdrd3_0: usb@fe800000 {
+		compatible = "rockchip,rk3399-dwc3";
+		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk", "grf_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+		usbdrd_dwc3_0: dwc3@fe800000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe800000 0x0 0x100000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
+			dr_mode = "otg";
+			phys = <&tcphy0_usb3>;
+			phy-names = "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,xhci-slow-suspend-quirk;
+			status = "disabled";
+		};
+	};
+
+	usbdrd3_1: usb@fe900000 {
+		compatible = "rockchip,rk3399-dwc3";
+		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
+			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk", "grf_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+		usbdrd_dwc3_1: dwc3@fe900000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe900000 0x0 0x100000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+			dr_mode = "host";
+			phys = <&tcphy1_usb3>;
+			phy-names = "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,xhci-slow-suspend-quirk;
+			status = "disabled";
+		};
+	};
+
 	gic: interrupt-controller@fee00000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <4>;
-- 
2.7.4

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Re: [PATCH v2 8/9] arm64: dts: rockchip: support dwc3 USB for rk3399

[Brian Norris]

+ Felipe, Arnd, others

Hi Caesar,

On Wed, Nov 09, 2016 at 09:22:00PM +0800, Caesar Wang wrote:
> From: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> 
> Add the dwc3 usb needed node information for rk3399.
> 
> Signed-off-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Note that none of this can work yet (at least for host mode, which I've
been testing), because DWC3 still hasn't been patched for ARM64 support.
It's been 7+ months and multiple people have tried to patch the issue,
but nothing has been merged.

See for instance:

usb: dwc3: host: inherit dma configuration from parent dev
https://lkml.org/lkml/2016/4/25/813
https://lkml.org/lkml/2016/5/5/391

Thread was resurrected in September:
https://lkml.org/lkml/2016/9/1/715
but there's still no end in sight. Maybe the following is the latest
incarnation?

[PATCH v2 0/6] inherit dma configuration from parent dev
https://www.mail-archive.com/linux-usb-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg82369.html

I guess nothing prevents a valid device tree being merged here, but it's
severely limited by the above bug still, so I just wanted to call
attention to it.

(Let me guess: you've still been testing an internal non-upstream tree
that has this patched already, Caesar?)

> ---
> 
> Changes in v2:
> - the original patches from brian posting on
>   https://chromium-review.googlesource.com/343603
> 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 54 ++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 09ebf4e..3659c56 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -353,6 +353,60 @@
>  		status = "disabled";
>  	};
>  
> +	usbdrd3_0: usb@fe800000 {
> +		compatible = "rockchip,rk3399-dwc3";
> +		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
> +			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
> +		clock-names = "ref_clk", "suspend_clk",
> +			      "bus_clk", "grf_clk";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		status = "disabled";
> +		usbdrd_dwc3_0: dwc3@fe800000 {
> +			compatible = "snps,dwc3";
> +			reg = <0x0 0xfe800000 0x0 0x100000>;
> +			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dr_mode = "otg";
> +			phys = <&tcphy0_usb3>;
> +			phy-names = "usb3-phy";

The USB3/TypeC PHY won't probe without extcon support, and no rk3399
platforms have proper extcon support upstream AFAIK, right? Seems like
it'd be better to leave this phy property off for now, with the hope of
at least getting USB2 working. We can add it later once somebody proves
USB3 support upstream.

> +			phy_type = "utmi_wide";
> +			snps,dis_enblslpm_quirk;
> +			snps,dis-u2-freeclk-exists-quirk;
> +			snps,dis_u2_susphy_quirk;
> +			snps,dis-del-phy-power-chg-quirk;
> +			snps,xhci-slow-suspend-quirk;

This property isn't supported upstream. Seems like we should drop it for
now.

Same comments on the other DWC3 instance below, of course.

Brian

> +			status = "disabled";
> +		};
> +	};
> +
> +	usbdrd3_1: usb@fe900000 {
> +		compatible = "rockchip,rk3399-dwc3";
> +		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
> +			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
> +		clock-names = "ref_clk", "suspend_clk",
> +			      "bus_clk", "grf_clk";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		status = "disabled";
> +		usbdrd_dwc3_1: dwc3@fe900000 {
> +			compatible = "snps,dwc3";
> +			reg = <0x0 0xfe900000 0x0 0x100000>;
> +			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dr_mode = "host";
> +			phys = <&tcphy1_usb3>;
> +			phy-names = "usb3-phy";
> +			phy_type = "utmi_wide";
> +			snps,dis_enblslpm_quirk;
> +			snps,dis-u2-freeclk-exists-quirk;
> +			snps,dis_u2_susphy_quirk;
> +			snps,dis-del-phy-power-chg-quirk;
> +			snps,xhci-slow-suspend-quirk;
> +			status = "disabled";
> +		};
> +	};
> +
>  	gic: interrupt-controller@fee00000 {
>  		compatible = "arm,gic-v3";
>  		#interrupt-cells = <4>;
> -- 
> 2.7.4
> 

[PATCH v2 9/9] arm64: dts: rockchip: add the usb3 pd for rk3399

[Caesar Wang]

1. add pd node for RK3399 Soc
2. create power domain tree
3. add qos node for domain
4. add the pd support for usb3

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v2:
- Reviewed-on: https://chromium-review.googlesource.com/384280

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 3659c56..7480fa7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -376,6 +376,7 @@
 			snps,dis_u2_susphy_quirk;
 			snps,dis-del-phy-power-chg-quirk;
 			snps,xhci-slow-suspend-quirk;
+			power-domains = <&power RK3399_PD_USB3>;
 			status = "disabled";
 		};
 	};
@@ -403,6 +404,7 @@
 			snps,dis_u2_susphy_quirk;
 			snps,dis-del-phy-power-chg-quirk;
 			snps,xhci-slow-suspend-quirk;
+			power-domains = <&power RK3399_PD_USB3>;
 			status = "disabled";
 		};
 	};
@@ -746,6 +748,16 @@
 		status = "disabled";
 	};
 
+	qos_usb_otg0: qos@ffa70000 {
+		compatible = "syscon";
+		reg = <0x0 0xffa70000 0x0 0x20>;
+	};
+
+	qos_usb_otg1: qos@ffa70080 {
+		compatible = "syscon";
+		reg = <0x0 0xffa70080 0x0 0x20>;
+	};
+
 	qos_sd: qos@ffa74000 {
 		compatible = "syscon";
 		reg = <0x0 0xffa74000 0x0 0x20>;
@@ -909,6 +921,12 @@
 					 <&cru SCLK_SDMMC>;
 				pm_qos = <&qos_sd>;
 			};
+			pd_usb3@RK3399_PD_USB3 {
+				reg = <RK3399_PD_USB3>;
+				clocks = <&cru ACLK_USB3>;
+				pm_qos = <&qos_usb_otg0>,
+					 <&qos_usb_otg1>;
+			};
 			pd_vio@RK3399_PD_VIO {
 				reg = <RK3399_PD_VIO>;
 				#address-cells = <1>;
-- 
2.7.4