From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lee Jones Subject: Re: [PATCH v6 3/8] PWM: add pwm-stm32 DT bindings Date: Tue, 13 Dec 2016 11:11:37 +0000 Message-ID: <20161213111137.GW3625@dell.home> References: <1481292919-26587-1-git-send-email-benjamin.gaignard@st.com> <1481292919-26587-4-git-send-email-benjamin.gaignard@st.com> <20161212190205.b5t3x6i2o7igldlo@rob-hp-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: Content-Disposition: inline In-Reply-To: <20161212190205.b5t3x6i2o7igldlo@rob-hp-laptop> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rob Herring Cc: Benjamin Gaignard , mark.rutland-5wv7dgnIgG8@public.gmane.org, alexandre.torgue-qxv4g6HH51o@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, knaack.h-Mmb7MZpHnFY@public.gmane.org, lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org, pmeerw-jW+XmwGofnusTnJN9+BGXg@public.gmane.org, linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, fabrice.gasnier-qxv4g6HH51o@public.gmane.org, gerald.baeza-qxv4g6HH51o@public.gmane.org, arnaud.pouliquen-qxv4g6HH51o@public.gmane.org, linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linaro-kernel-cunTk1MwBs8s++Sfvej+rw@public.gmane.org, Benjamin Gaignard List-Id: devicetree@vger.kernel.org On Mon, 12 Dec 2016, Rob Herring wrote: > On Fri, Dec 09, 2016 at 03:15:14PM +0100, Benjamin Gaignard wrote: > > Define bindings for pwm-stm32 > > > > version 6: > > - change st,breakinput parameter format to make it usuable on stm32f7 too. > > > > version 2: > > - use parameters instead of compatible of handle the hardware configuration > > > > Signed-off-by: Benjamin Gaignard > > --- > > .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++++++++++++++++++++++ > > 1 file changed, 33 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt > > > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt > > new file mode 100644 > > index 0000000..866f222 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt > > @@ -0,0 +1,33 @@ > > +STMicroelectronics STM32 Timers PWM bindings > > + > > +Must be a sub-node of an STM32 Timers device tree node. > > +See ../mfd/stm32-timers.txt for details about the parent node. > > + > > +Required parameters: > > +- compatible: Must be "st,stm32-pwm". > > +- pinctrl-names: Set to "default". > > +- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. > > + For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt > > + > > +Optional parameters: > > +- st,breakinput: Arrays of three u32 to describe break input configurations. > > + "index" indicates on which break input the configuration should be applied. > > + "level" gives the active level (0=low or 1=high) for this configuration. > > + "filter" gives the filtering value to be applied. > > + > > +Example: > > + timers@40010000 { > > timer@... No, it should be timers. The 's' is intentional, since this parent (MFD) device houses 3 different types of timers. The "timer" node is a child of this one. > With that, > > Acked-by: Rob Herring > > > > + #address-cells = <1>; > > + #size-cells = <0>; > > + compatible = "st,stm32-timers"; > > + reg = <0x40010000 0x400>; > > + clocks = <&rcc 0 160>; > > + clock-names = "clk_int"; > > + > > + pwm { > > + compatible = "st,stm32-pwm"; > > + pinctrl-0 = <&pwm1_pins>; > > + pinctrl-names = "default"; > > + st,breakinput = <0 1 5>; > > + }; > > + }; -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html