From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 4/5] ARM: dts: sunxi: add dtsi file for V3s SoC Date: Tue, 10 Jan 2017 19:21:06 +0100 Message-ID: <20170110182106.7q7uduxxqbzg4squ@lukather> References: <20170103151629.19447-1-icenowy@aosc.xyz> <20170103151629.19447-5-icenowy@aosc.xyz> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="u34jqn6krwdnlmfo" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20170103151629.19447-5-icenowy-ymACFijhrKM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Chen-Yu Tsai , Stephen Boyd , Linus Walleij , linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org --u34jqn6krwdnlmfo Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Tue, Jan 03, 2017 at 11:16:28PM +0800, Icenowy Zheng wrote: > + uart0_pins_a: uart0@0 { > + pins = "PB8", "PB9"; > + function = "uart0"; > + bias-pull-up; Why do you need a pullup here? Looks good otherwise. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --u34jqn6krwdnlmfo--