[PATCH 0/4] Add support for the USB OTG function of Allwinner V3s

[PATCH 0/4] Add support for the USB OTG function of Allwinner V3s

[Icenowy Zheng]

Allwinner V3s SoC come with a USB OTG controller, which is a bind of a Mentor
Graphics MUSB Dual-role controller and a private USB PHY.

Both the MUSB and the USB PHY slightly changed. (The MUSB is similar to the
one in the popular SBC SoC H3).

Add support for them.

The device tree patches depends on my preivous patchset, but the phy and musb
patches are independent (the device tree patches depend on them).

The MUSB patch may be picked for use on H3.

The clock of the USB part seems to need some hack in the U-Boot, they are at
my WIP u-boot repo:
https://github.com/Icenowy/u-boot-1/tree/v3s .

Icenowy Zheng (4):
  phy: sun4i-usb: add support for V3s USB PHY
  musb: sunxi: add support for the variant in H3/V3s SoC
  ARM: dts: sunxi: add usb_otg and usbphy node for V3s SoC
  ARM: dts: sun8i: add OTG function to Lichee Pi Zero

 .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  1 +
 .../bindings/usb/allwinner,sun4i-a10-musb.txt      |  4 +--
 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts      | 10 +++++++
 arch/arm/boot/dts/sun8i-v3s.dtsi                   | 27 +++++++++++++++++
 drivers/phy/phy-sun4i-usb.c                        | 14 ++++++++-
 drivers/usb/musb/sunxi.c                           | 35 ++++++++++++++++++++--
 6 files changed, 86 insertions(+), 5 deletions(-)

-- 
2.11.0

[PATCH 1/4] phy: sun4i-usb: add support for V3s USB PHY

[Icenowy Zheng]

Allwinner V3s come with a USB PHY controller slightly different to other
SoCs, with only one PHY.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt |  1 +
 drivers/phy/phy-sun4i-usb.c                             | 14 +++++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 287150db6db4..e42334258185 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -10,6 +10,7 @@ Required properties:
   * allwinner,sun8i-a23-usb-phy
   * allwinner,sun8i-a33-usb-phy
   * allwinner,sun8i-h3-usb-phy
+  * allwinner,sun8i-v3s-usb-phy
   * allwinner,sun50i-a64-usb-phy
 - reg : a list of offset + length pairs
 - reg-names :
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index bf28a0fdd569..4102841a8ad2 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -99,6 +99,7 @@ enum sun4i_usb_phy_type {
 	sun6i_a31_phy,
 	sun8i_a33_phy,
 	sun8i_h3_phy,
+	sun8i_v3s_phy,
 	sun50i_a64_phy,
 };
 
@@ -188,7 +189,8 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
 	spin_lock_irqsave(&phy_data->reg_lock, flags);
 
 	if (phy_data->cfg->type == sun8i_a33_phy ||
-	    phy_data->cfg->type == sun50i_a64_phy) {
+	    phy_data->cfg->type == sun50i_a64_phy ||
+	    phy_data->cfg->type == sun8i_v3s_phy) {
 		/* A33 or A64 needs us to set phyctl to 0 explicitly */
 		writel(0, phyctl);
 	}
@@ -825,6 +827,15 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.enable_pmu_unk1 = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
+	.num_phys = 1,
+	.type = sun8i_v3s_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.enable_pmu_unk1 = true,
+};
+
 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.num_phys = 2,
 	.type = sun50i_a64_phy,
@@ -842,6 +853,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
 	{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
 	{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
+	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy",
 	  .data = &sun50i_a64_cfg},
 	{ },
-- 
2.11.0

Re: [PATCH 1/4] phy: sun4i-usb: add support for V3s USB PHY

[Maxime Ripard]

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On Tue, Jan 03, 2017 at 11:25:31PM +0800, Icenowy Zheng wrote:
> Allwinner V3s come with a USB PHY controller slightly different to other
> SoCs, with only one PHY.
> 
> Add support for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks,
Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 1/4] phy: sun4i-usb: add support for V3s USB PHY

[Kishon Vijay Abraham I]

On Friday 06 January 2017 07:26 PM, Maxime Ripard wrote:
> On Tue, Jan 03, 2017 at 11:25:31PM +0800, Icenowy Zheng wrote:
>> Allwinner V3s come with a USB PHY controller slightly different to other
>> SoCs, with only one PHY.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> 
> Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

merged, thanks!

-Kishon
> 
> Thanks,
> Maxime
> 
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[PATCH 2/4] musb: sunxi: add support for the variant in H3/V3s SoC

[Icenowy Zheng]

Allwinner H3/V3s features a variant of MUSB controller, which lacks one
endpoint.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 .../bindings/usb/allwinner,sun4i-a10-musb.txt      |  4 +--
 drivers/usb/musb/sunxi.c                           | 35 ++++++++++++++++++++--
 2 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
index 862cd7c79805..d9b42da016f3 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.txt
@@ -2,8 +2,8 @@ Allwinner sun4i A10 musb DRC/OTG controller
 -------------------------------------------
 
 Required properties:
- - compatible      : "allwinner,sun4i-a10-musb", "allwinner,sun6i-a31-musb"
-                     or "allwinner,sun8i-a33-musb"
+ - compatible      : "allwinner,sun4i-a10-musb", "allwinner,sun6i-a31-musb",
+                     "allwinner,sun8i-a33-musb" or "allwinner,sun8i-h3-musb"
  - reg             : mmio address range of the musb controller
  - clocks          : clock specifier for the musb controller ahb gate clock
  - reset           : reset specifier for the ahb reset (A31 and newer only)
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index d0be0eadd0d9..48ecb1580817 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -645,6 +645,20 @@ static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
 	MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
 };
 
+/* H3/V3s OTG supports only 4 endpoints */
+#define SUNXI_MUSB_MAX_EP_NUM_H3	5
+
+static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
+	MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
+	MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
+	MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
+};
+
 static struct musb_hdrc_config sunxi_musb_hdrc_config = {
 	.fifo_cfg       = sunxi_musb_mode_cfg,
 	.fifo_cfg_size  = ARRAY_SIZE(sunxi_musb_mode_cfg),
@@ -656,6 +670,18 @@ static struct musb_hdrc_config sunxi_musb_hdrc_config = {
 	.dma		= 0,
 };
 
+static struct musb_hdrc_config sunxi_musb_hdrc_config_h3 = {
+	.fifo_cfg       = sunxi_musb_mode_cfg_h3,
+	.fifo_cfg_size  = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
+	.multipoint	= true,
+	.dyn_fifo	= true,
+	.soft_con       = true,
+	.num_eps	= SUNXI_MUSB_MAX_EP_NUM_H3,
+	.ram_bits	= SUNXI_MUSB_RAM_BITS,
+	.dma		= 0,
+};
+
+
 static int sunxi_musb_probe(struct platform_device *pdev)
 {
 	struct musb_hdrc_platform_data	pdata;
@@ -698,7 +724,10 @@ static int sunxi_musb_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 	pdata.platform_ops	= &sunxi_musb_ops;
-	pdata.config		= &sunxi_musb_hdrc_config;
+	if (!of_device_is_compatible(np, "allwinner,sun8i-h3-musb"))
+		pdata.config = &sunxi_musb_hdrc_config;
+	else
+		pdata.config = &sunxi_musb_hdrc_config_h3;
 
 	glue->dev = &pdev->dev;
 	INIT_WORK(&glue->work, sunxi_musb_work);
@@ -710,7 +739,8 @@ static int sunxi_musb_probe(struct platform_device *pdev)
 	if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
 		set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
 
-	if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb")) {
+	if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
+	    of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
 		set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
 		set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
 	}
@@ -804,6 +834,7 @@ static const struct of_device_id sunxi_musb_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-musb", },
 	{ .compatible = "allwinner,sun6i-a31-musb", },
 	{ .compatible = "allwinner,sun8i-a33-musb", },
+	{ .compatible = "allwinner,sun8i-h3-musb", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, sunxi_musb_match);
-- 
2.11.0

Re: [PATCH 2/4] musb: sunxi: add support for the variant in H3/V3s SoC

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 419 bytes --]

On Tue, Jan 03, 2017 at 11:25:32PM +0800, Icenowy Zheng wrote:
> Allwinner H3/V3s features a variant of MUSB controller, which lacks one
> endpoint.
> 
> Add support for it.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks,
Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 2/4] musb: sunxi: add support for the variant in H3/V3s SoC

[Bin Liu]

On Fri, Jan 06, 2017 at 02:57:15PM +0100, Maxime Ripard wrote:
> On Tue, Jan 03, 2017 at 11:25:32PM +0800, Icenowy Zheng wrote:
> > Allwinner H3/V3s features a variant of MUSB controller, which lacks one
> > endpoint.
> > 
> > Add support for it.
> > 
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> 
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Applied. Thanks.
-Bin.

[PATCH 3/4] ARM: dts: sunxi: add usb_otg and usbphy node for V3s SoC

[Icenowy Zheng]

V3s SoC features a USB PHY controller and a MUSB OTG controller.

Add device nodes for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 084da7474afb..ebefc0fefef2 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -153,6 +153,33 @@
 			#size-cells = <0>;
 		};
 
+		usb_otg: usb@01c19000 {
+			compatible = "allwinner,sun8i-h3-musb";
+			reg = <0x01c19000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			status = "disabled";
+		};
+
+		usbphy: phy@01c19400 {
+			compatible = "allwinner,sun8i-v3s-usb-phy";
+			reg = <0x01c19400 0x2c>,
+			      <0x01c1a800 0x4>;
+			reg-names = "phy_ctrl",
+				    "pmu0";
+			clocks = <&ccu CLK_USB_PHY0>;
+			clock-names = "usb0_phy";
+			resets = <&ccu RST_USB_PHY0>;
+			reset-names = "usb0_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
 		ccu: clock@01c20000 {
 			compatible = "allwinner,sun8i-v3s-ccu";
 			reg = <0x01c20000 0x400>;
-- 
2.11.0

Re: [PATCH 3/4] ARM: dts: sunxi: add usb_otg and usbphy node for V3s SoC

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 383 bytes --]

On Tue, Jan 03, 2017 at 11:25:33PM +0800, Icenowy Zheng wrote:
> V3s SoC features a USB PHY controller and a MUSB OTG controller.
> 
> Add device nodes for them.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

This can be merged in your other DTSI patch.

Maxime

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Embedded Linux and Kernel engineering
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[PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Icenowy Zheng]

Lichee Pi Zero features a USB OTG port.

Add support for it.

Note: in order to use the Host mode, the board must be powered via the
+5V and GND pins.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 0099affc6ce3..3d9168cbaeca 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -71,3 +71,13 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
-- 
2.11.0

Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Bin Liu]

On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
> Lichee Pi Zero features a USB OTG port.
> 
> Add support for it.
> 
> Note: in order to use the Host mode, the board must be powered via the
> +5V and GND pins.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> index 0099affc6ce3..3d9168cbaeca 100644
> --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> @@ -71,3 +71,13 @@
>  	pinctrl-names = "default";
>  	status = "okay";
>  };
> +
> +&usb_otg {
> +	dr_mode = "otg";

Why not set this default mode in dtsi instead?

Regards,
-Bin.

> +	status = "okay";
> +};
> +
> +&usbphy {
> +	usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> -- 
> 2.11.0
> 

Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Icenowy Zheng]

11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
> On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
>>  Lichee Pi Zero features a USB OTG port.
>>
>>  Add support for it.
>>
>>  Note: in order to use the Host mode, the board must be powered via the
>>  +5V and GND pins.
>>
>>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>>  ---
>>   arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>>  diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
>>  index 0099affc6ce3..3d9168cbaeca 100644
>>  --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
>>  +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
>>  @@ -71,3 +71,13 @@
>>           pinctrl-names = "default";
>>           status = "okay";
>>   };
>>  +
>>  +&usb_otg {
>>  + dr_mode = "otg";
>
> Why not set this default mode in dtsi instead?
>
> Regards,
> -Bin.

There's possibly boards which do not have OTG functions.

Even the official CDR design of V3s uses the USB controller to
connect a UVC webcam to make the design a dual-cam design
(V3s itself has a CSI).

>
>>  + status = "okay";
>>  +};
>>  +
>>  +&usbphy {
>>  + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
>>  + status = "okay";
>>  +};
>>  --
>>  2.11.0

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Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Bin Liu]

On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> 
> 
> 11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
> > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
> >>  Lichee Pi Zero features a USB OTG port.
> >>
> >>  Add support for it.
> >>
> >>  Note: in order to use the Host mode, the board must be powered via the
> >>  +5V and GND pins.
> >>
> >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >>  ---
> >>   arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
> >>   1 file changed, 10 insertions(+)
> >>
> >>  diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> >>  index 0099affc6ce3..3d9168cbaeca 100644
> >>  --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> >>  +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> >>  @@ -71,3 +71,13 @@
> >>           pinctrl-names = "default";
> >>           status = "okay";
> >>   };
> >>  +
> >>  +&usb_otg {
> >>  + dr_mode = "otg";
> >
> > Why not set this default mode in dtsi instead?
> >
> > Regards,
> > -Bin.
> 
> There's possibly boards which do not have OTG functions.

That is board specific.

You'd better to define the default dr_mode which the musb _controller_
supports in the dtsi, and then override it in a specific board dts if
necessary.

Regards,
-Bin.

> 
> Even the official CDR design of V3s uses the USB controller to
> connect a UVC webcam to make the design a dual-cam design
> (V3s itself has a CSI).
> 
> >
> >>  + status = "okay";
> >>  +};
> >>  +
> >>  +&usbphy {
> >>  + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
> >>  + status = "okay";
> >>  +};
> >>  --
> >>  2.11.0

Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Icenowy Zheng]

12.01.2017, 04:08, "Bin Liu" <b-liu@ti.com>:
> On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
>>  11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
>>  > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
>>  >>  Lichee Pi Zero features a USB OTG port.
>>  >>
>>  >>  Add support for it.
>>  >>
>>  >>  Note: in order to use the Host mode, the board must be powered via the
>>  >>  +5V and GND pins.
>>  >>
>>  >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>>  >>  ---
>>  >>   arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
>>  >>   1 file changed, 10 insertions(+)
>>  >>
>>  >>  diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
>>  >>  index 0099affc6ce3..3d9168cbaeca 100644
>>  >>  --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
>>  >>  +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
>>  >>  @@ -71,3 +71,13 @@
>>  >>           pinctrl-names = "default";
>>  >>           status = "okay";
>>  >>   };
>>  >>  +
>>  >>  +&usb_otg {
>>  >>  + dr_mode = "otg";
>>  >
>>  > Why not set this default mode in dtsi instead?
>>  >
>>  > Regards,
>>  > -Bin.
>>
>>  There's possibly boards which do not have OTG functions.
>
> That is board specific.
>
> You'd better to define the default dr_mode which the musb _controller_
> supports in the dtsi, and then override it in a specific board dts if
> necessary.

Is there MUSB controllers which do not support a certain mode?

(I remembered my omap3-n900 which do not work under OTG mode...)

>
> Regards,
> -Bin.
>
>>  Even the official CDR design of V3s uses the USB controller to
>>  connect a UVC webcam to make the design a dual-cam design
>>  (V3s itself has a CSI).
>>
>>  >
>>  >>  + status = "okay";
>>  >>  +};
>>  >>  +
>>  >>  +&usbphy {
>>  >>  + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
>>  >>  + status = "okay";
>>  >>  +};
>>  >>  --
>>  >>  2.11.0

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Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Bin Liu]

On Thu, Jan 12, 2017 at 04:13:34AM +0800, Icenowy Zheng wrote:
> 
> 
> 12.01.2017, 04:08, "Bin Liu" <b-liu@ti.com>:
> > On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> >>  11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
> >>  > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
> >>  >>  Lichee Pi Zero features a USB OTG port.
> >>  >>
> >>  >>  Add support for it.
> >>  >>
> >>  >>  Note: in order to use the Host mode, the board must be powered via the
> >>  >>  +5V and GND pins.
> >>  >>
> >>  >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> >>  >>  ---
> >>  >>   arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
> >>  >>   1 file changed, 10 insertions(+)
> >>  >>
> >>  >>  diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> >>  >>  index 0099affc6ce3..3d9168cbaeca 100644
> >>  >>  --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> >>  >>  +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> >>  >>  @@ -71,3 +71,13 @@
> >>  >>           pinctrl-names = "default";
> >>  >>           status = "okay";
> >>  >>   };
> >>  >>  +
> >>  >>  +&usb_otg {
> >>  >>  + dr_mode = "otg";
> >>  >
> >>  > Why not set this default mode in dtsi instead?
> >>  >
> >>  > Regards,
> >>  > -Bin.
> >>
> >>  There's possibly boards which do not have OTG functions.
> >
> > That is board specific.
> >
> > You'd better to define the default dr_mode which the musb _controller_
> > supports in the dtsi, and then override it in a specific board dts if
> > necessary.
> 
> Is there MUSB controllers which do not support a certain mode?

I am not aware of any. That is why I recommended to set "otg" in dtsi,
then override it in board dts if a port is specically designed to
host-only or device-only mode.

> 
> (I remembered my omap3-n900 which do not work under OTG mode...)

I belive it is n900 board specific. omap3 itself doesn't have such
limitation, AFAIK.

Regards,
-Bin.

> 
> >
> > Regards,
> > -Bin.
> >
> >>  Even the official CDR design of V3s uses the USB controller to
> >>  connect a UVC webcam to make the design a dual-cam design
> >>  (V3s itself has a CSI).
> >>
> >>  >
> >>  >>  + status = "okay";
> >>  >>  +};
> >>  >>  +
> >>  >>  +&usbphy {
> >>  >>  + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>;
> >>  >>  + status = "okay";
> >>  >>  +};
> >>  >>  --
> >>  >>  2.11.0

Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 1778 bytes --]

On Wed, Jan 11, 2017 at 02:08:11PM -0600, Bin Liu wrote:
> On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> > 
> > 
> > 11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
> > > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
> > >>  Lichee Pi Zero features a USB OTG port.
> > >>
> > >>  Add support for it.
> > >>
> > >>  Note: in order to use the Host mode, the board must be powered via the
> > >>  +5V and GND pins.
> > >>
> > >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> > >>  ---
> > >>   arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
> > >>   1 file changed, 10 insertions(+)
> > >>
> > >>  diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > >>  index 0099affc6ce3..3d9168cbaeca 100644
> > >>  --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > >>  +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > >>  @@ -71,3 +71,13 @@
> > >>           pinctrl-names = "default";
> > >>           status = "okay";
> > >>   };
> > >>  +
> > >>  +&usb_otg {
> > >>  + dr_mode = "otg";
> > >
> > > Why not set this default mode in dtsi instead?
> > >
> > > Regards,
> > > -Bin.
> > 
> > There's possibly boards which do not have OTG functions.
> 
> That is board specific.

Exactly, and this is why it should be done in the board DT.

The controller in the Allwinner SoCs do not handle directly the ID pin
and VBUS, but rather rely on a GPIO to do so.

So boards with OTG will need setup anyway, at least to tell which
GPIOs are used. There's no point in enforcing a default if it doesn't
work by default.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Bin Liu]

On Wed, Jan 11, 2017 at 10:06:38PM +0100, Maxime Ripard wrote:
> On Wed, Jan 11, 2017 at 02:08:11PM -0600, Bin Liu wrote:
> > On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> > > 
> > > 
> > > 11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
> > > > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
> > > >>  Lichee Pi Zero features a USB OTG port.
> > > >>
> > > >>  Add support for it.
> > > >>
> > > >>  Note: in order to use the Host mode, the board must be powered via the
> > > >>  +5V and GND pins.
> > > >>
> > > >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> > > >>  ---
> > > >>   arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
> > > >>   1 file changed, 10 insertions(+)
> > > >>
> > > >>  diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > >>  index 0099affc6ce3..3d9168cbaeca 100644
> > > >>  --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > >>  +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > >>  @@ -71,3 +71,13 @@
> > > >>           pinctrl-names = "default";
> > > >>           status = "okay";
> > > >>   };
> > > >>  +
> > > >>  +&usb_otg {
> > > >>  + dr_mode = "otg";
> > > >
> > > > Why not set this default mode in dtsi instead?
> > > >
> > > > Regards,
> > > > -Bin.
> > > 
> > > There's possibly boards which do not have OTG functions.
> > 
> > That is board specific.
> 
> Exactly, and this is why it should be done in the board DT.

I am just suggesting based on the common practice. If a .dtsi exists for
a family, the .dtsi describes the device and common properties for all
possible boards, and each board .dts adds or overrides its specific
implementation. Kernel has many devices/boards done in this way - define
the default dr_mode in .dtsi.

In this case, I suggest to set the common dr_mode in .dtsi, then each
board .dts only overrides it if the implementation is different. 

> 
> The controller in the Allwinner SoCs do not handle directly the ID pin
> and VBUS, but rather rely on a GPIO to do so.
> 
> So boards with OTG will need setup anyway, at least to tell which
> GPIOs are used. There's no point in enforcing a default if it doesn't
> work by default.

Then define a default which supposes to work for most boards.

Why I suggest this, is because defining a default dr_mode which works
for most cases in dtsi could prevent a little surprise in MUSB function.
If someone designs a new board but forgets to define dr_mode in the new
board DT, the MUSB driver will default to org mode, which might not be
intended.

Regards,
-Bin.

Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Maxime Ripard]

[-- Attachment #1.1: Type: text/plain, Size: 3329 bytes --]

Hi Bin,

On Thu, Jan 12, 2017 at 08:50:14AM -0600, Bin Liu wrote:
> On Wed, Jan 11, 2017 at 10:06:38PM +0100, Maxime Ripard wrote:
> > On Wed, Jan 11, 2017 at 02:08:11PM -0600, Bin Liu wrote:
> > > On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> > > > 
> > > > 
> > > > 11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
> > > > > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
> > > > >>  Lichee Pi Zero features a USB OTG port.
> > > > >>
> > > > >>  Add support for it.
> > > > >>
> > > > >>  Note: in order to use the Host mode, the board must be powered via the
> > > > >>  +5V and GND pins.
> > > > >>
> > > > >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> > > > >>  ---
> > > > >>   arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
> > > > >>   1 file changed, 10 insertions(+)
> > > > >>
> > > > >>  diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > > >>  index 0099affc6ce3..3d9168cbaeca 100644
> > > > >>  --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > > >>  +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > > >>  @@ -71,3 +71,13 @@
> > > > >>           pinctrl-names = "default";
> > > > >>           status = "okay";
> > > > >>   };
> > > > >>  +
> > > > >>  +&usb_otg {
> > > > >>  + dr_mode = "otg";
> > > > >
> > > > > Why not set this default mode in dtsi instead?
> > > > >
> > > > > Regards,
> > > > > -Bin.
> > > > 
> > > > There's possibly boards which do not have OTG functions.
> > > 
> > > That is board specific.
> > 
> > Exactly, and this is why it should be done in the board DT.
> 
> I am just suggesting based on the common practice. If a .dtsi exists for
> a family, the .dtsi describes the device and common properties for all
> possible boards, and each board .dts adds or overrides its specific
> implementation. Kernel has many devices/boards done in this way - define
> the default dr_mode in .dtsi.
> 
> In this case, I suggest to set the common dr_mode in .dtsi, then each
> board .dts only overrides it if the implementation is different. 
> 
> > 
> > The controller in the Allwinner SoCs do not handle directly the ID pin
> > and VBUS, but rather rely on a GPIO to do so.
> > 
> > So boards with OTG will need setup anyway, at least to tell which
> > GPIOs are used. There's no point in enforcing a default if it doesn't
> > work by default.
> 
> Then define a default which supposes to work for most boards.
> 
> Why I suggest this, is because defining a default dr_mode which works
> for most cases in dtsi could prevent a little surprise in MUSB function.
> If someone designs a new board but forgets to define dr_mode in the new
> board DT, the MUSB driver will default to org mode, which might not be
> intended.

The point is that there is no sensible default. Some boards don't have
an ID pin and no VBUS (peripheral), some don't have an ID pin but VBUS
(host), and some have an ID pin but no controllable VBUS, some have an
ID pin and a controllable VBUS, but we have no idea which GPIOs are
used.

There's no way we can have something that works on most cases.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero

[Bin Liu]

On Thu, Jan 12, 2017 at 06:39:38PM +0100, Maxime Ripard wrote:
> Hi Bin,
> 
> On Thu, Jan 12, 2017 at 08:50:14AM -0600, Bin Liu wrote:
> > On Wed, Jan 11, 2017 at 10:06:38PM +0100, Maxime Ripard wrote:
> > > On Wed, Jan 11, 2017 at 02:08:11PM -0600, Bin Liu wrote:
> > > > On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> > > > > 
> > > > > 
> > > > > 11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
> > > > > > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
> > > > > >>  Lichee Pi Zero features a USB OTG port.
> > > > > >>
> > > > > >>  Add support for it.
> > > > > >>
> > > > > >>  Note: in order to use the Host mode, the board must be powered via the
> > > > > >>  +5V and GND pins.
> > > > > >>
> > > > > >>  Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> > > > > >>  ---
> > > > > >>   arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
> > > > > >>   1 file changed, 10 insertions(+)
> > > > > >>
> > > > > >>  diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > > > >>  index 0099affc6ce3..3d9168cbaeca 100644
> > > > > >>  --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > > > >>  +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > > > >>  @@ -71,3 +71,13 @@
> > > > > >>           pinctrl-names = "default";
> > > > > >>           status = "okay";
> > > > > >>   };
> > > > > >>  +
> > > > > >>  +&usb_otg {
> > > > > >>  + dr_mode = "otg";
> > > > > >
> > > > > > Why not set this default mode in dtsi instead?
> > > > > >
> > > > > > Regards,
> > > > > > -Bin.
> > > > > 
> > > > > There's possibly boards which do not have OTG functions.
> > > > 
> > > > That is board specific.
> > > 
> > > Exactly, and this is why it should be done in the board DT.
> > 
> > I am just suggesting based on the common practice. If a .dtsi exists for
> > a family, the .dtsi describes the device and common properties for all
> > possible boards, and each board .dts adds or overrides its specific
> > implementation. Kernel has many devices/boards done in this way - define
> > the default dr_mode in .dtsi.
> > 
> > In this case, I suggest to set the common dr_mode in .dtsi, then each
> > board .dts only overrides it if the implementation is different. 
> > 
> > > 
> > > The controller in the Allwinner SoCs do not handle directly the ID pin
> > > and VBUS, but rather rely on a GPIO to do so.
> > > 
> > > So boards with OTG will need setup anyway, at least to tell which
> > > GPIOs are used. There's no point in enforcing a default if it doesn't
> > > work by default.
> > 
> > Then define a default which supposes to work for most boards.
> > 
> > Why I suggest this, is because defining a default dr_mode which works
> > for most cases in dtsi could prevent a little surprise in MUSB function.
> > If someone designs a new board but forgets to define dr_mode in the new
> > board DT, the MUSB driver will default to org mode, which might not be
> > intended.
> 
> The point is that there is no sensible default. Some boards don't have
> an ID pin and no VBUS (peripheral), some don't have an ID pin but VBUS
> (host), and some have an ID pin but no controllable VBUS, some have an
> ID pin and a controllable VBUS, but we have no idea which GPIOs are
> used.
> 
> There's no way we can have something that works on most cases.

Ok, understood.

Regards,
-Bin.