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From: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
To: Maxime Ripard
	<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Michael Turquette
	<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
	Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register
Date: Tue, 24 Jan 2017 10:32:23 +0800	[thread overview]
Message-ID: <20170124023230.3990-5-wens@csie.org> (raw)
In-Reply-To: <20170124023230.3990-1-wens-jdAy2FN1RRM@public.gmane.org>

On the Allwinner A80 SoC, the PLL lock status indicators are grouped
together in a separate register, as opposed to being scattered in each
PLL's configuration register.

Add a flag to support this.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
 drivers/clk/sunxi-ng/ccu_common.c | 8 ++++++--
 drivers/clk/sunxi-ng/ccu_common.h | 2 ++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 51d4bac97ab3..3fd0c3331aff 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -25,13 +25,17 @@ static DEFINE_SPINLOCK(ccu_lock);
 
 void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
 {
+	void __iomem *addr;
 	u32 reg;
 
 	if (!lock)
 		return;
 
-	WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg,
-					   reg & lock, 100, 70000));
+	addr = common->base + common->reg;
+	if (common->features & CCU_FEATURE_LOCK_REG)
+		addr = common->base + common->lock_reg;
+
+	WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
 }
 
 int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index cdd69eb2e0b9..73d81dc58fc5 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -22,6 +22,7 @@
 #define CCU_FEATURE_FIXED_PREDIV	BIT(2)
 #define CCU_FEATURE_FIXED_POSTDIV	BIT(3)
 #define CCU_FEATURE_ALL_PREDIV		BIT(4)
+#define CCU_FEATURE_LOCK_REG		BIT(5)
 
 struct device_node;
 
@@ -57,6 +58,7 @@ struct device_node;
 struct ccu_common {
 	void __iomem	*base;
 	u16		reg;
+	u16		lock_reg;
 	u32		prediv;
 
 	unsigned long	features;
-- 
2.11.0

  parent reply	other threads:[~2017-01-24  2:32 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-24  2:32 [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Chen-Yu Tsai
     [not found] ` <20170124023230.3990-1-wens-jdAy2FN1RRM@public.gmane.org>
2017-01-24  2:32   ` [PATCH 01/11] clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers Chen-Yu Tsai
     [not found]     ` <20170124023230.3990-2-wens-jdAy2FN1RRM@public.gmane.org>
2017-01-26  9:55       ` Maxime Ripard
2017-01-26 11:22         ` Chen-Yu Tsai
2017-01-24  2:32   ` [PATCH 02/11] clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag Chen-Yu Tsai
2017-01-24  2:32   ` [PATCH 03/11] clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT Chen-Yu Tsai
2017-01-24  2:32   ` Chen-Yu Tsai [this message]
2017-01-26  9:57     ` [PATCH 04/11] clk: sunxi-ng: Support separately grouped PLL lock status register Maxime Ripard
2017-01-24  2:32   ` [PATCH 05/11] clk: sunxi-ng: Add A80 CCU Chen-Yu Tsai
     [not found]     ` <20170124023230.3990-6-wens-jdAy2FN1RRM@public.gmane.org>
2017-01-27 21:13       ` Rob Herring
2017-01-24  2:32   ` [PATCH 06/11] clk: sunxi-ng: Add A80 USB CCU Chen-Yu Tsai
     [not found]     ` <20170124023230.3990-7-wens-jdAy2FN1RRM@public.gmane.org>
2017-01-26 10:14       ` Maxime Ripard
2017-01-26 11:12         ` [linux-sunxi] " Chen-Yu Tsai
     [not found]           ` <CAGb2v66R+NtOQ_J-kQeawppvPUUxBd1n0BXD7p8H5JA6pwYDJQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-01-27  8:45             ` Maxime Ripard
2017-01-27 21:15       ` Rob Herring
2017-01-24  2:32   ` [PATCH 07/11] clk: sunxi-ng: Add A80 Display Engine CCU Chen-Yu Tsai
2017-01-26 10:39     ` Maxime Ripard
2017-01-26 11:20       ` Chen-Yu Tsai
     [not found]         ` <CAGb2v65QLAD4C27NoRHALO=2WzW=DC6OxwCCMhes-N+kWO3_kg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-01-27  8:58           ` Maxime Ripard
2017-01-27  9:26             ` Chen-Yu Tsai
     [not found]               ` <CAGb2v671951p7-QNJh_JHXqCPJMHso8EjER-mBt1sn8j+U+uHg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-01-27  9:42                 ` Maxime Ripard
2017-01-24  2:32   ` [PATCH 08/11] ARM: dts: sun8i-a23-q8-tablet: Drop pinmux setting for codec PA gpio Chen-Yu Tsai
     [not found]     ` <20170124023230.3990-9-wens-jdAy2FN1RRM@public.gmane.org>
2017-01-26 10:38       ` Maxime Ripard
2017-01-26 11:15         ` Chen-Yu Tsai
2017-01-24  2:32   ` [PATCH 09/11] ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h header Chen-Yu Tsai
     [not found]     ` <20170124023230.3990-10-wens-jdAy2FN1RRM@public.gmane.org>
2017-01-26 10:21       ` Maxime Ripard
2017-01-24  2:32   ` [PATCH 10/11] arm64: dts: allwinner: " Chen-Yu Tsai
     [not found]     ` <20170124023230.3990-11-wens-jdAy2FN1RRM@public.gmane.org>
2017-01-26 10:15       ` Maxime Ripard
2017-01-26 11:23         ` Chen-Yu Tsai
     [not found]           ` <CAGb2v66cQoPQzd6W1D8bZ5hSURfGP3icJjeoo1mNk2ccG9B2vw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-01-27  8:46             ` Maxime Ripard
2017-01-24  2:32   ` [PATCH 11/11] ARM: dts: sun9i: Switch to new clock bindings Chen-Yu Tsai
2017-01-24  6:03   ` [PATCH 00/11] clk: sunxi-ng: Add support for A80 CCUs Priit Laes

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