[PATCH 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[PATCH 00/21] net-next: stmmac: add dwmac-sun8i ethernet driver

[Corentin Labbe]

Hello

This patch series add the driver for dwmac-sun8i which handle the Ethernet MAC
present on Allwinner H3/A83T/A64 SoCs.

This driver is the continuation of the sun8i-emac driver.
During the development, it appeared that in fact the hardware was a modified
version of some dwmac.
So the driver is now written as a glue driver for stmmac.

It supports 10/100/1000 Mbit/s speed with half/full duplex.
It can use an internal PHY (MII 10/100) or an external PHY
via RGMII/RMII.

This patch series enable the driver only for the H3/A64 SoC since A83T
doesn't have the necessary clocks present in mainline.

The driver have been tested on the following boards:
- H3 Orange PI PC, BananaPI-M2+
- A64 Pine64, BananaPi-M64
- A83T BananaPI-M3

The first three patchs are some mandatory changes for letting dwmac-sun8i be used.
The following two patchs add the driver and its documentation.
The remaining are DT patch enabling it.

Regards
Corentin Labbe

Corentin Labbe (16):
  net-next: stmmac add optional init_phy function
  net-next: stmmac: export stmmac_set_mac_addr/stmmac_get_mac_addr
  net-next: stmmac: add optional setup function
  ARM: sun8i: dt: Add DT bindings documentation for Allwinner
    dwmac-sun8i
  net-next: stmmac: Add dwmac-sun8i
  ARM: dts: sun8i-h3: add dwmac-sun8i rgmii pins
  ARM: dts: sun8i: Enable dwmac-sun8i on the Orange Pi 2
  ARM: dts: sun8i: Enable dwmac-sun8i on the Orange PI One
  ARM: dts: sun8i: Enable dwmac-sun8i on the Orange Pi plus
  ARM: dts: sun8i: orangepi-pc-plus: Set EMAC activity LEDs to active
    high
  ARM64: dts: sun50i-a64: Add dt node for the syscon control module
  ARM64: dts: sun50i-a64: add dwmac-sun8i Ethernet driver
  ARM: dts: sun50i-a64: enable dwmac-sun8i on pine64
  ARM: dts: sun50i-a64: enable dwmac-sun8i on pine64 plus
  ARM: dts: sun50i-a64: enable dwmac-sun8i on the BananaPi M64
  ARM: sunxi: Enable dwmac-sun8i driver on multi_v7_defconfig

LABBE Corentin (5):
  ARM: dts: sun8i-h3: Add dt node for the syscon control module
  ARM: dts: sun8i-h3: add dwmac-sun8i ethernet driver
  ARM: dts: sun8i: Enable dwmac-sun8i on the Banana Pi M2+
  ARM: dts: sun8i: Enable dwmac-sun8i on the Orange PI PC
  ARM: sunxi: Enable dwmac-sun8i driver on sunxi_defconfig

 .../devicetree/bindings/net/dwmac-sun8i.txt        |  86 ++
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts    |  38 +
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts          |   8 +
 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts        |   8 +
 arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts    |   5 +
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts         |   8 +
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts       |  36 +
 arch/arm/boot/dts/sun8i-h3.dtsi                    |  42 +
 arch/arm/configs/multi_v7_defconfig                |   1 +
 arch/arm/configs/sunxi_defconfig                   |   1 +
 .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts |  14 +
 .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts  |  16 +-
 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts |  15 +
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      |  43 +
 drivers/net/ethernet/stmicro/stmmac/Kconfig        |  11 +
 drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 +
 drivers/net/ethernet/stmicro/stmmac/common.h       |   3 +
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c  | 892 +++++++++++++++++++++
 drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c    |   3 +-
 .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c   |   3 +
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |  45 +-
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   9 +-
 include/linux/stmmac.h                             |   4 +
 23 files changed, 1286 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

-- 
2.10.2

[PATCH 01/21] net-next: stmmac add optional init_phy function

[Corentin Labbe]

For dwmac-sun8i, some actions must be done for enabling attached PHY.
Thoses actions must be done after stmmac_probe_config_dt() and
at start of stmmac_init_phy().

The best way to handle that is to add an optional init_phy() function.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/net/ethernet/stmicro/stmmac/common.h      |  3 +++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 11 +++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 144fe84..daaafa9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -483,6 +483,9 @@ struct stmmac_ops {
 			     bool loopback);
 	void (*pcs_rane)(void __iomem *ioaddr, bool restart);
 	void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
+	/* optional function for powering/init PHY */
+	int (*init_phy)(struct net_device *ndev);
+	void (*uninit_phy)(struct net_device *ndev);
 };
 
 /* PTP and HW Timer helpers */
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 3cbe096..942efb7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -820,10 +820,18 @@ static int stmmac_init_phy(struct net_device *dev)
 	char bus_id[MII_BUS_ID_SIZE];
 	int interface = priv->plat->interface;
 	int max_speed = priv->plat->max_speed;
+	int ret;
+
 	priv->oldlink = 0;
 	priv->speed = SPEED_UNKNOWN;
 	priv->oldduplex = DUPLEX_UNKNOWN;
 
+	if (priv->hw->mac->init_phy) {
+		ret = priv->hw->mac->init_phy(dev);
+		if (ret)
+			return ret;
+	}
+
 	if (priv->plat->phy_node) {
 		phydev = of_phy_connect(dev, priv->plat->phy_node,
 					&stmmac_adjust_link, 0, interface);
@@ -1892,6 +1900,9 @@ static int stmmac_release(struct net_device *dev)
 		phy_disconnect(dev->phydev);
 	}
 
+	if (priv->hw->mac->uninit_phy)
+		priv->hw->mac->uninit_phy(dev);
+
 	netif_stop_queue(dev);
 
 	napi_disable(&priv->napi);
-- 
2.10.2

[PATCH 02/21] net-next: stmmac: export stmmac_set_mac_addr/stmmac_get_mac_addr

[Corentin Labbe]

Thoses symbol will be needed for the dwmac-sun8i ethernet driver.
For letting it to be build as module, they need to be exported.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
index e60bfca..0ab985c8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c
@@ -248,6 +248,7 @@ void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 	data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
 	writel(data, ioaddr + low);
 }
+EXPORT_SYMBOL_GPL(stmmac_set_mac_addr);
 
 /* Enable disable MAC RX/TX */
 void stmmac_set_mac(void __iomem *ioaddr, bool enable)
@@ -279,4 +280,4 @@ void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 	addr[4] = hi_addr & 0xff;
 	addr[5] = (hi_addr >> 8) & 0xff;
 }
-
+EXPORT_SYMBOL_GPL(stmmac_get_mac_addr);
-- 
2.10.2

[PATCH 03/21] net-next: stmmac: add optional setup function

[Corentin Labbe]

Instead of ading more ifthen login for adding a new mac_device_info
setup function, it is easier to add a function pointer to the function
needed.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++++++-
 include/linux/stmmac.h                            | 3 +++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 942efb7..319394e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3117,7 +3117,12 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
 	struct mac_device_info *mac;
 
 	/* Identify the MAC HW device */
-	if (priv->plat->has_gmac) {
+	if (priv->plat->setup) {
+		mac = priv->plat->setup(priv->ioaddr,
+					priv->plat->multicast_filter_bins,
+					priv->plat->unicast_filter_entries,
+					&priv->synopsys_id);
+	} else if (priv->plat->has_gmac) {
 		priv->dev->priv_flags |= IFF_UNICAST_FLT;
 		mac = dwmac1000_setup(priv->ioaddr,
 				      priv->plat->multicast_filter_bins,
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index fc273e9..95ee4c4 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -136,6 +136,9 @@ struct plat_stmmacenet_data {
 	void (*fix_mac_speed)(void *priv, unsigned int speed);
 	int (*init)(struct platform_device *pdev, void *priv);
 	void (*exit)(struct platform_device *pdev, void *priv);
+	struct mac_device_info *(*setup)(void __iomem *ioaddr, int mcbins,
+					 int perfect_uc_entries,
+					 int *synopsys_id);
 	void *bsp_priv;
 	struct clk *stmmac_clk;
 	struct clk *pclk;
-- 
2.10.2

Re: [PATCH 03/21] net-next: stmmac: add optional setup function

[Peter Korsgaard]

>>>>> "Corentin" == Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> writes:

 > Instead of ading more ifthen login for adding a new mac_device_info

s/login/logic/

-- 
Bye, Peter Korsgaard

Re: [PATCH 03/21] net-next: stmmac: add optional setup function

[Corentin Labbe]

On Thu, Feb 16, 2017 at 09:38:33PM +0100, Peter Korsgaard wrote:
> >>>>> "Corentin" == Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> writes:
> 
>  > Instead of ading more ifthen login for adding a new mac_device_info
> 
> s/login/logic/
> 
> -- 
> Bye, Peter Korsgaard

Thanks, will fix it.
Regards
Corentin Labbe

[PATCH 04/21] ARM: sun8i: dt: Add DT bindings documentation for Allwinner dwmac-sun8i

[Corentin Labbe]

This patch adds documentation for Device-Tree bindings for the
Allwinner dwmac-sun8i driver.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 .../devicetree/bindings/net/dwmac-sun8i.txt        | 86 ++++++++++++++++++++++
 1 file changed, 86 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt

diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
new file mode 100644
index 0000000..ac806c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,86 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: should be one of the following string:
+		"allwinner,sun8i-a83t-emac"
+		"allwinner,sun8i-h3-emac"
+		"allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: should be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+  - allwinner,sun8i-h3-system-controller
+  - allwinner,sun8i-a64-system-controller
+  - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. Default is 0)
+- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. Default is 0)
+Both delay properties does not have units, there are arbitrary value.
+The TX/RX clock delay chain settings are board specific and could be found
+in vendor FEX files.
+
+Optional properties for "allwinner,sun8i-h3-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with "allwinner,sun8i-h3-emac":
+- clocks: an extra phandle to the reference clock for the EPHY
+- resets: an extra phandle to the reset control for the EPHY
+
+Required properties for the system controller:
+- reg: address and length of the register for the device.
+- compatible: should be "syscon" and one of the following string:
+		"allwinner,sun8i-h3-system-controller"
+		"allwinner,sun8i-a64-system-controller"
+		"allwinner,sun8i-a83t-system-controller"
+
+Example:
+
+emac: ethernet@1c0b000 {
+	compatible = "allwinner,sun8i-h3-emac";
+	syscon = <&syscon>;
+	reg = <0x01c0b000 0x104>;
+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "macirq";
+	resets = <&ccu RST_BUS_EMAC>;
+	reset-names = "stmmaceth";
+	clocks = <&ccu CLK_BUS_EMAC>;
+	clock-names = "stmmaceth";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	phy = <&int_mii_phy>;
+	phy-mode = "mii";
+	allwinner,leds-active-low;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		int_mii_phy: ethernet-phy@1 {
+			reg = <1>;
+			clocks = <&ccu CLK_BUS_EPHY>;
+			resets = <&ccu RST_BUS_EPHY>;
+		};
+	};
+};
-- 
2.10.2

Re: [PATCH 04/21] ARM: sun8i: dt: Add DT bindings documentation for Allwinner dwmac-sun8i

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 3329 bytes --]

Hi,

On Thu, Feb 16, 2017 at 01:48:42PM +0100, Corentin Labbe wrote:
> This patch adds documentation for Device-Tree bindings for the
> Allwinner dwmac-sun8i driver.
> 
> Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  .../devicetree/bindings/net/dwmac-sun8i.txt        | 86 ++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> new file mode 100644
> index 0000000..ac806c6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> @@ -0,0 +1,86 @@
> +* Allwinner sun8i GMAC ethernet controller
> +
> +This device is a platform glue layer for stmmac.
> +Please see stmmac.txt for the other unchanged properties.
> +
> +Required properties:
> +- compatible: should be one of the following string:
> +		"allwinner,sun8i-a83t-emac"
> +		"allwinner,sun8i-h3-emac"
> +		"allwinner,sun50i-a64-emac"
> +- reg: address and length of the register for the device.
> +- interrupts: interrupt for the device
> +- interrupt-names: should be "macirq"
> +- clocks: A phandle to the reference clock for this device
> +- clock-names: should be "stmmaceth"
> +- resets: A phandle to the reset control for this device
> +- reset-names: should be "stmmaceth"
> +- phy-mode: See ethernet.txt
> +- phy-handle: See ethernet.txt
> +- #address-cells: shall be 1
> +- #size-cells: shall be 0
> +- syscon: A phandle to the syscon of the SoC with one of the following
> + compatible string:
> +  - allwinner,sun8i-h3-system-controller
> +  - allwinner,sun8i-a64-system-controller
> +  - allwinner,sun8i-a83t-system-controller
> +
> +Optional properties:
> +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. Default is 0)
> +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. Default is 0)
> +Both delay properties does not have units, there are arbitrary value.
> +The TX/RX clock delay chain settings are board specific and could be found
> +in vendor FEX files.
> +
> +Optional properties for "allwinner,sun8i-h3-emac":
> +- allwinner,leds-active-low: EPHY LEDs are active low
> +
> +Required child node of emac:
> +- mdio bus node: should be named mdio
> +
> +Required properties of the mdio node:
> +- #address-cells: shall be 1
> +- #size-cells: shall be 0
> +
> +The device node referenced by "phy" or "phy-handle" should be a child node
> +of the mdio node. See phy.txt for the generic PHY bindings.
> +
> +Required properties of the phy node with "allwinner,sun8i-h3-emac":
> +- clocks: an extra phandle to the reference clock for the EPHY
> +- resets: an extra phandle to the reset control for the EPHY
> +
> +Required properties for the system controller:
> +- reg: address and length of the register for the device.
> +- compatible: should be "syscon" and one of the following string:
> +		"allwinner,sun8i-h3-system-controller"
> +		"allwinner,sun8i-a64-system-controller"
> +		"allwinner,sun8i-a83t-system-controller"

This should be in a separate binding document.

What does it describe / represent?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 04/21] ARM: sun8i: dt: Add DT bindings documentation for Allwinner dwmac-sun8i

[Corentin Labbe]

On Thu, Feb 16, 2017 at 07:48:18PM +0100, Maxime Ripard wrote:
> Hi,
> 
> On Thu, Feb 16, 2017 at 01:48:42PM +0100, Corentin Labbe wrote:
> > This patch adds documentation for Device-Tree bindings for the
> > Allwinner dwmac-sun8i driver.
> > 
> > Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> >  .../devicetree/bindings/net/dwmac-sun8i.txt        | 86 ++++++++++++++++++++++
> >  1 file changed, 86 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > new file mode 100644
> > index 0000000..ac806c6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > @@ -0,0 +1,86 @@
> > +* Allwinner sun8i GMAC ethernet controller
> > +
> > +This device is a platform glue layer for stmmac.
> > +Please see stmmac.txt for the other unchanged properties.
> > +
> > +Required properties:
> > +- compatible: should be one of the following string:
> > +		"allwinner,sun8i-a83t-emac"
> > +		"allwinner,sun8i-h3-emac"
> > +		"allwinner,sun50i-a64-emac"
> > +- reg: address and length of the register for the device.
> > +- interrupts: interrupt for the device
> > +- interrupt-names: should be "macirq"
> > +- clocks: A phandle to the reference clock for this device
> > +- clock-names: should be "stmmaceth"
> > +- resets: A phandle to the reset control for this device
> > +- reset-names: should be "stmmaceth"
> > +- phy-mode: See ethernet.txt
> > +- phy-handle: See ethernet.txt
> > +- #address-cells: shall be 1
> > +- #size-cells: shall be 0
> > +- syscon: A phandle to the syscon of the SoC with one of the following
> > + compatible string:
> > +  - allwinner,sun8i-h3-system-controller
> > +  - allwinner,sun8i-a64-system-controller
> > +  - allwinner,sun8i-a83t-system-controller
> > +
> > +Optional properties:
> > +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. Default is 0)
> > +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. Default is 0)
> > +Both delay properties does not have units, there are arbitrary value.
> > +The TX/RX clock delay chain settings are board specific and could be found
> > +in vendor FEX files.
> > +
> > +Optional properties for "allwinner,sun8i-h3-emac":
> > +- allwinner,leds-active-low: EPHY LEDs are active low
> > +
> > +Required child node of emac:
> > +- mdio bus node: should be named mdio
> > +
> > +Required properties of the mdio node:
> > +- #address-cells: shall be 1
> > +- #size-cells: shall be 0
> > +
> > +The device node referenced by "phy" or "phy-handle" should be a child node
> > +of the mdio node. See phy.txt for the generic PHY bindings.
> > +
> > +Required properties of the phy node with "allwinner,sun8i-h3-emac":
> > +- clocks: an extra phandle to the reference clock for the EPHY
> > +- resets: an extra phandle to the reset control for the EPHY
> > +
> > +Required properties for the system controller:
> > +- reg: address and length of the register for the device.
> > +- compatible: should be "syscon" and one of the following string:
> > +		"allwinner,sun8i-h3-system-controller"
> > +		"allwinner,sun8i-a64-system-controller"
> > +		"allwinner,sun8i-a83t-system-controller"
> 
> This should be in a separate binding document.
> 
> What does it describe / represent?
> 
> Thanks,
> Maxime
> 

I agree, I will split it in two one for syscon, one for emac

Thanks
Corentin Labbe

Re: [PATCH 04/21] ARM: sun8i: dt: Add DT bindings documentation for Allwinner dwmac-sun8i

[Florian Fainelli]

On 02/16/2017 04:48 AM, Corentin Labbe wrote:
> This patch adds documentation for Device-Tree bindings for the
> Allwinner dwmac-sun8i driver.
> 
> Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  .../devicetree/bindings/net/dwmac-sun8i.txt        | 86 ++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> 
> diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> new file mode 100644
> index 0000000..ac806c6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> @@ -0,0 +1,86 @@
> +* Allwinner sun8i GMAC ethernet controller
> +
> +This device is a platform glue layer for stmmac.
> +Please see stmmac.txt for the other unchanged properties.
> +
> +Required properties:
> +- compatible: should be one of the following string:
> +		"allwinner,sun8i-a83t-emac"
> +		"allwinner,sun8i-h3-emac"
> +		"allwinner,sun50i-a64-emac"
> +- reg: address and length of the register for the device.
> +- interrupts: interrupt for the device
> +- interrupt-names: should be "macirq"
> +- clocks: A phandle to the reference clock for this device
> +- clock-names: should be "stmmaceth"
> +- resets: A phandle to the reset control for this device
> +- reset-names: should be "stmmaceth"
> +- phy-mode: See ethernet.txt
> +- phy-handle: See ethernet.txt
> +- #address-cells: shall be 1
> +- #size-cells: shall be 0
> +- syscon: A phandle to the syscon of the SoC with one of the following
> + compatible string:
> +  - allwinner,sun8i-h3-system-controller
> +  - allwinner,sun8i-a64-system-controller
> +  - allwinner,sun8i-a83t-system-controller
> +
> +Optional properties:
> +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. Default is 0)
> +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. Default is 0)

Delays should be specified in nanosecond units, and should not be a
value that maps directly to a HW register value, you need to convert the
property value into the appropriate register value.

> +Both delay properties does not have units, there are arbitrary value.
> +The TX/RX clock delay chain settings are board specific and could be found
> +in vendor FEX files.
> +
> +Optional properties for "allwinner,sun8i-h3-emac":
> +- allwinner,leds-active-low: EPHY LEDs are active low

Are you sure this is appropriate at the MAC node level and this is not
something that follows the PHY instead?

> +
> +Required child node of emac:
> +- mdio bus node: should be named mdio
> +
> +Required properties of the mdio node:
> +- #address-cells: shall be 1
> +- #size-cells: shall be 0
> +
> +The device node referenced by "phy" or "phy-handle" should be a child node
> +of the mdio node. See phy.txt for the generic PHY bindings.
> +
> +Required properties of the phy node with "allwinner,sun8i-h3-emac":
> +- clocks: an extra phandle to the reference clock for the EPHY

s/an extra/a phandle/

> +- resets: an extra phandle to the reset control for the EPHY
> +
> +Required properties for the system controller:
> +- reg: address and length of the register for the device.
> +- compatible: should be "syscon" and one of the following string:
> +		"allwinner,sun8i-h3-system-controller"
> +		"allwinner,sun8i-a64-system-controller"
> +		"allwinner,sun8i-a83t-system-controller"
> +
> +Example:
> +
> +emac: ethernet@1c0b000 {
> +	compatible = "allwinner,sun8i-h3-emac";
> +	syscon = <&syscon>;
> +	reg = <0x01c0b000 0x104>;
> +	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +	interrupt-names = "macirq";
> +	resets = <&ccu RST_BUS_EMAC>;
> +	reset-names = "stmmaceth";
> +	clocks = <&ccu CLK_BUS_EMAC>;
> +	clock-names = "stmmaceth";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	phy = <&int_mii_phy>;
> +	phy-mode = "mii";
> +	allwinner,leds-active-low;
> +	mdio: mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		int_mii_phy: ethernet-phy@1 {
> +			reg = <1>;
> +			clocks = <&ccu CLK_BUS_EPHY>;
> +			resets = <&ccu RST_BUS_EPHY>;
> +		};
> +	};
> +};
> 


-- 
Florian

Re: [PATCH 04/21] ARM: sun8i: dt: Add DT bindings documentation for Allwinner dwmac-sun8i

[Corentin Labbe]

On Thu, Feb 16, 2017 at 12:58:46PM -0800, Florian Fainelli wrote:
> On 02/16/2017 04:48 AM, Corentin Labbe wrote:
> > +
> > +Optional properties:
> > +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. Default is 0)
> > +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. Default is 0)
> 
> Delays should be specified in nanosecond units, and should not be a
> value that maps directly to a HW register value, you need to convert the
> property value into the appropriate register value.
> 

This question already raised multiple times in sun8i-emac development, I do not have any information on how to decode thoses values. (and so the comment below in documentation)
I will try to contact Allwinner for more details.

> > +Both delay properties does not have units, there are arbitrary value.
> > +The TX/RX clock delay chain settings are board specific and could be found
> > +in vendor FEX files.
> > +
> > +Optional properties for "allwinner,sun8i-h3-emac":
> > +- allwinner,leds-active-low: EPHY LEDs are active low
> 
> Are you sure this is appropriate at the MAC node level and this is not
> something that follows the PHY instead?
> 

As said by MoeIcenowy, an internal PHY is present. At early stage of development, wens tried to create a PHY driver for it, but finaly it was too much over complicated and with few interest to split in two.

> > +
> > +Required child node of emac:
> > +- mdio bus node: should be named mdio
> > +
> > +Required properties of the mdio node:
> > +- #address-cells: shall be 1
> > +- #size-cells: shall be 0
> > +
> > +The device node referenced by "phy" or "phy-handle" should be a child node
> > +of the mdio node. See phy.txt for the generic PHY bindings.
> > +
> > +Required properties of the phy node with "allwinner,sun8i-h3-emac":
> > +- clocks: an extra phandle to the reference clock for the EPHY
> 
> s/an extra/a phandle/
> 

Thanks, will fix

Regards
Corentin Labbe

[PATCH 05/21] net-next: stmmac: Add dwmac-sun8i

[Corentin Labbe]

The dwmac-sun8i is a heavy hacked version of stmmac hardware by
allwinner.
In fact the only common part is the descriptor management and the first
register function.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/net/ethernet/stmicro/stmmac/Kconfig        |  11 +
 drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 +
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c  | 892 +++++++++++++++++++++
 .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c   |   3 +
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |  27 +-
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   9 +-
 include/linux/stmmac.h                             |   1 +
 7 files changed, 941 insertions(+), 3 deletions(-)
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c

diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index cfbe363..85c0e41 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -145,6 +145,17 @@ config DWMAC_SUNXI
 	  This selects Allwinner SoC glue layer support for the
 	  stmmac device driver. This driver is used for A20/A31
 	  GMAC ethernet controller.
+
+config DWMAC_SUN8I
+	tristate "Allwinner sun8i GMAC support"
+	default ARCH_SUNXI
+	depends on OF && (ARCH_SUNXI || COMPILE_TEST)
+	---help---
+	  Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
+
+	  This selects Allwinner SoC glue layer support for the
+	  stmmac device driver. This driver is used for H3/A83T/A64
+	  EMAC ethernet controller.
 endif
 
 config STMMAC_PCI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 700c603..fd4937a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o
 obj-$(CONFIG_DWMAC_STI)		+= dwmac-sti.o
 obj-$(CONFIG_DWMAC_STM32)	+= dwmac-stm32.o
 obj-$(CONFIG_DWMAC_SUNXI)	+= dwmac-sunxi.o
+obj-$(CONFIG_DWMAC_SUN8I)	+= dwmac-sun8i.o
 obj-$(CONFIG_DWMAC_DWC_QOS_ETH)	+= dwmac-dwc-qos-eth.o
 obj-$(CONFIG_DWMAC_GENERIC)	+= dwmac-generic.o
 stmmac-platform-objs:= stmmac_platform.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
new file mode 100644
index 0000000..0951eb9
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -0,0 +1,892 @@
+/*
+ * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
+ *
+ * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_mdio.h>
+#include <linux/of_net.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regmap.h>
+#include <linux/stmmac.h>
+
+#include "stmmac.h"
+#include "stmmac_platform.h"
+
+struct emac_variant {
+	u32 default_syscon_value;
+	int internal_phy;
+	bool support_mii;
+	bool support_rmii;
+	bool support_rgmii;
+};
+
+struct sunxi_priv_data {
+	struct clk *tx_clk;
+	struct clk *ephy_clk;
+	struct regulator *regulator;
+	struct reset_control *rst_ephy;
+	const struct emac_variant *variant;
+	bool use_internal_phy;
+	struct regmap *regmap;
+};
+
+static const struct emac_variant emac_variant_h3 = {
+	.default_syscon_value = 0x58000,
+	.internal_phy = PHY_INTERFACE_MODE_MII,
+	.support_mii = true,
+	.support_rmii = true,
+	.support_rgmii = true
+};
+
+static const struct emac_variant emac_variant_a83t = {
+	.default_syscon_value = 0,
+	.internal_phy = 0,
+	.support_mii = true,
+	.support_rgmii = true
+};
+
+static const struct emac_variant emac_variant_a64 = {
+	.default_syscon_value = 0,
+	.internal_phy = 0,
+	.support_mii = true,
+	.support_rmii = true,
+	.support_rgmii = true
+};
+
+#define EMAC_BASIC_CTL0 0x00
+#define EMAC_BASIC_CTL1 0x04
+#define EMAC_INT_STA    0x08
+#define EMAC_INT_EN     0x0C
+#define EMAC_TX_CTL0    0x10
+#define EMAC_TX_CTL1    0x14
+#define EMAC_TX_FLOW_CTL        0x1C
+#define EMAC_TX_DESC_LIST 0x20
+#define EMAC_RX_CTL0    0x24
+#define EMAC_RX_CTL1    0x28
+#define EMAC_RX_DESC_LIST 0x34
+#define EMAC_RX_FRM_FLT 0x38
+#define EMAC_MDIO_CMD   0x48
+#define EMAC_MDIO_DATA  0x4C
+#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
+#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
+#define EMAC_TX_DMA_STA 0xB0
+#define EMAC_TX_CUR_DESC        0xB4
+#define EMAC_TX_CUR_BUF 0xB8
+#define EMAC_RX_DMA_STA 0xC0
+#define EMAC_RX_CUR_DESC        0xC4
+#define EMAC_RX_CUR_BUF 0xC8
+
+/* Used in EMAC_RX_FRM_FLT */
+#define EMAC_FRM_FLT_RXALL              BIT(0)
+#define EMAC_FRM_FLT_CTL                BIT(13)
+#define EMAC_FRM_FLT_MULTICAST          BIT(16)
+
+/* Used in RX_CTL1*/
+#define EMAC_RX_MD              BIT(1)
+#define EMAC_RX_TH_MASK		GENMASK(4, 5)
+#define EMAC_RX_TH_32		0
+#define EMAC_RX_TH_64		(0x1 << 4)
+#define EMAC_RX_TH_96		(0x2 << 4)
+#define EMAC_RX_TH_128		(0x3 << 4)
+#define EMAC_RX_DMA_EN  BIT(30)
+#define EMAC_RX_DMA_START       BIT(31)
+
+/* Used in TX_CTL1*/
+#define EMAC_TX_MD              BIT(1)
+#define EMAC_TX_NEXT_FRM        BIT(2)
+#define EMAC_TX_TH_MASK		GENMASK(8, 10)
+#define EMAC_TX_TH_64		0
+#define EMAC_TX_TH_128		(0x1 << 8)
+#define EMAC_TX_TH_192		(0x2 << 8)
+#define EMAC_TX_TH_256		(0x3 << 8)
+#define EMAC_TX_DMA_EN  BIT(30)
+#define EMAC_TX_DMA_START       BIT(31)
+
+/* Used in RX_CTL0 */
+#define EMAC_RX_RECEIVER_EN             BIT(31)
+#define EMAC_RX_DO_CRC BIT(27)
+#define EMAC_RX_FLOW_CTL_EN             BIT(16)
+
+/* Used in TX_CTL0 */
+#define EMAC_TX_TRANSMITTER_EN  BIT(31)
+
+/* Used in EMAC_TX_FLOW_CTL */
+#define EMAC_TX_FLOW_CTL_EN             BIT(0)
+
+/* Used in EMAC_INT_STA */
+#define EMAC_TX_INT             BIT(0)
+#define EMAC_TX_DMA_STOP_INT    BIT(1)
+#define EMAC_TX_BUF_UA_INT      BIT(2)
+#define EMAC_TX_TIMEOUT_INT     BIT(3)
+#define EMAC_TX_UNDERFLOW_INT   BIT(4)
+#define EMAC_TX_EARLY_INT       BIT(5)
+#define EMAC_RX_INT             BIT(8)
+#define EMAC_RX_BUF_UA_INT      BIT(9)
+#define EMAC_RX_DMA_STOP_INT    BIT(10)
+#define EMAC_RX_TIMEOUT_INT     BIT(11)
+#define EMAC_RX_OVERFLOW_INT    BIT(12)
+#define EMAC_RX_EARLY_INT       BIT(13)
+#define EMAC_RGMII_STA_INT      BIT(16)
+
+#define MAC_ADDR_TYPE_DST BIT(31)
+
+/* H3 specific bits for EPHY */
+#define H3_EPHY_ADDR_SHIFT	20
+#define H3_EPHY_LED_POL		BIT(17) /* 1: active low, 0: active high */
+#define H3_EPHY_SHUTDOWN	BIT(16) /* 1: shutdown, 0: power up */
+#define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
+
+/* H3/A64 specific bits */
+#define SYSCON_RMII_EN		BIT(13) /* 1: enable RMII (overrides EPIT) */
+
+/* Generic system control EMAC_CLK bits */
+#define SYSCON_ETXDC_MASK		GENMASK(2, 0)
+#define SYSCON_ETXDC_SHIFT		10
+#define SYSCON_ERXDC_MASK		GENMASK(4, 0)
+#define SYSCON_ERXDC_SHIFT		5
+/* EMAC PHY Interface Type */
+#define SYSCON_EPIT			BIT(2) /* 1: RGMII, 0: MII */
+#define SYSCON_ETCS_MASK		GENMASK(1, 0)
+#define SYSCON_ETCS_MII		0x0
+#define SYSCON_ETCS_EXT_GMII	0x1
+#define SYSCON_ETCS_INT_GMII	0x2
+#define SYSCON_EMAC_REG		0x30
+
+static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
+{
+	writel(0, ioaddr + EMAC_RX_CTL1);
+	writel(0, ioaddr + EMAC_TX_CTL1);
+	writel(0, ioaddr + EMAC_RX_FRM_FLT);
+	writel(0, ioaddr + EMAC_RX_DESC_LIST);
+	writel(0, ioaddr + EMAC_TX_DESC_LIST);
+	writel(0, ioaddr + EMAC_INT_EN);
+	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
+	return 0;
+}
+
+static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
+				 struct stmmac_dma_cfg *dma_cfg,
+				 u32 dma_tx, u32 dma_rx, int atds)
+{
+	/* write tx and rx descs*/
+	writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST);
+	writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST);
+
+	writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
+	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
+}
+
+static void sun8i_dwmac_dump_regs(void __iomem *ioaddr)
+{
+	int i;
+
+	pr_info(" DMA registers\n");
+	for (i = 0; i < 0xC8; i += 4) {
+		if (i == 0x32 || i == 0x3C)
+			continue;
+		pr_err("Reg 0x%x: 0x%08x\n", i, readl(ioaddr + i));
+	}
+}
+
+static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw)
+{
+	sun8i_dwmac_dump_regs(hw->pcsr);
+}
+
+static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr)
+{
+	writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
+}
+
+static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr)
+{
+	writel(0, ioaddr + EMAC_INT_EN);
+}
+
+static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr)
+{
+	u32 v;
+
+	v = readl(ioaddr + EMAC_TX_CTL0);
+	v |= EMAC_TX_TRANSMITTER_EN;
+	writel(v, ioaddr + EMAC_TX_CTL0);
+
+	v = readl(ioaddr + EMAC_TX_CTL1);
+	v |= EMAC_TX_DMA_START;
+	v |= EMAC_TX_DMA_EN;
+	writel(v, ioaddr + EMAC_TX_CTL1);
+}
+
+static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
+{
+	u32 v;
+
+	v = readl(ioaddr + EMAC_TX_CTL1);
+	v |= EMAC_TX_DMA_START;
+	v |= EMAC_TX_DMA_EN;
+	writel_relaxed(v, ioaddr + EMAC_TX_CTL1);
+}
+
+static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr)
+{
+	u32 v;
+
+	v = readl(ioaddr + EMAC_TX_CTL0);
+	v &= ~EMAC_TX_TRANSMITTER_EN;
+	writel(v, ioaddr + EMAC_TX_CTL0);
+
+	v = readl(ioaddr + EMAC_TX_CTL1);
+	v &= ~EMAC_TX_DMA_EN;
+	writel(v, ioaddr + EMAC_TX_CTL1);
+}
+
+static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr)
+{
+	u32 v;
+
+	v = readl(ioaddr + EMAC_RX_CTL0);
+	v |= EMAC_RX_RECEIVER_EN;
+	writel(v, ioaddr + EMAC_RX_CTL0);
+
+	v = readl(ioaddr + EMAC_RX_CTL1);
+	v |= EMAC_RX_DMA_START;
+	v |= EMAC_RX_DMA_EN;
+	writel(v, ioaddr + EMAC_RX_CTL1);
+}
+
+static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr)
+{
+	u32 v;
+
+	v = readl(ioaddr + EMAC_RX_CTL0);
+	v &= ~EMAC_RX_RECEIVER_EN;
+	writel(v, ioaddr + EMAC_RX_CTL0);
+
+	v = readl(ioaddr + EMAC_RX_CTL1);
+	v &= ~EMAC_RX_DMA_EN;
+	writel(v, ioaddr + EMAC_RX_CTL1);
+}
+
+static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
+				     struct stmmac_extra_stats *x)
+{
+	u32 v;
+	int ret = 0;
+
+	v = readl(ioaddr + EMAC_INT_STA);
+
+	if (v & EMAC_TX_INT) {
+		ret |= handle_tx;
+		x->tx_normal_irq_n++;
+	}
+
+	if (v & EMAC_TX_DMA_STOP_INT)
+		x->tx_process_stopped_irq++;
+
+	if (v & EMAC_TX_BUF_UA_INT)
+		x->tx_process_stopped_irq++;
+
+	if (v & EMAC_TX_TIMEOUT_INT)
+		ret |= tx_hard_error;
+
+	if (v & EMAC_TX_UNDERFLOW_INT) {
+		ret |= tx_hard_error;
+		x->tx_undeflow_irq++;
+	}
+
+	if (v & EMAC_TX_EARLY_INT)
+		x->tx_early_irq++;
+
+	if (v & EMAC_RX_INT) {
+		ret |= handle_rx;
+		x->rx_normal_irq_n++;
+	}
+
+	if (v & EMAC_RX_BUF_UA_INT)
+		x->rx_buf_unav_irq++;
+
+	if (v & EMAC_RX_DMA_STOP_INT)
+		x->rx_process_stopped_irq++;
+
+	if (v & EMAC_RX_TIMEOUT_INT)
+		ret |= tx_hard_error;
+
+	if (v & EMAC_RX_OVERFLOW_INT) {
+		ret |= tx_hard_error;
+		x->rx_overflow_irq++;
+	}
+
+	if (v & EMAC_RX_EARLY_INT)
+		x->rx_early_irq++;
+
+	if (v & EMAC_RGMII_STA_INT)
+		x->irq_rgmii_n++;
+
+	writel(v, ioaddr + EMAC_INT_STA);
+
+	return ret;
+}
+
+static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode,
+					   int rxmode, int rxfifosz)
+{
+	u32 v;
+
+	v = readl(ioaddr + EMAC_TX_CTL1);
+	if (txmode == SF_DMA_MODE) {
+		v |= EMAC_TX_MD;
+		/* Undocumented bit (called TX_NEXT_FRM in BSP), the original
+		 * comment is
+		 * "Operating on second frame increase the performance
+		 * especially when transmit store-and-forward is used."
+		 */
+		v |= EMAC_TX_NEXT_FRM;
+	} else {
+		v &= ~EMAC_TX_MD;
+		v &= ~EMAC_TX_TH_MASK;
+		if (txmode < 64)
+			v |= EMAC_TX_TH_64;
+		else if (txmode < 128)
+			v |= EMAC_TX_TH_128;
+		else if (txmode < 192)
+			v |= EMAC_TX_TH_192;
+		else if (txmode < 256)
+			v |= EMAC_TX_TH_256;
+	}
+	writel(v, ioaddr + EMAC_TX_CTL1);
+
+	v = readl(ioaddr + EMAC_RX_CTL1);
+	if (rxmode == SF_DMA_MODE) {
+		v |= EMAC_RX_MD;
+	} else {
+		v &= ~EMAC_RX_MD;
+		v &= ~EMAC_RX_TH_MASK;
+		if (rxmode < 32)
+			v |= EMAC_RX_TH_32;
+		else if (rxmode < 64)
+			v |= EMAC_RX_TH_64;
+		else if (rxmode < 96)
+			v |= EMAC_RX_TH_96;
+		else if (rxmode < 128)
+			v |= EMAC_RX_TH_128;
+	}
+	writel(v, ioaddr + EMAC_RX_CTL1);
+}
+
+static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
+	.reset = sun8i_dwmac_dma_reset,
+	.init = sun8i_dwmac_dma_init,
+	.dump_regs = sun8i_dwmac_dump_regs,
+	.dma_mode = sun8i_dwmac_dma_operation_mode,
+	.enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
+	.enable_dma_irq = sun8i_dwmac_enable_dma_irq,
+	.disable_dma_irq = sun8i_dwmac_disable_dma_irq,
+	.start_tx = sun8i_dwmac_dma_start_tx,
+	.stop_tx = sun8i_dwmac_dma_stop_tx,
+	.start_rx = sun8i_dwmac_dma_start_rx,
+	.stop_rx = sun8i_dwmac_dma_stop_rx,
+	.dma_interrupt = sun8i_dwmac_dma_interrupt,
+};
+
+static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+{
+	struct sunxi_priv_data *gmac = priv;
+	int ret;
+
+	if (gmac->regulator) {
+		ret = regulator_enable(gmac->regulator);
+		if (ret) {
+			dev_err(&pdev->dev, "Fail to enable regulator\n");
+			return ret;
+		}
+	}
+
+	ret = clk_prepare_enable(gmac->tx_clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Could not enable AHB clock\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 v;
+
+	v = (8 << 24);/* burst len */
+	writel(v, ioaddr + EMAC_BASIC_CTL1);
+}
+
+static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
+				      unsigned char *addr,
+				      unsigned int reg_n)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 v;
+
+	stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
+			    EMAC_MACADDR_LO(reg_n));
+	if (reg_n > 0) {
+		v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
+		v |= MAC_ADDR_TYPE_DST;
+		writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
+	}
+}
+
+static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
+				      unsigned char *addr,
+				      unsigned int reg_n)
+{
+	void __iomem *ioaddr = hw->pcsr;
+
+	stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
+			    EMAC_MACADDR_LO(reg_n));
+}
+
+/* caution this function must return non 0 to work */
+static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 v;
+
+	v = readl(ioaddr + EMAC_RX_CTL0);
+	v |= EMAC_RX_DO_CRC;
+	writel(v, ioaddr + EMAC_RX_CTL0);
+
+	return 1;
+}
+
+static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
+				   struct net_device *dev)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 v;
+	int i = 0;
+	struct netdev_hw_addr *ha;
+
+	v = readl(ioaddr + EMAC_RX_FRM_FLT);
+
+	v |= EMAC_FRM_FLT_CTL;
+
+	if (dev->flags & IFF_PROMISC) {
+		v = EMAC_FRM_FLT_RXALL;
+	} else if (dev->flags & IFF_ALLMULTI) {
+		v = EMAC_FRM_FLT_MULTICAST;
+	} else if (!netdev_mc_empty(dev)) {
+		netdev_for_each_mc_addr(ha, dev) {
+			i++;
+			sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
+		}
+	}
+
+	if (netdev_uc_count(dev) + i > hw->unicast_filter_entries) {
+		netdev_info(dev, "Too many address, switching to promiscuous\n");
+		v = EMAC_FRM_FLT_RXALL;
+	} else {
+		netdev_for_each_uc_addr(ha, dev) {
+			i++;
+			sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
+		}
+	}
+	writel(v, ioaddr + EMAC_RX_FRM_FLT);
+}
+
+static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
+				  unsigned int duplex,
+				  unsigned int fc, unsigned int pause_time)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 v;
+
+	v = readl(ioaddr + EMAC_RX_CTL0);
+	if (fc == FLOW_AUTO)
+		v |= EMAC_RX_FLOW_CTL_EN;
+	else
+		v &= ~EMAC_RX_FLOW_CTL_EN;
+	writel(v, ioaddr + EMAC_RX_CTL0);
+
+	v = readl(ioaddr + EMAC_TX_FLOW_CTL);
+	if (fc == FLOW_AUTO)
+		v |= EMAC_TX_FLOW_CTL_EN;
+	else
+		v &= ~EMAC_TX_FLOW_CTL_EN;
+	writel(v, ioaddr + EMAC_TX_FLOW_CTL);
+}
+
+static int sun8i_dwmac_reset(struct stmmac_priv *priv)
+{
+	u32 v;
+	int err;
+
+	v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
+	writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
+
+	err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
+				 !(v & 0x01), 100, 10000);
+
+	if (err) {
+		dev_err(priv->device, "EMAC reset timeout\n");
+		return -EFAULT;
+	}
+	return 0;
+}
+
+static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
+{
+	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+	struct device_node *node = priv->device->of_node;
+	int ret;
+	u32 reg, val;
+
+	reg = gmac->variant->default_syscon_value;
+
+	if (gmac->variant->internal_phy) {
+		if (!gmac->use_internal_phy) {
+			/* switch to external PHY interface */
+			reg &= ~H3_EPHY_SELECT;
+		} else {
+			reg |= H3_EPHY_SELECT;
+			reg &= ~H3_EPHY_SHUTDOWN;
+			dev_info(priv->device, "Select internal_phy %x\n", reg);
+
+			if (of_property_read_bool(priv->plat->phy_node,
+						  "allwinner,leds-active-low"))
+				reg |= H3_EPHY_LED_POL;
+			else
+				reg &= ~H3_EPHY_LED_POL;
+
+			ret = of_mdio_parse_addr(priv->device,
+						 priv->plat->phy_node);
+			if (ret < 0) {
+				dev_err(priv->device, "Could not parse MDIO addr\n");
+				return ret;
+			}
+			/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
+			 * address. No need to mask it again.
+			 */
+			reg |= ret << H3_EPHY_ADDR_SHIFT;
+		}
+	}
+
+	if (!of_property_read_u32(node, "allwinner,tx-delay", &val)) {
+		dev_info(priv->device, "set tx-delay to %x\n", val);
+		if (val <= SYSCON_ETXDC_MASK) {
+			reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT);
+			reg |= (val << SYSCON_ETXDC_SHIFT);
+		} else {
+			dev_warn(priv->device, "Invalid TX clock delay: %d\n",
+				 val);
+		}
+	}
+
+	if (!of_property_read_u32(node, "allwinner,rx-delay", &val)) {
+		dev_info(priv->device, "set rx-delay to %x\n", val);
+		if (val <= SYSCON_ERXDC_MASK) {
+			reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT);
+			reg |= (val << SYSCON_ERXDC_SHIFT);
+		} else {
+			dev_warn(priv->device, "Invalid RX clock delay: %d\n",
+				 val);
+		}
+	}
+
+	/* Clear interface mode bits */
+	reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
+	if (gmac->variant->support_rmii)
+		reg &= ~SYSCON_RMII_EN;
+
+	switch (priv->plat->interface) {
+	case PHY_INTERFACE_MODE_MII:
+		/* default */
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+		reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
+		break;
+	default:
+		dev_err(priv->device, "Unsupported interface mode: %s",
+			phy_modes(priv->plat->interface));
+		return -EINVAL;
+	}
+
+	regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
+
+	return 0;
+}
+
+static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
+{
+	u32 reg = gmac->variant->default_syscon_value;
+
+	regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
+}
+
+static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
+{
+	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+	int ret;
+
+	if (gmac->ephy_clk) {
+		ret = clk_prepare_enable(gmac->ephy_clk);
+		if (ret) {
+			dev_err(priv->device, "Cannot enable ephy\n");
+			return ret;
+		}
+	}
+
+	if (gmac->rst_ephy) {
+		ret = reset_control_deassert(gmac->rst_ephy);
+		if (ret) {
+			dev_err(priv->device, "Cannot deassert ephy\n");
+			clk_disable_unprepare(gmac->ephy_clk);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
+{
+	if (gmac->ephy_clk)
+		clk_disable_unprepare(gmac->ephy_clk);
+	if (gmac->rst_ephy)
+		reset_control_assert(gmac->rst_ephy);
+	return 0;
+}
+
+static int sun8i_power_phy(struct net_device *ndev)
+{
+	struct stmmac_priv *priv = netdev_priv(ndev);
+	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+	int ret;
+
+	ret = sun8i_dwmac_power_internal_phy(priv);
+	if (ret)
+		return ret;
+
+	ret = sun8i_dwmac_set_syscon(priv);
+	if (ret)
+		goto error_phy;
+
+	ret = sun8i_dwmac_reset(priv);
+	if (ret)
+		goto error_phy;
+	return 0;
+
+error_phy:
+	sun8i_dwmac_unset_syscon(gmac);
+	sun8i_dwmac_unpower_internal_phy(gmac);
+	return ret;
+}
+
+static void sun8i_unpower_phy(struct net_device *ndev)
+{
+	struct stmmac_priv *priv = netdev_priv(ndev);
+	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+
+	sun8i_dwmac_unset_syscon(gmac);
+	sun8i_dwmac_unpower_internal_phy(gmac);
+}
+
+static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+{
+	struct sunxi_priv_data *gmac = priv;
+
+	clk_disable_unprepare(gmac->tx_clk);
+
+	if (gmac->regulator)
+		regulator_disable(gmac->regulator);
+}
+
+static const struct stmmac_ops sun8i_dwmac_ops = {
+	.core_init = sun8i_dwmac_core_init,
+	.dump_regs = sun8i_dwmac_dump_mac_regs,
+	.rx_ipc = sun8i_dwmac_rx_ipc_enable,
+	.set_filter = sun8i_dwmac_set_filter,
+	.flow_ctrl = sun8i_dwmac_flow_ctrl,
+	.set_umac_addr = sun8i_dwmac_set_umac_addr,
+	.get_umac_addr = sun8i_dwmac_get_umac_addr,
+	.init_phy = sun8i_power_phy,
+	.uninit_phy = sun8i_unpower_phy,
+};
+
+static struct mac_device_info *sun8i_dwmac_setup(void __iomem *ioaddr,
+						 int mcbins,
+						 int perfect_uc_entries,
+						 int *synopsys_id)
+{
+	struct mac_device_info *mac;
+
+	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
+	if (!mac)
+		return NULL;
+
+	mac->pcsr = ioaddr;
+	mac->mac = &sun8i_dwmac_ops;
+	mac->dma = &sun8i_dwmac_dma_ops;
+
+	mac->link.port = 0;
+	mac->link.duplex = BIT(0);
+	mac->link.speed = 1;
+	mac->mii.addr = EMAC_MDIO_CMD;
+	mac->mii.data = EMAC_MDIO_DATA;
+	mac->mii.reg_shift = 4;
+	mac->mii.reg_mask = GENMASK(8, 4);
+	mac->mii.addr_shift = 12;
+	mac->mii.addr_mask = GENMASK(16, 12);
+	mac->mii.clk_csr_shift = 20;
+	mac->mii.clk_csr_mask = GENMASK(22, 20);
+	mac->unicast_filter_entries = 8;
+
+	/* Synopsys Id is not available */
+	*synopsys_id = 0;
+
+	return mac;
+}
+
+static int sun8i_dwmac_probe(struct platform_device *pdev)
+{
+	struct plat_stmmacenet_data *plat_dat;
+	struct stmmac_resources stmmac_res;
+	struct sunxi_priv_data *gmac;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+	if (ret)
+		return ret;
+
+	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
+	if (IS_ERR(plat_dat))
+		return PTR_ERR(plat_dat);
+
+	gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
+	if (!gmac)
+		return -ENOMEM;
+
+	gmac->variant = of_device_get_match_data(&pdev->dev);
+	if (!gmac->variant) {
+		dev_err(&pdev->dev, "Missing sun8i-emac variant\n");
+		return -EINVAL;
+	}
+
+	gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
+	if (IS_ERR(gmac->tx_clk)) {
+		dev_err(dev, "could not get tx clock\n");
+		return PTR_ERR(gmac->tx_clk);
+	}
+
+	/* Optional regulator for PHY */
+	gmac->regulator = devm_regulator_get_optional(dev, "phy");
+	if (IS_ERR(gmac->regulator)) {
+		if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
+			return -EPROBE_DEFER;
+		dev_info(dev, "no regulator found\n");
+		gmac->regulator = NULL;
+	}
+
+	gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+						       "syscon");
+	if (IS_ERR(gmac->regmap)) {
+		ret = PTR_ERR(gmac->regmap);
+		dev_err(&pdev->dev, "unable to map SYSCON:%d\n", ret);
+		return ret;
+	}
+
+	plat_dat->interface = of_get_phy_mode(dev->of_node);
+	if (plat_dat->interface == gmac->variant->internal_phy) {
+		dev_info(&pdev->dev, "Will use internal PHY\n");
+		gmac->use_internal_phy = true;
+		gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
+		if (IS_ERR(gmac->ephy_clk)) {
+			ret = PTR_ERR(gmac->ephy_clk);
+			dev_err(&pdev->dev, "Cannot get EPHY clock err=%d\n",
+				ret);
+			return -EINVAL;
+		}
+
+		gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
+		if (IS_ERR(gmac->rst_ephy)) {
+			ret = PTR_ERR(gmac->rst_ephy);
+			if (ret == -EPROBE_DEFER)
+				return ret;
+			dev_err(&pdev->dev, "No EPHY reset control found %d\n",
+				ret);
+			return -EINVAL;
+		}
+	} else {
+		dev_info(&pdev->dev, "Will use external PHY\n");
+		gmac->use_internal_phy = false;
+	}
+
+	/* platform data specifying hardware features and callbacks.
+	 * hardware features were copied from Allwinner drivers.
+	 */
+	plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
+	plat_dat->tx_coe = 1;
+	plat_dat->has_sun8i = true;
+	plat_dat->bsp_priv = gmac;
+	plat_dat->init = sun8i_dwmac_init;
+	plat_dat->exit = sun8i_dwmac_exit;
+	plat_dat->setup = sun8i_dwmac_setup;
+
+	ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
+	if (ret)
+		return ret;
+
+	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
+	if (ret)
+		sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
+
+	return ret;
+}
+
+static const struct of_device_id sun8i_dwmac_match[] = {
+	{ .compatible = "allwinner,sun8i-h3-emac",
+		.data = &emac_variant_h3 },
+	{ .compatible = "allwinner,sun8i-a83t-emac",
+		.data = &emac_variant_a83t },
+	{ .compatible = "allwinner,sun50i-a64-emac",
+		.data = &emac_variant_a64 },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
+
+static struct platform_driver sun8i_dwmac_driver = {
+	.probe  = sun8i_dwmac_probe,
+	.remove = stmmac_pltfr_remove,
+	.driver = {
+		.name           = "sun8i-dwmac",
+		.pm		= &stmmac_pltfr_pm_ops,
+		.of_match_table = sun8i_dwmac_match,
+	},
+};
+module_platform_driver(sun8i_dwmac_driver);
+
+MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index 5ff6bc4..11db658 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -450,6 +450,9 @@ static void stmmac_ethtool_gregs(struct net_device *dev,
 		for (i = 0; i < 22; i++)
 			reg_space[i + 55] =
 			    readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
+	} else if (priv->plat->has_sun8i) {
+		for (i = 0; i < 0xC8 / 4; i++)
+			reg_space[i] = readl(priv->ioaddr + i * 4);
 	} else {
 		/* MAC registers */
 		for (i = 0; i < 12; i++)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 319394e..f473d54 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -177,6 +177,17 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 		else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 			priv->clk_csr = STMMAC_CSR_250_300M;
 	}
+
+	if (priv->plat->has_sun8i) {
+		if (clk_rate > 160000000)
+			priv->clk_csr = 0x03;
+		else if (clk_rate > 80000000)
+			priv->clk_csr = 0x02;
+		else if (clk_rate > 40000000)
+			priv->clk_csr = 0x01;
+		else
+			priv->clk_csr = 0;
+	}
 }
 
 static void print_pkt(unsigned char *buf, int len)
@@ -697,6 +708,10 @@ static void stmmac_adjust_link(struct net_device *dev)
 	if (phydev->link) {
 		u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 
+		/* disable loopback */
+		if (priv->plat->has_sun8i)
+			ctrl &= ~BIT(1);
+
 		/* Now we make sure that we can be in full duplex mode.
 		 * If not, we operate in half-duplex mode. */
 		if (phydev->duplex != priv->oldduplex) {
@@ -714,6 +729,8 @@ static void stmmac_adjust_link(struct net_device *dev)
 
 		if (phydev->speed != priv->speed) {
 			new_state = 1;
+			if (priv->plat->has_sun8i)
+				ctrl &= ~GENMASK(3, 2);
 			switch (phydev->speed) {
 			case 1000:
 				if (priv->plat->has_gmac ||
@@ -725,6 +742,8 @@ static void stmmac_adjust_link(struct net_device *dev)
 				    priv->plat->has_gmac4) {
 					ctrl |= priv->hw->link.port;
 					ctrl |= priv->hw->link.speed;
+				} else if (priv->plat->has_sun8i) {
+					ctrl |= 3 << 2;
 				} else {
 					ctrl &= ~priv->hw->link.port;
 				}
@@ -734,6 +753,8 @@ static void stmmac_adjust_link(struct net_device *dev)
 				    priv->plat->has_gmac4) {
 					ctrl |= priv->hw->link.port;
 					ctrl &= ~(priv->hw->link.speed);
+				} else if (priv->plat->has_sun8i) {
+					ctrl |= 2 << 2;
 				} else {
 					ctrl &= ~priv->hw->link.port;
 				}
@@ -1710,7 +1731,7 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
 	/* Enable the MAC Rx/Tx */
 	if (priv->synopsys_id >= DWMAC_CORE_4_00)
 		stmmac_dwmac4_set_mac(priv->ioaddr, true);
-	else
+	else if (!priv->plat->has_sun8i)
 		stmmac_set_mac(priv->ioaddr, true);
 
 	/* Set the HW DMA mode and the COE */
@@ -3142,6 +3163,10 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
 
 	priv->hw = mac;
 
+	/* dwmac-sun8i only work in chain mode */
+	if (priv->plat->has_sun8i)
+		chain_mode = 1;
+
 	/* To use the chained or ring mode */
 	if (priv->synopsys_id >= DWMAC_CORE_4_00) {
 		priv->hw->mode = &dwmac4_ring_mode_ops;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 433a842..92b7ca9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -160,6 +160,12 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
 			 struct device_node *np, struct device *dev)
 {
 	bool mdio = true;
+	static const struct of_device_id need_mdio_ids[] = {
+		{ .compatible = "snps,dwc-qos-ethernet-4.10" },
+		{ .compatible = "allwinner,sun8i-a83t-emac" },
+		{ .compatible = "allwinner,sun8i-h3-emac" },
+		{ .compatible = "allwinner,sun50i-a64-emac" },
+	};
 
 	/* If phy-handle property is passed from DT, use it as the PHY */
 	plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
@@ -176,8 +182,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
 		mdio = false;
 	}
 
-	/* exception for dwmac-dwc-qos-eth glue logic */
-	if (of_device_is_compatible(np, "snps,dwc-qos-ethernet-4.10")) {
+	if (of_match_node(need_mdio_ids, np)) {
 		plat->mdio_node = of_get_child_by_name(np, "mdio");
 	} else {
 		/**
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 95ee4c4..ddb9980 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -147,6 +147,7 @@ struct plat_stmmacenet_data {
 	struct reset_control *stmmac_rst;
 	struct stmmac_axi *axi;
 	int has_gmac4;
+	bool has_sun8i;
 	bool tso_en;
 	int mac_port_sel_speed;
 	bool en_tx_lpi_clockgating;
-- 
2.10.2

Re: [PATCH 05/21] net-next: stmmac: Add dwmac-sun8i

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 29233 bytes --]

Hi,

On Thu, Feb 16, 2017 at 01:48:43PM +0100, Corentin Labbe wrote:
> The dwmac-sun8i is a heavy hacked version of stmmac hardware by
> allwinner.
> In fact the only common part is the descriptor management and the first
> register function.
> 
> Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  drivers/net/ethernet/stmicro/stmmac/Kconfig        |  11 +
>  drivers/net/ethernet/stmicro/stmmac/Makefile       |   1 +
>  drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c  | 892 +++++++++++++++++++++
>  .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c   |   3 +
>  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |  27 +-
>  .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |   9 +-
>  include/linux/stmmac.h                             |   1 +
>  7 files changed, 941 insertions(+), 3 deletions(-)
>  create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> 
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> index cfbe363..85c0e41 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
> +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> @@ -145,6 +145,17 @@ config DWMAC_SUNXI
>  	  This selects Allwinner SoC glue layer support for the
>  	  stmmac device driver. This driver is used for A20/A31
>  	  GMAC ethernet controller.
> +
> +config DWMAC_SUN8I
> +	tristate "Allwinner sun8i GMAC support"
> +	default ARCH_SUNXI
> +	depends on OF && (ARCH_SUNXI || COMPILE_TEST)
> +	---help---
> +	  Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
> +
> +	  This selects Allwinner SoC glue layer support for the
> +	  stmmac device driver. This driver is used for H3/A83T/A64
> +	  EMAC ethernet controller.
>  endif
>  
>  config STMMAC_PCI
> diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
> index 700c603..fd4937a 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/Makefile
> +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o
>  obj-$(CONFIG_DWMAC_STI)		+= dwmac-sti.o
>  obj-$(CONFIG_DWMAC_STM32)	+= dwmac-stm32.o
>  obj-$(CONFIG_DWMAC_SUNXI)	+= dwmac-sunxi.o
> +obj-$(CONFIG_DWMAC_SUN8I)	+= dwmac-sun8i.o
>  obj-$(CONFIG_DWMAC_DWC_QOS_ETH)	+= dwmac-dwc-qos-eth.o
>  obj-$(CONFIG_DWMAC_GENERIC)	+= dwmac-generic.o
>  stmmac-platform-objs:= stmmac_platform.o
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> new file mode 100644
> index 0000000..0951eb9
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
> @@ -0,0 +1,892 @@
> +/*
> + * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
> + *
> + * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_mdio.h>
> +#include <linux/of_net.h>
> +#include <linux/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/regmap.h>
> +#include <linux/stmmac.h>
> +
> +#include "stmmac.h"
> +#include "stmmac_platform.h"
> +
> +struct emac_variant {
> +	u32 default_syscon_value;

Why do you need a default value? Can't you read it from the syscon
directly?

> +	int internal_phy;
> +	bool support_mii;
> +	bool support_rmii;
> +	bool support_rgmii;
> +};
> +
> +struct sunxi_priv_data {
> +	struct clk *tx_clk;
> +	struct clk *ephy_clk;
> +	struct regulator *regulator;
> +	struct reset_control *rst_ephy;
> +	const struct emac_variant *variant;
> +	bool use_internal_phy;
> +	struct regmap *regmap;
> +};
> +
> +static const struct emac_variant emac_variant_h3 = {
> +	.default_syscon_value = 0x58000,
> +	.internal_phy = PHY_INTERFACE_MODE_MII,
> +	.support_mii = true,
> +	.support_rmii = true,
> +	.support_rgmii = true
> +};
> +
> +static const struct emac_variant emac_variant_a83t = {
> +	.default_syscon_value = 0,
> +	.internal_phy = 0,
> +	.support_mii = true,
> +	.support_rgmii = true
> +};
> +
> +static const struct emac_variant emac_variant_a64 = {
> +	.default_syscon_value = 0,
> +	.internal_phy = 0,
> +	.support_mii = true,
> +	.support_rmii = true,
> +	.support_rgmii = true
> +};
> +
> +#define EMAC_BASIC_CTL0 0x00
> +#define EMAC_BASIC_CTL1 0x04
> +#define EMAC_INT_STA    0x08
> +#define EMAC_INT_EN     0x0C
> +#define EMAC_TX_CTL0    0x10
> +#define EMAC_TX_CTL1    0x14
> +#define EMAC_TX_FLOW_CTL        0x1C
> +#define EMAC_TX_DESC_LIST 0x20
> +#define EMAC_RX_CTL0    0x24
> +#define EMAC_RX_CTL1    0x28
> +#define EMAC_RX_DESC_LIST 0x34
> +#define EMAC_RX_FRM_FLT 0x38
> +#define EMAC_MDIO_CMD   0x48
> +#define EMAC_MDIO_DATA  0x4C
> +#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
> +#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
> +#define EMAC_TX_DMA_STA 0xB0
> +#define EMAC_TX_CUR_DESC        0xB4
> +#define EMAC_TX_CUR_BUF 0xB8
> +#define EMAC_RX_DMA_STA 0xC0
> +#define EMAC_RX_CUR_DESC        0xC4
> +#define EMAC_RX_CUR_BUF 0xC8
> +
> +/* Used in EMAC_RX_FRM_FLT */
> +#define EMAC_FRM_FLT_RXALL              BIT(0)
> +#define EMAC_FRM_FLT_CTL                BIT(13)
> +#define EMAC_FRM_FLT_MULTICAST          BIT(16)
> +
> +/* Used in RX_CTL1*/
> +#define EMAC_RX_MD              BIT(1)
> +#define EMAC_RX_TH_MASK		GENMASK(4, 5)
> +#define EMAC_RX_TH_32		0
> +#define EMAC_RX_TH_64		(0x1 << 4)
> +#define EMAC_RX_TH_96		(0x2 << 4)
> +#define EMAC_RX_TH_128		(0x3 << 4)
> +#define EMAC_RX_DMA_EN  BIT(30)
> +#define EMAC_RX_DMA_START       BIT(31)
> +
> +/* Used in TX_CTL1*/
> +#define EMAC_TX_MD              BIT(1)
> +#define EMAC_TX_NEXT_FRM        BIT(2)
> +#define EMAC_TX_TH_MASK		GENMASK(8, 10)
> +#define EMAC_TX_TH_64		0
> +#define EMAC_TX_TH_128		(0x1 << 8)
> +#define EMAC_TX_TH_192		(0x2 << 8)
> +#define EMAC_TX_TH_256		(0x3 << 8)
> +#define EMAC_TX_DMA_EN  BIT(30)
> +#define EMAC_TX_DMA_START       BIT(31)
> +
> +/* Used in RX_CTL0 */
> +#define EMAC_RX_RECEIVER_EN             BIT(31)
> +#define EMAC_RX_DO_CRC BIT(27)
> +#define EMAC_RX_FLOW_CTL_EN             BIT(16)
> +
> +/* Used in TX_CTL0 */
> +#define EMAC_TX_TRANSMITTER_EN  BIT(31)
> +
> +/* Used in EMAC_TX_FLOW_CTL */
> +#define EMAC_TX_FLOW_CTL_EN             BIT(0)
> +
> +/* Used in EMAC_INT_STA */
> +#define EMAC_TX_INT             BIT(0)
> +#define EMAC_TX_DMA_STOP_INT    BIT(1)
> +#define EMAC_TX_BUF_UA_INT      BIT(2)
> +#define EMAC_TX_TIMEOUT_INT     BIT(3)
> +#define EMAC_TX_UNDERFLOW_INT   BIT(4)
> +#define EMAC_TX_EARLY_INT       BIT(5)
> +#define EMAC_RX_INT             BIT(8)
> +#define EMAC_RX_BUF_UA_INT      BIT(9)
> +#define EMAC_RX_DMA_STOP_INT    BIT(10)
> +#define EMAC_RX_TIMEOUT_INT     BIT(11)
> +#define EMAC_RX_OVERFLOW_INT    BIT(12)
> +#define EMAC_RX_EARLY_INT       BIT(13)
> +#define EMAC_RGMII_STA_INT      BIT(16)
> +
> +#define MAC_ADDR_TYPE_DST BIT(31)
> +
> +/* H3 specific bits for EPHY */
> +#define H3_EPHY_ADDR_SHIFT	20
> +#define H3_EPHY_LED_POL		BIT(17) /* 1: active low, 0: active high */
> +#define H3_EPHY_SHUTDOWN	BIT(16) /* 1: shutdown, 0: power up */
> +#define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
> +
> +/* H3/A64 specific bits */
> +#define SYSCON_RMII_EN		BIT(13) /* 1: enable RMII (overrides EPIT) */
> +
> +/* Generic system control EMAC_CLK bits */
> +#define SYSCON_ETXDC_MASK		GENMASK(2, 0)
> +#define SYSCON_ETXDC_SHIFT		10
> +#define SYSCON_ERXDC_MASK		GENMASK(4, 0)
> +#define SYSCON_ERXDC_SHIFT		5
> +/* EMAC PHY Interface Type */
> +#define SYSCON_EPIT			BIT(2) /* 1: RGMII, 0: MII */
> +#define SYSCON_ETCS_MASK		GENMASK(1, 0)
> +#define SYSCON_ETCS_MII		0x0
> +#define SYSCON_ETCS_EXT_GMII	0x1
> +#define SYSCON_ETCS_INT_GMII	0x2
> +#define SYSCON_EMAC_REG		0x30
> +
> +static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
> +{
> +	writel(0, ioaddr + EMAC_RX_CTL1);
> +	writel(0, ioaddr + EMAC_TX_CTL1);
> +	writel(0, ioaddr + EMAC_RX_FRM_FLT);
> +	writel(0, ioaddr + EMAC_RX_DESC_LIST);
> +	writel(0, ioaddr + EMAC_TX_DESC_LIST);
> +	writel(0, ioaddr + EMAC_INT_EN);
> +	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
> +	return 0;
> +}
> +
> +static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
> +				 struct stmmac_dma_cfg *dma_cfg,
> +				 u32 dma_tx, u32 dma_rx, int atds)
> +{
> +	/* write tx and rx descs*/
> +	writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST);
> +	writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST);
> +
> +	writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
> +	writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
> +}
> +
> +static void sun8i_dwmac_dump_regs(void __iomem *ioaddr)
> +{
> +	int i;
> +
> +	pr_info(" DMA registers\n");

Logging this as pr_info is bad already...

> +	for (i = 0; i < 0xC8; i += 4) {
> +		if (i == 0x32 || i == 0x3C)
> +			continue;
> +		pr_err("Reg 0x%x: 0x%08x\n", i, readl(ioaddr + i));

... But this is worse.

Why do you need to do that? Can't you create a file in debugfs
instead?

> +	}
> +}
> +
> +static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw)
> +{
> +	sun8i_dwmac_dump_regs(hw->pcsr);
> +}
> +
> +static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr)
> +{
> +	writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
> +}
> +
> +static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr)
> +{
> +	writel(0, ioaddr + EMAC_INT_EN);
> +}
> +
> +static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr)
> +{
> +	u32 v;
> +
> +	v = readl(ioaddr + EMAC_TX_CTL0);
> +	v |= EMAC_TX_TRANSMITTER_EN;
> +	writel(v, ioaddr + EMAC_TX_CTL0);
> +
> +	v = readl(ioaddr + EMAC_TX_CTL1);
> +	v |= EMAC_TX_DMA_START;
> +	v |= EMAC_TX_DMA_EN;
> +	writel(v, ioaddr + EMAC_TX_CTL1);

This is a bit worrying. There's not a single lock in your driver,
while you have a significant number of read / modify / write.

Where is the locking handled?

> +}
> +
> +static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
> +{
> +	u32 v;
> +
> +	v = readl(ioaddr + EMAC_TX_CTL1);
> +	v |= EMAC_TX_DMA_START;
> +	v |= EMAC_TX_DMA_EN;
> +	writel_relaxed(v, ioaddr + EMAC_TX_CTL1);
> +}
> +
> +static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr)
> +{
> +	u32 v;
> +
> +	v = readl(ioaddr + EMAC_TX_CTL0);
> +	v &= ~EMAC_TX_TRANSMITTER_EN;
> +	writel(v, ioaddr + EMAC_TX_CTL0);
> +
> +	v = readl(ioaddr + EMAC_TX_CTL1);
> +	v &= ~EMAC_TX_DMA_EN;
> +	writel(v, ioaddr + EMAC_TX_CTL1);
> +}
> +
> +static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr)
> +{
> +	u32 v;
> +
> +	v = readl(ioaddr + EMAC_RX_CTL0);
> +	v |= EMAC_RX_RECEIVER_EN;
> +	writel(v, ioaddr + EMAC_RX_CTL0);
> +
> +	v = readl(ioaddr + EMAC_RX_CTL1);
> +	v |= EMAC_RX_DMA_START;
> +	v |= EMAC_RX_DMA_EN;
> +	writel(v, ioaddr + EMAC_RX_CTL1);
> +}
> +
> +static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr)
> +{
> +	u32 v;
> +
> +	v = readl(ioaddr + EMAC_RX_CTL0);
> +	v &= ~EMAC_RX_RECEIVER_EN;
> +	writel(v, ioaddr + EMAC_RX_CTL0);
> +
> +	v = readl(ioaddr + EMAC_RX_CTL1);
> +	v &= ~EMAC_RX_DMA_EN;
> +	writel(v, ioaddr + EMAC_RX_CTL1);
> +}
> +
> +static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
> +				     struct stmmac_extra_stats *x)
> +{
> +	u32 v;
> +	int ret = 0;
> +
> +	v = readl(ioaddr + EMAC_INT_STA);
> +
> +	if (v & EMAC_TX_INT) {
> +		ret |= handle_tx;
> +		x->tx_normal_irq_n++;
> +	}
> +
> +	if (v & EMAC_TX_DMA_STOP_INT)
> +		x->tx_process_stopped_irq++;
> +
> +	if (v & EMAC_TX_BUF_UA_INT)
> +		x->tx_process_stopped_irq++;
> +
> +	if (v & EMAC_TX_TIMEOUT_INT)
> +		ret |= tx_hard_error;
> +
> +	if (v & EMAC_TX_UNDERFLOW_INT) {
> +		ret |= tx_hard_error;
> +		x->tx_undeflow_irq++;
> +	}
> +
> +	if (v & EMAC_TX_EARLY_INT)
> +		x->tx_early_irq++;
> +
> +	if (v & EMAC_RX_INT) {
> +		ret |= handle_rx;
> +		x->rx_normal_irq_n++;
> +	}
> +
> +	if (v & EMAC_RX_BUF_UA_INT)
> +		x->rx_buf_unav_irq++;
> +
> +	if (v & EMAC_RX_DMA_STOP_INT)
> +		x->rx_process_stopped_irq++;
> +
> +	if (v & EMAC_RX_TIMEOUT_INT)
> +		ret |= tx_hard_error;
> +
> +	if (v & EMAC_RX_OVERFLOW_INT) {
> +		ret |= tx_hard_error;
> +		x->rx_overflow_irq++;
> +	}
> +
> +	if (v & EMAC_RX_EARLY_INT)
> +		x->rx_early_irq++;
> +
> +	if (v & EMAC_RGMII_STA_INT)
> +		x->irq_rgmii_n++;
> +
> +	writel(v, ioaddr + EMAC_INT_STA);
> +
> +	return ret;
> +}
> +
> +static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode,
> +					   int rxmode, int rxfifosz)
> +{
> +	u32 v;
> +
> +	v = readl(ioaddr + EMAC_TX_CTL1);
> +	if (txmode == SF_DMA_MODE) {
> +		v |= EMAC_TX_MD;
> +		/* Undocumented bit (called TX_NEXT_FRM in BSP), the original
> +		 * comment is
> +		 * "Operating on second frame increase the performance
> +		 * especially when transmit store-and-forward is used."
> +		 */
> +		v |= EMAC_TX_NEXT_FRM;
> +	} else {
> +		v &= ~EMAC_TX_MD;
> +		v &= ~EMAC_TX_TH_MASK;
> +		if (txmode < 64)
> +			v |= EMAC_TX_TH_64;
> +		else if (txmode < 128)
> +			v |= EMAC_TX_TH_128;
> +		else if (txmode < 192)
> +			v |= EMAC_TX_TH_192;
> +		else if (txmode < 256)
> +			v |= EMAC_TX_TH_256;
> +	}
> +	writel(v, ioaddr + EMAC_TX_CTL1);
> +
> +	v = readl(ioaddr + EMAC_RX_CTL1);
> +	if (rxmode == SF_DMA_MODE) {
> +		v |= EMAC_RX_MD;
> +	} else {
> +		v &= ~EMAC_RX_MD;
> +		v &= ~EMAC_RX_TH_MASK;
> +		if (rxmode < 32)
> +			v |= EMAC_RX_TH_32;
> +		else if (rxmode < 64)
> +			v |= EMAC_RX_TH_64;
> +		else if (rxmode < 96)
> +			v |= EMAC_RX_TH_96;
> +		else if (rxmode < 128)
> +			v |= EMAC_RX_TH_128;
> +	}
> +	writel(v, ioaddr + EMAC_RX_CTL1);
> +}
> +
> +static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
> +	.reset = sun8i_dwmac_dma_reset,
> +	.init = sun8i_dwmac_dma_init,
> +	.dump_regs = sun8i_dwmac_dump_regs,
> +	.dma_mode = sun8i_dwmac_dma_operation_mode,
> +	.enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
> +	.enable_dma_irq = sun8i_dwmac_enable_dma_irq,
> +	.disable_dma_irq = sun8i_dwmac_disable_dma_irq,
> +	.start_tx = sun8i_dwmac_dma_start_tx,
> +	.stop_tx = sun8i_dwmac_dma_stop_tx,
> +	.start_rx = sun8i_dwmac_dma_start_rx,
> +	.stop_rx = sun8i_dwmac_dma_stop_rx,
> +	.dma_interrupt = sun8i_dwmac_dma_interrupt,
> +};
> +
> +static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
> +{
> +	struct sunxi_priv_data *gmac = priv;
> +	int ret;
> +
> +	if (gmac->regulator) {
> +		ret = regulator_enable(gmac->regulator);
> +		if (ret) {
> +			dev_err(&pdev->dev, "Fail to enable regulator\n");
> +			return ret;
> +		}
> +	}
> +
> +	ret = clk_prepare_enable(gmac->tx_clk);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Could not enable AHB clock\n");

If that call fails, you leave the regulator (if there was any) enabled.

> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu)
> +{
> +	void __iomem *ioaddr = hw->pcsr;
> +	u32 v;
> +
> +	v = (8 << 24);/* burst len */
> +	writel(v, ioaddr + EMAC_BASIC_CTL1);

do you need an intermediate value? you should make a define for that
too.

> +}
> +
> +static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
> +				      unsigned char *addr,
> +				      unsigned int reg_n)
> +{
> +	void __iomem *ioaddr = hw->pcsr;
> +	u32 v;
> +
> +	stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
> +			    EMAC_MACADDR_LO(reg_n));
> +	if (reg_n > 0) {
> +		v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
> +		v |= MAC_ADDR_TYPE_DST;
> +		writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
> +	}
> +}
> +
> +static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
> +				      unsigned char *addr,
> +				      unsigned int reg_n)
> +{
> +	void __iomem *ioaddr = hw->pcsr;
> +
> +	stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
> +			    EMAC_MACADDR_LO(reg_n));
> +}
> +
> +/* caution this function must return non 0 to work */
> +static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
> +{
> +	void __iomem *ioaddr = hw->pcsr;
> +	u32 v;
> +
> +	v = readl(ioaddr + EMAC_RX_CTL0);
> +	v |= EMAC_RX_DO_CRC;
> +	writel(v, ioaddr + EMAC_RX_CTL0);
> +
> +	return 1;
> +}
> +
> +static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
> +				   struct net_device *dev)
> +{
> +	void __iomem *ioaddr = hw->pcsr;
> +	u32 v;
> +	int i = 0;
> +	struct netdev_hw_addr *ha;
> +
> +	v = readl(ioaddr + EMAC_RX_FRM_FLT);
> +
> +	v |= EMAC_FRM_FLT_CTL;
> +
> +	if (dev->flags & IFF_PROMISC) {
> +		v = EMAC_FRM_FLT_RXALL;
> +	} else if (dev->flags & IFF_ALLMULTI) {
> +		v = EMAC_FRM_FLT_MULTICAST;
> +	} else if (!netdev_mc_empty(dev)) {
> +		netdev_for_each_mc_addr(ha, dev) {
> +			i++;
> +			sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
> +		}
> +	}
> +
> +	if (netdev_uc_count(dev) + i > hw->unicast_filter_entries) {
> +		netdev_info(dev, "Too many address, switching to promiscuous\n");
> +		v = EMAC_FRM_FLT_RXALL;
> +	} else {
> +		netdev_for_each_uc_addr(ha, dev) {
> +			i++;
> +			sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
> +		}
> +	}
> +	writel(v, ioaddr + EMAC_RX_FRM_FLT);
> +}
> +
> +static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
> +				  unsigned int duplex,
> +				  unsigned int fc, unsigned int pause_time)
> +{
> +	void __iomem *ioaddr = hw->pcsr;
> +	u32 v;
> +
> +	v = readl(ioaddr + EMAC_RX_CTL0);
> +	if (fc == FLOW_AUTO)
> +		v |= EMAC_RX_FLOW_CTL_EN;
> +	else
> +		v &= ~EMAC_RX_FLOW_CTL_EN;
> +	writel(v, ioaddr + EMAC_RX_CTL0);
> +
> +	v = readl(ioaddr + EMAC_TX_FLOW_CTL);
> +	if (fc == FLOW_AUTO)
> +		v |= EMAC_TX_FLOW_CTL_EN;
> +	else
> +		v &= ~EMAC_TX_FLOW_CTL_EN;
> +	writel(v, ioaddr + EMAC_TX_FLOW_CTL);
> +}
> +
> +static int sun8i_dwmac_reset(struct stmmac_priv *priv)
> +{
> +	u32 v;
> +	int err;
> +
> +	v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
> +	writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
> +
> +	err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
> +				 !(v & 0x01), 100, 10000);
> +
> +	if (err) {
> +		dev_err(priv->device, "EMAC reset timeout\n");
> +		return -EFAULT;
> +	}
> +	return 0;
> +}
> +
> +static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
> +{
> +	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> +	struct device_node *node = priv->device->of_node;
> +	int ret;
> +	u32 reg, val;
> +
> +	reg = gmac->variant->default_syscon_value;
> +
> +	if (gmac->variant->internal_phy) {
> +		if (!gmac->use_internal_phy) {
> +			/* switch to external PHY interface */
> +			reg &= ~H3_EPHY_SELECT;
> +		} else {
> +			reg |= H3_EPHY_SELECT;
> +			reg &= ~H3_EPHY_SHUTDOWN;
> +			dev_info(priv->device, "Select internal_phy %x\n", reg);

The logging level is too high

> +
> +			if (of_property_read_bool(priv->plat->phy_node,
> +						  "allwinner,leds-active-low"))
> +				reg |= H3_EPHY_LED_POL;
> +			else
> +				reg &= ~H3_EPHY_LED_POL;
> +
> +			ret = of_mdio_parse_addr(priv->device,
> +						 priv->plat->phy_node);
> +			if (ret < 0) {
> +				dev_err(priv->device, "Could not parse MDIO addr\n");
> +				return ret;
> +			}
> +			/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
> +			 * address. No need to mask it again.
> +			 */
> +			reg |= ret << H3_EPHY_ADDR_SHIFT;
> +		}
> +	}
> +
> +	if (!of_property_read_u32(node, "allwinner,tx-delay", &val)) {

How do you compute it? Can't this be done through auto-training?

> +		dev_info(priv->device, "set tx-delay to %x\n", val);

change the logging level here too.

> +		if (val <= SYSCON_ETXDC_MASK) {
> +			reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT);
> +			reg |= (val << SYSCON_ETXDC_SHIFT);
> +		} else {
> +			dev_warn(priv->device, "Invalid TX clock delay: %d\n",
> +				 val);

If it's invalid, why don't you treat it as an error and return?

> +		}
> +	}
> +
> +	if (!of_property_read_u32(node, "allwinner,rx-delay", &val)) {
> +		dev_info(priv->device, "set rx-delay to %x\n", val);
> +		if (val <= SYSCON_ERXDC_MASK) {
> +			reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT);
> +			reg |= (val << SYSCON_ERXDC_SHIFT);
> +		} else {
> +			dev_warn(priv->device, "Invalid RX clock delay: %d\n",
> +				 val);
> +		}
> +	}
> +
> +	/* Clear interface mode bits */
> +	reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
> +	if (gmac->variant->support_rmii)
> +		reg &= ~SYSCON_RMII_EN;
> +
> +	switch (priv->plat->interface) {
> +	case PHY_INTERFACE_MODE_MII:
> +		/* default */
> +		break;
> +	case PHY_INTERFACE_MODE_RGMII:
> +		reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
> +		break;
> +	case PHY_INTERFACE_MODE_RMII:
> +		reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
> +		break;
> +	default:
> +		dev_err(priv->device, "Unsupported interface mode: %s",
> +			phy_modes(priv->plat->interface));
> +		return -EINVAL;
> +	}
> +
> +	regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
> +
> +	return 0;
> +}
> +
> +static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
> +{
> +	u32 reg = gmac->variant->default_syscon_value;
> +
> +	regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg);
> +}
> +
> +static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
> +{
> +	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> +	int ret;
> +
> +	if (gmac->ephy_clk) {
> +		ret = clk_prepare_enable(gmac->ephy_clk);
> +		if (ret) {
> +			dev_err(priv->device, "Cannot enable ephy\n");
> +			return ret;
> +		}
> +	}
> +
> +	if (gmac->rst_ephy) {
> +		ret = reset_control_deassert(gmac->rst_ephy);
> +		if (ret) {
> +			dev_err(priv->device, "Cannot deassert ephy\n");
> +			clk_disable_unprepare(gmac->ephy_clk);
> +			return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
> +{
> +	if (gmac->ephy_clk)
> +		clk_disable_unprepare(gmac->ephy_clk);
> +	if (gmac->rst_ephy)
> +		reset_control_assert(gmac->rst_ephy);
> +	return 0;
> +}
> +
> +static int sun8i_power_phy(struct net_device *ndev)
> +{
> +	struct stmmac_priv *priv = netdev_priv(ndev);
> +	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> +	int ret;
> +
> +	ret = sun8i_dwmac_power_internal_phy(priv);
> +	if (ret)
> +		return ret;
> +
> +	ret = sun8i_dwmac_set_syscon(priv);
> +	if (ret)
> +		goto error_phy;
> +
> +	ret = sun8i_dwmac_reset(priv);
> +	if (ret)
> +		goto error_phy;
> +	return 0;
> +
> +error_phy:
> +	sun8i_dwmac_unset_syscon(gmac);
> +	sun8i_dwmac_unpower_internal_phy(gmac);
> +	return ret;
> +}
> +
> +static void sun8i_unpower_phy(struct net_device *ndev)
> +{
> +	struct stmmac_priv *priv = netdev_priv(ndev);
> +	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> +
> +	sun8i_dwmac_unset_syscon(gmac);
> +	sun8i_dwmac_unpower_internal_phy(gmac);
> +}
> +
> +static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
> +{
> +	struct sunxi_priv_data *gmac = priv;
> +
> +	clk_disable_unprepare(gmac->tx_clk);
> +
> +	if (gmac->regulator)
> +		regulator_disable(gmac->regulator);
> +}
> +
> +static const struct stmmac_ops sun8i_dwmac_ops = {
> +	.core_init = sun8i_dwmac_core_init,
> +	.dump_regs = sun8i_dwmac_dump_mac_regs,
> +	.rx_ipc = sun8i_dwmac_rx_ipc_enable,
> +	.set_filter = sun8i_dwmac_set_filter,
> +	.flow_ctrl = sun8i_dwmac_flow_ctrl,
> +	.set_umac_addr = sun8i_dwmac_set_umac_addr,
> +	.get_umac_addr = sun8i_dwmac_get_umac_addr,
> +	.init_phy = sun8i_power_phy,
> +	.uninit_phy = sun8i_unpower_phy,
> +};
> +
> +static struct mac_device_info *sun8i_dwmac_setup(void __iomem *ioaddr,
> +						 int mcbins,
> +						 int perfect_uc_entries,
> +						 int *synopsys_id)
> +{
> +	struct mac_device_info *mac;
> +
> +	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
> +	if (!mac)
> +		return NULL;

Do you ever free that memory?

> +
> +	mac->pcsr = ioaddr;
> +	mac->mac = &sun8i_dwmac_ops;
> +	mac->dma = &sun8i_dwmac_dma_ops;
> +
> +	mac->link.port = 0;
> +	mac->link.duplex = BIT(0);
> +	mac->link.speed = 1;
> +	mac->mii.addr = EMAC_MDIO_CMD;
> +	mac->mii.data = EMAC_MDIO_DATA;
> +	mac->mii.reg_shift = 4;
> +	mac->mii.reg_mask = GENMASK(8, 4);
> +	mac->mii.addr_shift = 12;
> +	mac->mii.addr_mask = GENMASK(16, 12);
> +	mac->mii.clk_csr_shift = 20;
> +	mac->mii.clk_csr_mask = GENMASK(22, 20);
> +	mac->unicast_filter_entries = 8;
> +
> +	/* Synopsys Id is not available */
> +	*synopsys_id = 0;
> +
> +	return mac;
> +}
> +
> +static int sun8i_dwmac_probe(struct platform_device *pdev)
> +{
> +	struct plat_stmmacenet_data *plat_dat;
> +	struct stmmac_resources stmmac_res;
> +	struct sunxi_priv_data *gmac;
> +	struct device *dev = &pdev->dev;
> +	int ret;
> +
> +	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
> +	if (ret)
> +		return ret;
> +
> +	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
> +	if (IS_ERR(plat_dat))
> +		return PTR_ERR(plat_dat);
> +
> +	gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
> +	if (!gmac)
> +		return -ENOMEM;
> +
> +	gmac->variant = of_device_get_match_data(&pdev->dev);
> +	if (!gmac->variant) {
> +		dev_err(&pdev->dev, "Missing sun8i-emac variant\n");
> +		return -EINVAL;
> +	}
> +
> +	gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
> +	if (IS_ERR(gmac->tx_clk)) {
> +		dev_err(dev, "could not get tx clock\n");
> +		return PTR_ERR(gmac->tx_clk);
> +	}
> +
> +	/* Optional regulator for PHY */
> +	gmac->regulator = devm_regulator_get_optional(dev, "phy");
> +	if (IS_ERR(gmac->regulator)) {
> +		if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
> +			return -EPROBE_DEFER;
> +		dev_info(dev, "no regulator found\n");
> +		gmac->regulator = NULL;
> +	}
> +
> +	gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
> +						       "syscon");
> +	if (IS_ERR(gmac->regmap)) {
> +		ret = PTR_ERR(gmac->regmap);
> +		dev_err(&pdev->dev, "unable to map SYSCON:%d\n", ret);
> +		return ret;
> +	}
> +
> +	plat_dat->interface = of_get_phy_mode(dev->of_node);
> +	if (plat_dat->interface == gmac->variant->internal_phy) {
> +		dev_info(&pdev->dev, "Will use internal PHY\n");
> +		gmac->use_internal_phy = true;
> +		gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
> +		if (IS_ERR(gmac->ephy_clk)) {
> +			ret = PTR_ERR(gmac->ephy_clk);
> +			dev_err(&pdev->dev, "Cannot get EPHY clock err=%d\n",
> +				ret);
> +			return -EINVAL;
> +		}
> +
> +		gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
> +		if (IS_ERR(gmac->rst_ephy)) {
> +			ret = PTR_ERR(gmac->rst_ephy);
> +			if (ret == -EPROBE_DEFER)
> +				return ret;
> +			dev_err(&pdev->dev, "No EPHY reset control found %d\n",
> +				ret);
> +			return -EINVAL;
> +		}
> +	} else {
> +		dev_info(&pdev->dev, "Will use external PHY\n");
> +		gmac->use_internal_phy = false;
> +	}
> +
> +	/* platform data specifying hardware features and callbacks.
> +	 * hardware features were copied from Allwinner drivers.
> +	 */
> +	plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
> +	plat_dat->tx_coe = 1;
> +	plat_dat->has_sun8i = true;
> +	plat_dat->bsp_priv = gmac;
> +	plat_dat->init = sun8i_dwmac_init;
> +	plat_dat->exit = sun8i_dwmac_exit;
> +	plat_dat->setup = sun8i_dwmac_setup;
> +
> +	ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
> +	if (ret)
> +		return ret;
> +
> +	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
> +	if (ret)
> +		sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id sun8i_dwmac_match[] = {
> +	{ .compatible = "allwinner,sun8i-h3-emac",
> +		.data = &emac_variant_h3 },
> +	{ .compatible = "allwinner,sun8i-a83t-emac",
> +		.data = &emac_variant_a83t },
> +	{ .compatible = "allwinner,sun50i-a64-emac",
> +		.data = &emac_variant_a64 },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
> +
> +static struct platform_driver sun8i_dwmac_driver = {
> +	.probe  = sun8i_dwmac_probe,
> +	.remove = stmmac_pltfr_remove,
> +	.driver = {
> +		.name           = "sun8i-dwmac",
> +		.pm		= &stmmac_pltfr_pm_ops,
> +		.of_match_table = sun8i_dwmac_match,
> +	},
> +};
> +module_platform_driver(sun8i_dwmac_driver);
> +
> +MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
> +MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> index 5ff6bc4..11db658 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> @@ -450,6 +450,9 @@ static void stmmac_ethtool_gregs(struct net_device *dev,
>  		for (i = 0; i < 22; i++)
>  			reg_space[i + 55] =
>  			    readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
> +	} else if (priv->plat->has_sun8i) {

Surely we don't want to add a new flag to the common structure for
every new platform supported.

Can't you base that on the compatible instead?

Thanks a lot for your work,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 05/21] net-next: stmmac: Add dwmac-sun8i

[Corentin Labbe]

On Thu, Feb 16, 2017 at 08:05:24PM +0100, Maxime Ripard wrote:
> Hi,
> 

[...]
> > +
> > +struct emac_variant {
> > +	u32 default_syscon_value;
> 
> Why do you need a default value? Can't you read it from the syscon
> directly?
> 

Why not, but you can see the default value as "value for disabled state".
My fear is that something (uboot) modify it (keep it activated) before driver load.

[...]
> > +static void sun8i_dwmac_dump_regs(void __iomem *ioaddr)
> > +{
> > +	int i;
> > +
> > +	pr_info(" DMA registers\n");
> 
> Logging this as pr_info is bad already...
> 
> > +	for (i = 0; i < 0xC8; i += 4) {
> > +		if (i == 0x32 || i == 0x3C)
> > +			continue;
> > +		pr_err("Reg 0x%x: 0x%08x\n", i, readl(ioaddr + i));
> 
> ... But this is worse.
> 
> Why do you need to do that? Can't you create a file in debugfs
> instead?
> 

I just do as other glue does. But yes this is uglyi, no excuse.
Reworking all stmmac register dump (ethtool, stmmac_ops->dump_regs and stmmac_dma_ops->dump_regs) was on my todo list,
but I postponed it.

I will propose something better based on debugfs.

[...]
> > +static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr)
> > +{
> > +	u32 v;
> > +
> > +	v = readl(ioaddr + EMAC_TX_CTL0);
> > +	v |= EMAC_TX_TRANSMITTER_EN;
> > +	writel(v, ioaddr + EMAC_TX_CTL0);
> > +
> > +	v = readl(ioaddr + EMAC_TX_CTL1);
> > +	v |= EMAC_TX_DMA_START;
> > +	v |= EMAC_TX_DMA_EN;
> > +	writel(v, ioaddr + EMAC_TX_CTL1);
> 
> This is a bit worrying. There's not a single lock in your driver,
> while you have a significant number of read / modify / write.
> 
> Where is the locking handled?
> 

All thoses function are handled by the "stmmac_ops framework", all other glue drivers does not lock anything.
The few functions that need locking already got it on the calling stmmac side.

[...]
> > +static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
> > +{
> > +	struct sunxi_priv_data *gmac = priv;
> > +	int ret;
> > +
> > +	if (gmac->regulator) {
> > +		ret = regulator_enable(gmac->regulator);
> > +		if (ret) {
> > +			dev_err(&pdev->dev, "Fail to enable regulator\n");
> > +			return ret;
> > +		}
> > +	}
> > +
> > +	ret = clk_prepare_enable(gmac->tx_clk);
> > +	if (ret) {
> > +		dev_err(&pdev->dev, "Could not enable AHB clock\n");
> 
> If that call fails, you leave the regulator (if there was any) enabled.
> 

I will fix it

> > +		return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu)
> > +{
> > +	void __iomem *ioaddr = hw->pcsr;
> > +	u32 v;
> > +
> > +	v = (8 << 24);/* burst len */
> > +	writel(v, ioaddr + EMAC_BASIC_CTL1);
> 
> do you need an intermediate value? you should make a define for that
> too.
> 

I will fix it

[...]
> > +static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
> > +{
> > +	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
> > +	struct device_node *node = priv->device->of_node;
> > +	int ret;
> > +	u32 reg, val;
> > +
> > +	reg = gmac->variant->default_syscon_value;
> > +
> > +	if (gmac->variant->internal_phy) {
> > +		if (!gmac->use_internal_phy) {
> > +			/* switch to external PHY interface */
> > +			reg &= ~H3_EPHY_SELECT;
> > +		} else {
> > +			reg |= H3_EPHY_SELECT;
> > +			reg &= ~H3_EPHY_SHUTDOWN;
> > +			dev_info(priv->device, "Select internal_phy %x\n", reg);
> 
> The logging level is too high
> 

I will reduce it

> > +
> > +			if (of_property_read_bool(priv->plat->phy_node,
> > +						  "allwinner,leds-active-low"))
> > +				reg |= H3_EPHY_LED_POL;
> > +			else
> > +				reg &= ~H3_EPHY_LED_POL;
> > +
> > +			ret = of_mdio_parse_addr(priv->device,
> > +						 priv->plat->phy_node);
> > +			if (ret < 0) {
> > +				dev_err(priv->device, "Could not parse MDIO addr\n");
> > +				return ret;
> > +			}
> > +			/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
> > +			 * address. No need to mask it again.
> > +			 */
> > +			reg |= ret << H3_EPHY_ADDR_SHIFT;
> > +		}
> > +	}
> > +
> > +	if (!of_property_read_u32(node, "allwinner,tx-delay", &val)) {
> 
> How do you compute it? Can't this be done through auto-training?
> 

The value is the same as used in vendor BSP kernel.
I do not understand what you mean by auto-training.

> > +		dev_info(priv->device, "set tx-delay to %x\n", val);
> 
> change the logging level here too.
> 

I agree

> > +		if (val <= SYSCON_ETXDC_MASK) {
> > +			reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT);
> > +			reg |= (val << SYSCON_ETXDC_SHIFT);
> > +		} else {
> > +			dev_warn(priv->device, "Invalid TX clock delay: %d\n",
> > +				 val);
> 
> If it's invalid, why don't you treat it as an error and return?
> 

Ok

[...]
> > +static struct mac_device_info *sun8i_dwmac_setup(void __iomem *ioaddr,
> > +						 int mcbins,
> > +						 int perfect_uc_entries,
> > +						 int *synopsys_id)
> > +{
> > +	struct mac_device_info *mac;
> > +
> > +	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
> > +	if (!mac)
> > +		return NULL;
> 
> Do you ever free that memory?
> 

Good catch, I believed that the "stmmac framework" would free it.
I will send a fix for this memory leak.

[...]
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> > index 5ff6bc4..11db658 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
> > @@ -450,6 +450,9 @@ static void stmmac_ethtool_gregs(struct net_device *dev,
> >  		for (i = 0; i < 22; i++)
> >  			reg_space[i + 55] =
> >  			    readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4)));
> > +	} else if (priv->plat->has_sun8i) {
> 
> Surely we don't want to add a new flag to the common structure for
> every new platform supported.
> 
> Can't you base that on the compatible instead?

This part will be fixed with the debugfs speaked early in the mail.

But yes I have tried to avoid use of has_sun8i at maximum.

> 
> Thanks a lot for your work,
> Maxime
> 

Thanks for the review

Corentin Labbe
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Re: [PATCH 05/21] net-next: stmmac: Add dwmac-sun8i

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2916 bytes --]

On Fri, Feb 17, 2017 at 02:18:02PM +0100, Corentin Labbe wrote:
> On Thu, Feb 16, 2017 at 08:05:24PM +0100, Maxime Ripard wrote:
> > Hi,
> > 
> 
> [...]
> > > +
> > > +struct emac_variant {
> > > +	u32 default_syscon_value;
> > 
> > Why do you need a default value? Can't you read it from the syscon
> > directly?
> > 
> 
> Why not, but you can see the default value as "value for disabled
> state".

i'm not sure what you mean here, sorry.

> My fear is that something (uboot) modify it (keep it activated)
> before driver load.

You could have the same argument there then for the board that require
reading it. What if U-boot modified it to some non-functional state?

Either you trust the value there, and you read it, or you don't, and
then you never read it. But being stuck in between doesn't seem that
great.

> > > +static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr)
> > > +{
> > > +	u32 v;
> > > +
> > > +	v = readl(ioaddr + EMAC_TX_CTL0);
> > > +	v |= EMAC_TX_TRANSMITTER_EN;
> > > +	writel(v, ioaddr + EMAC_TX_CTL0);
> > > +
> > > +	v = readl(ioaddr + EMAC_TX_CTL1);
> > > +	v |= EMAC_TX_DMA_START;
> > > +	v |= EMAC_TX_DMA_EN;
> > > +	writel(v, ioaddr + EMAC_TX_CTL1);
> > 
> > This is a bit worrying. There's not a single lock in your driver,
> > while you have a significant number of read / modify / write.
> > 
> > Where is the locking handled?
> 
> All thoses function are handled by the "stmmac_ops framework", all
> other glue drivers does not lock anything.

Most of them seem to use regmap though, that has an internal lock.

> The few functions that need locking already got it on the calling
> stmmac side.

Ok.

> > > +
> > > +			if (of_property_read_bool(priv->plat->phy_node,
> > > +						  "allwinner,leds-active-low"))
> > > +				reg |= H3_EPHY_LED_POL;
> > > +			else
> > > +				reg &= ~H3_EPHY_LED_POL;
> > > +
> > > +			ret = of_mdio_parse_addr(priv->device,
> > > +						 priv->plat->phy_node);
> > > +			if (ret < 0) {
> > > +				dev_err(priv->device, "Could not parse MDIO addr\n");
> > > +				return ret;
> > > +			}
> > > +			/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
> > > +			 * address. No need to mask it again.
> > > +			 */
> > > +			reg |= ret << H3_EPHY_ADDR_SHIFT;
> > > +		}
> > > +	}
> > > +
> > > +	if (!of_property_read_u32(node, "allwinner,tx-delay", &val)) {
> > 
> > How do you compute it? Can't this be done through auto-training?
> 
> The value is the same as used in vendor BSP kernel.

This is not really usable though. I've had already three boards that
never got any BSP kernel. You need to be able at least to document
some way to compute it (even if it's based on manual, trial and error
process).

> I do not understand what you mean by auto-training.

Being able to automatically detect the optimal settings at boot time.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[PATCH 06/21] ARM: dts: sun8i-h3: Add dt node for the syscon control module

[Corentin Labbe]

From: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

This patch add the dt node for the syscon register present on the
Allwinner H3.

Only two register are present in this syscon and the only one useful is
the one dedicated to EMAC clock.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 27780b9..9f91aaa 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -140,6 +140,12 @@
 		#size-cells = <1>;
 		ranges;
 
+		syscon: syscon@01c00000 {
+			compatible = "syscon",
+				     "allwinner,sun8i-h3-system-controller";
+			reg = <0x01c00000 0x1000>;
+		};
+
 		dma: dma-controller@01c02000 {
 			compatible = "allwinner,sun8i-h3-dma";
 			reg = <0x01c02000 0x1000>;
-- 
2.10.2

[PATCH 07/21] ARM: dts: sun8i-h3: add dwmac-sun8i ethernet driver

[Corentin Labbe]

From: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000
speed.

This patch enable the dwmac-sun8i on the Allwinner H3 SoC Device-tree.
The SoC H3 have an internal PHY, so optionals syscon and ephy are set.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 9f91aaa..61d56d2 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -594,6 +594,31 @@
 			#size-cells = <0>;
 		};
 
+		emac: ethernet@1c30000 {
+			compatible = "allwinner,sun8i-h3-emac";
+			syscon = <&syscon>;
+			reg = <0x01c30000 0x104>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			resets = <&ccu RST_BUS_EMAC>;
+			reset-names = "stmmaceth";
+			clocks = <&ccu CLK_BUS_EMAC>;
+			clock-names = "stmmaceth";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			mdio: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				int_mii_phy: ethernet-phy@1 {
+					reg = <1>;
+					clocks = <&ccu CLK_BUS_EPHY>;
+					resets = <&ccu RST_BUS_EPHY>;
+				};
+			};
+		};
+
 		gic: interrupt-controller@01c81000 {
 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 			reg = <0x01c81000 0x1000>,
-- 
2.10.2

[PATCH 08/21] ARM: dts: sun8i-h3: add dwmac-sun8i rgmii pins

[Corentin Labbe]

This patch add pinctrl node for dwmac-sun8i on H3.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 61d56d2..59ed40e 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -349,6 +349,17 @@
 				function = "i2c2";
 			};
 
+			emac_rgmii_pins: emac0@0 {
+				allwinner,pins = "PD0", "PD1", "PD2", "PD3",
+						"PD4", "PD5", "PD7",
+						"PD8", "PD9", "PD10",
+						"PD12", "PD13", "PD15",
+						"PD16", "PD17";
+				allwinner,function = "emac";
+				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			mmc0_pins_a: mmc0@0 {
 				pins = "PF0", "PF1", "PF2", "PF3",
 				       "PF4", "PF5";
-- 
2.10.2

Re: [PATCH 08/21] ARM: dts: sun8i-h3: add dwmac-sun8i rgmii pins

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1143 bytes --]

On Thu, Feb 16, 2017 at 01:48:46PM +0100, Corentin Labbe wrote:
> This patch add pinctrl node for dwmac-sun8i on H3.
> 
> Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 61d56d2..59ed40e 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -349,6 +349,17 @@
>  				function = "i2c2";
>  			};
>  
> +			emac_rgmii_pins: emac0@0 {
> +				allwinner,pins = "PD0", "PD1", "PD2", "PD3",
> +						"PD4", "PD5", "PD7",
> +						"PD8", "PD9", "PD10",
> +						"PD12", "PD13", "PD15",
> +						"PD16", "PD17";
> +				allwinner,function = "emac";

Please use the generic pin config properties (ie. pins and functions).

> +				allwinner,drive = <SUN4I_PINCTRL_40_MA>;

Why do you need to use 40mA?

> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

This is the default now.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 08/21] ARM: dts: sun8i-h3: add dwmac-sun8i rgmii pins

[Corentin Labbe]

On Thu, Feb 16, 2017 at 08:06:32PM +0100, Maxime Ripard wrote:
> On Thu, Feb 16, 2017 at 01:48:46PM +0100, Corentin Labbe wrote:
> > This patch add pinctrl node for dwmac-sun8i on H3.
> > 
> > Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> >  arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> > index 61d56d2..59ed40e 100644
> > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> > @@ -349,6 +349,17 @@
> >  				function = "i2c2";
> >  			};
> >  
> > +			emac_rgmii_pins: emac0@0 {
> > +				allwinner,pins = "PD0", "PD1", "PD2", "PD3",
> > +						"PD4", "PD5", "PD7",
> > +						"PD8", "PD9", "PD10",
> > +						"PD12", "PD13", "PD15",
> > +						"PD16", "PD17";
> > +				allwinner,function = "emac";
> 
> Please use the generic pin config properties (ie. pins and functions).
> 
> > +				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> 
> Why do you need to use 40mA?
> 
> > +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> 
> This is the default now.
> 

Will fix that in all DT

Thanks
Corentin Labbe

[PATCH 09/21] ARM: dts: sun8i: Enable dwmac-sun8i on the Banana Pi M2+

[Corentin Labbe]

From: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

The dwmac-sun8i hardware is present on the Banana Pi M2+
It uses an external PHY rtl8211e via RGMII.

This patch create the needed regulator, emac and phy nodes.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 38 +++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index c0c49dd..a4f7b99 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -91,6 +91,18 @@
 		pinctrl-0 = <&wifi_en_bpi_m2p>;
 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
 	};
+
+	reg_gmac_3v3: gmac-3v3 {
+		      compatible = "regulator-fixed";
+		      pinctrl-names = "default";
+		      pinctrl-0 = <&gmac_power_pin_orangepi>;
+		      regulator-name = "gmac-3v3";
+		      regulator-min-microvolt = <3300000>;
+		      regulator-max-microvolt = <3300000>;
+		      startup-delay-us = <100000>;
+		      enable-active-high;
+		      gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+	      };
 };
 
 &ehci1 {
@@ -187,3 +199,29 @@
 	/* USB VBUS is on as long as VCC-IO is on */
 	status = "okay";
 };
+
+&pio {
+	gmac_power_pin_orangepi: gmac_power_pin@0 {
+		 allwinner,pins = "PD6";
+		 allwinner,function = "gpio_out";
+		 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	 };
+};
+
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		reg = <0>;
+	};
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_rgmii_pins>;
+	phy-supply = <&reg_gmac_3v3>;
+	phy-handle = <&ext_rgmii_phy>;
+	phy-mode = "rgmii";
+
+	allwinner,leds-active-low;
+	status = "okay";
+};
-- 
2.10.2

[PATCH 10/21] ARM: dts: sun8i: Enable dwmac-sun8i on the Orange PI PC

[Corentin Labbe]

From: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

The dwmac-sun8i hardware is present on the Orange PI PC.
It uses the internal PHY.

This patch create the needed emac node.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index d43978d..13f7267 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -54,6 +54,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &emac;
 	};
 
 	chosen {
@@ -185,3 +186,10 @@
 	/* USB VBUS is always on */
 	status = "okay";
 };
+
+&emac {
+	phy-handle = <&int_mii_phy>;
+	phy-mode = "mii";
+	allwinner,leds-active-low;
+	status = "okay";
+};
-- 
2.10.2

[PATCH 11/21] ARM: dts: sun8i: Enable dwmac-sun8i on the Orange Pi 2

[Corentin Labbe]

The dwmac-sun8i hardware is present on the Orange PI 2.
It uses the internal PHY.

This patch create the needed emac node.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 047e9e1..4b5077c 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -56,6 +56,7 @@
 		serial0 = &uart0;
 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
 		ethernet1 = &rtl8189;
+		ethernet0 = &emac;
 	};
 
 	chosen {
@@ -204,3 +205,10 @@
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	status = "okay";
 };
+
+&emac {
+	phy-handle = <&int_mii_phy>;
+	phy-mode = "mii";
+	allwinner,leds-active-low;
+	status = "okay";
+};
-- 
2.10.2

[PATCH 12/21] ARM: dts: sun8i: Enable dwmac-sun8i on the Orange PI One

[Corentin Labbe]

The dwmac-sun8i hardware is present on the Orange PI One.
It uses the internal PHY.

This patch create the needed emac node.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 34da853..a053b79 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -54,6 +54,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &emac;
 	};
 
 	chosen {
@@ -94,6 +95,13 @@
 	status = "okay";
 };
 
+&emac {
+	phy-handle = <&int_mii_phy>;
+	phy-mode = "mii";
+	allwinner,leds-active-low;
+	status = "okay";
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
-- 
2.10.2

[PATCH 13/21] ARM: dts: sun8i: Enable dwmac-sun8i on the Orange Pi plus

[Corentin Labbe]

The dwmac-sun8i hardware is present on the Orange PI plus.
It uses an external PHY rtl8211e via RGMII.

This patch create the needed regulator, emac and phy nodes.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 36 ++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index 8c40ab7..17b2b92 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -58,6 +58,18 @@
 		enable-active-high;
 		gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
 	};
+
+	reg_gmac_3v3: gmac-3v3 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gmac_power_pin_orangepi>;
+		regulator-name = "gmac-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <100000>;
+		enable-active-high;
+		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+	};
 };
 
 &ehci3 {
@@ -86,8 +98,32 @@
 		pins = "PG11";
 		function = "gpio_out";
 	};
+
+	gmac_power_pin_orangepi: gmac_power_pin@0 {
+		allwinner,pins = "PD6";
+		allwinner,function = "gpio_out";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+		};
 };
 
 &usbphy {
 	usb3_vbus-supply = <&reg_usb3_vbus>;
 };
+
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		reg = <0>;
+	};
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_rgmii_pins>;
+	phy-supply = <&reg_gmac_3v3>;
+	phy-handle = <&ext_rgmii_phy>;
+	phy-mode = "rgmii";
+
+	allwinner,leds-active-low;
+	status = "okay";
+};
-- 
2.10.2

[PATCH 14/21] ARM: dts: sun8i: orangepi-pc-plus: Set EMAC activity LEDs to active high

[Corentin Labbe]

On the Orange Pi PC Plus, the polarity of the LEDs on the RJ45 Ethernet
port were changed from active low to active high.

Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
index 8b93f5c..0380769 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
@@ -86,3 +86,8 @@
 	/* eMMC is missing pull-ups */
 	bias-pull-up;
 };
+
+&emac {
+	/* LEDs changed to active high on the plus */
+	/delete-property/ allwinner,leds-active-low;
+};
-- 
2.10.2

[PATCH 15/21] ARM64: dts: sun50i-a64: Add dt node for the syscon control module

[Corentin Labbe]

This patch add the dt node for the syscon register present on the
Allwinner A64.

Only two register are present in this syscon and the only one useful is
the one dedicated to EMAC clock.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2..3b09af2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -121,6 +121,12 @@
 		#size-cells = <1>;
 		ranges;
 
+		syscon: syscon@01c00000 {
+			compatible = "syscon",
+				"allwinner,sun8i-h3-system-controller";
+			reg = <0x01c00000 0x1000>;
+		};
+
 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,sun50i-a64-mmc";
 			reg = <0x01c0f000 0x1000>;
-- 
2.10.2

[PATCH 16/21] ARM64: dts: sun50i-a64: add dwmac-sun8i Ethernet driver

[Corentin Labbe]

The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit
connections. It is very similar to the device found in the Allwinner
H3, but lacks the internal 100 Mbit PHY and its associated control
bits.
This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps
it disabled at this level.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 37 +++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 3b09af2..57d69e5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -277,6 +277,23 @@
 				bias-pull-up;
 			};
 
+			rmii_pins: rmii_pins {
+				pins = "PD10", "PD11", "PD13", "PD14",
+						"PD17", "PD18", "PD19", "PD20",
+						"PD22", "PD23";
+				function = "emac";
+				drive-strength = <40>;
+			};
+
+			rgmii_pins: rgmii_pins {
+				pins = "PD8", "PD9", "PD10", "PD11",
+						"PD12", "PD13", "PD15",
+						"PD16", "PD17", "PD18", "PD19",
+						"PD20", "PD21", "PD22", "PD23";
+				function = "emac";
+				drive-strength = <40>;
+			};
+
 			uart0_pins_a: uart0@0 {
 				pins = "PB8", "PB9";
 				function = "uart0";
@@ -381,6 +398,26 @@
 			#size-cells = <0>;
 		};
 
+		emac: ethernet@1c30000 {
+			compatible = "allwinner,sun50i-a64-emac";
+			syscon = <&syscon>;
+			reg = <0x01c30000 0x100>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			resets = <&ccu RST_BUS_EMAC>;
+			reset-names = "stmmaceth";
+			clocks = <&ccu CLK_BUS_EMAC>;
+			clock-names = "stmmaceth";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mdio: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
 		gic: interrupt-controller@1c81000 {
 			compatible = "arm,gic-400";
 			reg = <0x01c81000 0x1000>,
-- 
2.10.2

[PATCH 17/21] ARM: dts: sun50i-a64: enable dwmac-sun8i on pine64

[Corentin Labbe]

The dwmac-sun8i hardware is present on the pine64
It uses an external PHY via RMII.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed3..b53994d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -109,3 +109,18 @@
 &usbphy {
 	status = "okay";
 };
+
+&mdio {
+	ext_rmii_phy1: ethernet-phy@1 {
+	      reg = <1>;
+	};
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rmii_pins>;
+	phy-mode = "rmii";
+	phy-handle = <&ext_rmii_phy1>;
+	status = "okay";
+
+};
-- 
2.10.2

[PATCH 18/21] ARM: dts: sun50i-a64: enable dwmac-sun8i on pine64 plus

[Corentin Labbe]

The dwmac-sun8i hardware is present on the pine64 plus.
It uses an external PHY rtl8211e via RGMII.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
index 790d14d..8e06aed 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -46,5 +46,19 @@
 	model = "Pine64+";
 	compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
 
-	/* TODO: Camera, Ethernet PHY, touchscreen, etc. */
+	/* TODO: Camera, touchscreen, etc. */
+};
+
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-handle = <&ext_rgmii_phy>;
+	status = "okay";
 };
-- 
2.10.2

[PATCH 19/21] ARM: dts: sun50i-a64: enable dwmac-sun8i on the BananaPi M64

[Corentin Labbe]

The dwmac-sun8i  hardware is present on the BananaPi M64.
It uses an external PHY rtl8211e via RGMII.

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 6872135..347c262 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -77,6 +77,20 @@
 	bias-pull-up;
 };
 
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	phy-mode = "rgmii";
+	phy-handle = <&ext_rgmii_phy>;
+	status = "okay";
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
-- 
2.10.2

[PATCH 20/21] ARM: sunxi: Enable dwmac-sun8i driver on sunxi_defconfig

[Corentin Labbe]

From: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Enable the dwmac-sun8i driver in the sunxi default configuration

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/configs/sunxi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index da92c25..33bde86 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -40,6 +40,7 @@ CONFIG_ATA=y
 CONFIG_AHCI_SUNXI=y
 CONFIG_NETDEVICES=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_DWMAC_SUN8I=m
 # CONFIG_NET_VENDOR_ARC is not set
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
-- 
2.10.2

Re: [PATCH 20/21] ARM: sunxi: Enable dwmac-sun8i driver on sunxi_defconfig

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 944 bytes --]

Hi,

On Thu, Feb 16, 2017 at 01:48:58PM +0100, Corentin Labbe wrote:
> From: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> 
> Enable the dwmac-sun8i driver in the sunxi default configuration
> 
> Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/configs/sunxi_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
> index da92c25..33bde86 100644
> --- a/arch/arm/configs/sunxi_defconfig
> +++ b/arch/arm/configs/sunxi_defconfig
> @@ -40,6 +40,7 @@ CONFIG_ATA=y
>  CONFIG_AHCI_SUNXI=y
>  CONFIG_NETDEVICES=y
>  CONFIG_SUN4I_EMAC=y
> +CONFIG_DWMAC_SUN8I=m

I think I'd prefer to have it compiled statically, just like the other
net drivers, and drivers in general.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

Re: [PATCH 20/21] ARM: sunxi: Enable dwmac-sun8i driver on sunxi_defconfig

[Corentin Labbe]

On Thu, Feb 16, 2017 at 08:08:27PM +0100, Maxime Ripard wrote:
> Hi,
> 
> On Thu, Feb 16, 2017 at 01:48:58PM +0100, Corentin Labbe wrote:
> > From: LABBE Corentin <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > 
> > Enable the dwmac-sun8i driver in the sunxi default configuration
> > 
> > Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> >  arch/arm/configs/sunxi_defconfig | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
> > index da92c25..33bde86 100644
> > --- a/arch/arm/configs/sunxi_defconfig
> > +++ b/arch/arm/configs/sunxi_defconfig
> > @@ -40,6 +40,7 @@ CONFIG_ATA=y
> >  CONFIG_AHCI_SUNXI=y
> >  CONFIG_NETDEVICES=y
> >  CONFIG_SUN4I_EMAC=y
> > +CONFIG_DWMAC_SUN8I=m
> 
> I think I'd prefer to have it compiled statically, just like the other
> net drivers, and drivers in general.
> 
> Thanks!
> Maxime
> 

In previous sun8i-emac, someone request that CONFIG must be set as module because kernel went too big.
But I do not care to set it statically.

Regards
Corentin Labbe

[PATCH 21/21] ARM: sunxi: Enable dwmac-sun8i driver on multi_v7_defconfig

[Corentin Labbe]

Enable the dwmac-sun8i driver in the multi_v7 default configuration

Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 3a17555..72f974d 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -257,6 +257,7 @@ CONFIG_SMSC911X=y
 CONFIG_STMMAC_ETH=y
 CONFIG_STMMAC_PLATFORM=y
 CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_SUN8I=m
 CONFIG_TI_CPSW=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_AT803X_PHY=y
-- 
2.10.2