[PATCH 0/4] ARM64: Initial Marvell IAP140 enablement

[PATCH 0/4] ARM64: Initial Marvell IAP140 enablement

[Andreas Färber]

Hello,

This mini-series adds initial support for the Marvell IAP140 SoC (aka PXA1908)
and the Andromeda Box Edge development board.

In order to enable the 8250 UART driver, it reuses ARCH_PXA; but some drivers
enabled with ARCH_PXA don't build due to arm assembly or arm64's lack of mach-,
so their dependencies need to be limited to ARM alongside (blacklisted). The
alternative would of course be to choose a new ARCH_ symbol and to selectively
add it to drivers known working (whitelisting). The latter would require
finding a suitable name.

Both earlycon and serial are working, but an explicit console=ttyS0,115200n8
is needed; with just "earlycon" and stdout-path the earlycon stops early and
switches to a tty0, long before disabling the bootconsole...

All four CPUs come up, and an initrd can be reached.

However, there are errors about CPUs 1-3 having a zero SYS_CNTFRQ_EL0:

[    0.095812] smp: Bringing up secondary CPUs ...
======pxa1908_pmu_core_pwr_on: mpidr = 0x1
======pxa1908_pmu_core_pwr_on: mpidr = 0x2
======pxa1908_pmu_core_pwr_on: mpidr = 0x3
[    0.133419] Detected VIPT I-cache on CPU1
[    0.133430] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000
[    0.133447] Unsupported CPU feature variation.
...
[    0.133748] CPU1: Booted secondary processor [410fd032]
[    0.165465] Detected VIPT I-cache on CPU2
[    0.165474] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000
[    0.165505] CPU2: Booted secondary processor [410fd032]
[    0.197539] Detected VIPT I-cache on CPU3
[    0.197546] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000
[    0.197573] CPU3: Booted secondary processor [410fd032]
[    0.197625] smp: Brought up 1 node, 4 CPUs
[    0.522514] SMP: Total of 4 processors activated.
[    0.527212] CPU features: detected feature: 32-bit EL0 Support
[    0.533105] CPU: All CPU(s) started at EL2

KVM appears to initialize okay, but was not yet tested with guests.

[    0.865255] kvm [1]: 8-bit VMID
[    0.868401] kvm [1]: IDMAP page: d23000
[    0.872233] kvm [1]: HYP VA range: 800000000000:ffffffffffff
[    0.878262] kvm [1]: Hyp mode initialized successfully
[    0.883429] kvm [1]: vgic-v2@d1dfc000
[    0.887179] kvm [1]: vgic interrupt IRQ1
[    0.891120] kvm [1]: virtual timer IRQ4

More Marvell drivers may be available in-tree for reuse - besides build errors
the limitation is currently the lack of an IAP140 clk driver though. Patch 4/4
works around that for UART0 with a fixed-clock.

A 3.14 based tree is available on GitHub acorn-marvell/brillo_pxa_kernel. No
driver comparisons to mainline have been attempted yet.

Booting required changes to the vendor U-Boot,
cf. https://en.opensuse.org/HCL:AndromedaBoxEdge

https://github.com/afaerber/linux/commits/edge-next

Have a lot of fun!

Cheers,
Andreas

Cc: info-PWLG29+z7hGxBmiGZ5/UTQ@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

Andreas Färber (4):
  ARM64: Prepare Marvell IAP140 aka PXA1908
  Documentation: devicetree: arm: Document Marvell IAP140
  ARM64: dts: marvell: Add IAP140 and Andromeda Box Edge
  ARM64: dts: marvell: iap140-andromeda-box-edge: Add uart0 clock

 .../devicetree/bindings/arm/marvell/iap140.txt     |   7 +
 arch/arm64/Kconfig.platforms                       |   5 +
 arch/arm64/boot/dts/marvell/Makefile               |   2 +
 .../boot/dts/marvell/iap140-andromeda-box-edge.dts |  77 ++++++++
 arch/arm64/boot/dts/marvell/iap140.dtsi            | 195 +++++++++++++++++++++
 drivers/clk/Kconfig                                |   2 +-
 drivers/mmc/host/Kconfig                           |   2 +-
 drivers/tty/serial/Kconfig                         |   2 +-
 8 files changed, 289 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/iap140.txt
 create mode 100644 arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
 create mode 100644 arch/arm64/boot/dts/marvell/iap140.dtsi

-- 
2.10.2

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[PATCH 3/4] ARM64: dts: marvell: Add IAP140 and Andromeda Box Edge

[Andreas Färber]

PPI interrupts 11, 10, 9 are guesses, and so are the second two memory
regions of the GIC.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 arch/arm64/boot/dts/marvell/Makefile               |   2 +
 .../boot/dts/marvell/iap140-andromeda-box-edge.dts |  70 ++++++++
 arch/arm64/boot/dts/marvell/iap140.dtsi            | 195 +++++++++++++++++++++
 3 files changed, 267 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
 create mode 100644 arch/arm64/boot/dts/marvell/iap140.dtsi

diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 3e6ce6c..d2046be 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -9,6 +9,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
 
+dtb-$(CONFIG_ARCH_PXA) += iap140-andromeda-box-edge.dtb
+
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)
 clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts b/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
new file mode 100644
index 0000000..de01d93
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/memreserve/ 0x09000000 0x01000000;
+/memreserve/ 0x0a000000 0x00080000;
+
+#include "iap140.dtsi"
+
+/ {
+	compatible = "mrvl,andromeda-box-edge", "mrvl,iap140";
+	model = "Andromeda Box Edge";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/marvell/iap140.dtsi b/arch/arm64/boot/dts/marvell/iap140.dtsi
new file mode 100644
index 0000000..38acb14
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/iap140.dtsi
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "mrvl,iap140";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		smmu: iommu@c0010000 {
+			compatible = "arm,mmu-400";
+			reg = <0x0 0xc0010000 0x0 0x10000>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+			             <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		asram: sram@d12a0000 {
+			compatible = "mmio-sram";
+			reg = <0x0 0xd12a0000 0x0 0x10000>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@d1df9000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xd1df9000 0x0 0x1000>,
+			      <0x0 0xd1dfa000 0x0 0x2000>,
+			      <0x0 0xd1dfc000 0x0 0x2000>,
+			      <0x0 0xd1dfe000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		apb@d4000000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xd4000000 0x0 0x00200000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0xd4000000 0x00200000>;
+
+			pdma: dma-controller@0 {
+				compatible = "marvell,pdma-1.0";
+				reg = <0x0 0x10000>;
+				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				#dma-cells = <2>;
+				#dma-channels = <30>;
+			};
+
+			uart0: serial@17000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0x17000 0x1000>;
+				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&pdma 21 1>,
+				       <&pdma 22 1>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			uart1: serial@18000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0x18000 0x1000>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&pdma 23 1>,
+				       <&pdma 24 1>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			uart2: serial@36000 {
+				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+				reg = <0x36000 0x1000>;
+				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&pdma 4 1>,
+				       <&pdma 5 1>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+		};
+
+		axi@d4200000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xd4200000 0x0 0x00200000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x0 0xd4200000 0x00200000>;
+		};
+	};
+};
-- 
2.10.2

[PATCH 2/4] Documentation: devicetree: arm: Document Marvell IAP140

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/marvell/iap140.txt | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/iap140.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/iap140.txt b/Documentation/devicetree/bindings/arm/marvell/iap140.txt
new file mode 100644
index 0000000..25d307c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/iap140.txt
@@ -0,0 +1,7 @@
+Marvell IAP140 Device Tree Bindings
+-----------------------------------
+
+Boards using a SoC of the Marvell IAP140 family must carry the following
+root node property:
+
+ - compatible :  must contain "mrvl,iap140"
-- 
2.10.2

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Re: [PATCH 2/4] Documentation: devicetree: arm: Document Marvell IAP140

[Thomas Petazzoni]

Hello,

On Sun, 19 Feb 2017 04:19:58 +0100, Andreas Färber wrote:

> + - compatible :  must contain "mrvl,iap140"

Even though there's indeed a good number of existing "mrvl," compatible
strings in the tree, the official vendor prefix according to
Documentation/devicetree/bindings/vendor-prefixes.txt is "marvell".
Probably you should use that instead for new bindings?

Thanks,

Thomas
-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com
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Re: [PATCH 2/4] Documentation: devicetree: arm: Document Marvell IAP140

[Andreas Färber]

Hi,

Am 20.02.2017 um 13:56 schrieb Thomas Petazzoni:
> On Sun, 19 Feb 2017 04:19:58 +0100, Andreas Färber wrote:
> 
>> + - compatible :  must contain "mrvl,iap140"
> 
> Even though there's indeed a good number of existing "mrvl," compatible
> strings in the tree, the official vendor prefix according to
> Documentation/devicetree/bindings/vendor-prefixes.txt is "marvell".
> Probably you should use that instead for new bindings?

I'm confused now. According to Marvell IR [0] they are NASDAQ-listed as
MRVL. My understanding is that in that case the official vendor prefix
becomes mrvl. Why not here? Would be good to understand for other
pending vendors such as Actions Semi.

Any comments on the iap140 vs. pxa1908 naming? The Communication
Processors section has disappeared from marvell.com, so I couldn't
verify whether IAP140 was renamed from PXA1908 or whether both coexist
and we should add a second compatible string here?

Thanks,
Andreas

[0] http://investor.marvell.com/phoenix.zhtml?c=120802&p=irol-irhome

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Re: [PATCH 2/4] Documentation: devicetree: arm: Document Marvell IAP140

[Thomas Petazzoni]

Hello,

On Mon, 20 Feb 2017 14:16:13 +0100, Andreas Färber wrote:

> I'm confused now. According to Marvell IR [0] they are NASDAQ-listed as
> MRVL. My understanding is that in that case the official vendor prefix
> becomes mrvl. Why not here?

Not sure why, but as of today, we have a mix of "mrvl" and "marvell" in
the tree, and "marvell" is the one official listed in
vendor-prefixes.txt.

> Any comments on the iap140 vs. pxa1908 naming? The Communication
> Processors section has disappeared from marvell.com, so I couldn't
> verify whether IAP140 was renamed from PXA1908 or whether both coexist
> and we should add a second compatible string here?

I don't have an opinion on this because I'm not familiar with this
family of Marvell SoCs. However, the only thing I would recommend is
that you send a patch to update Documentation/arm/Marvell/README to
document this PXA1908/IAP140 thing. This is particularly important
since this document mentions PXA1908 already.

Thanks!

Thomas
-- 
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Embedded Linux and Kernel engineering
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[PATCH 4/4] ARM64: dts: marvell: iap140-andromeda-box-edge: Add uart0 clock

[Andreas Färber]

Use a fixed clock to enable ttyS0 output.

Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
 arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts b/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
index de01d93..dceab69 100644
--- a/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
+++ b/arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
@@ -63,8 +63,15 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x40000000>;
 	};
+
+	uart0_clk: uart0-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <14740000>;
+		#clock-cells = <0>;
+	};
 };
 
 &uart0 {
 	status = "okay";
+	clocks = <&uart0_clk>;
 };
-- 
2.10.2

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Re: [PATCH 0/4] ARM64: Initial Marvell IAP140 enablement

[Gregory CLEMENT]

Hi Andreas,
 
 On dim., févr. 19 2017, Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org> wrote:

> Hello,
>
> This mini-series adds initial support for the Marvell IAP140 SoC (aka PXA1908)
> and the Andromeda Box Edge development board.

Given the name of the SoC (PXA1908) and the fact that you reuse driver
related to PXA, for me these SoC is neither a mvebu nor a berlin SoC. So
just to avoid any misunderstanding, I don't mind being CC and possibly
doing review but I don't plan to take this patch ( I don't think the
berlin maintainer will do it too). 

>
> In order to enable the 8250 UART driver, it reuses ARCH_PXA; but some drivers
> enabled with ARCH_PXA don't build due to arm assembly or arm64's lack of mach-,
> so their dependencies need to be limited to ARM alongside (blacklisted). The
> alternative would of course be to choose a new ARCH_ symbol and to selectively
> add it to drivers known working (whitelisting). The latter would require
> finding a suitable name.

For this kind of issue you can have a look on what we did when
introducing mvebu SoC using ARM64.

Gregory

>
> Both earlycon and serial are working, but an explicit console=ttyS0,115200n8
> is needed; with just "earlycon" and stdout-path the earlycon stops early and
> switches to a tty0, long before disabling the bootconsole...
>
> All four CPUs come up, and an initrd can be reached.
>
> However, there are errors about CPUs 1-3 having a zero SYS_CNTFRQ_EL0:
>
> [    0.095812] smp: Bringing up secondary CPUs ...
> ======pxa1908_pmu_core_pwr_on: mpidr = 0x1
> ======pxa1908_pmu_core_pwr_on: mpidr = 0x2
> ======pxa1908_pmu_core_pwr_on: mpidr = 0x3
> [    0.133419] Detected VIPT I-cache on CPU1
> [    0.133430] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000
> [    0.133447] Unsupported CPU feature variation.
> ...
> [    0.133748] CPU1: Booted secondary processor [410fd032]
> [    0.165465] Detected VIPT I-cache on CPU2
> [    0.165474] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000
> [    0.165505] CPU2: Booted secondary processor [410fd032]
> [    0.197539] Detected VIPT I-cache on CPU3
> [    0.197546] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000
> [    0.197573] CPU3: Booted secondary processor [410fd032]
> [    0.197625] smp: Brought up 1 node, 4 CPUs
> [    0.522514] SMP: Total of 4 processors activated.
> [    0.527212] CPU features: detected feature: 32-bit EL0 Support
> [    0.533105] CPU: All CPU(s) started at EL2
>
> KVM appears to initialize okay, but was not yet tested with guests.
>
> [    0.865255] kvm [1]: 8-bit VMID
> [    0.868401] kvm [1]: IDMAP page: d23000
> [    0.872233] kvm [1]: HYP VA range: 800000000000:ffffffffffff
> [    0.878262] kvm [1]: Hyp mode initialized successfully
> [    0.883429] kvm [1]: vgic-v2@d1dfc000
> [    0.887179] kvm [1]: vgic interrupt IRQ1
> [    0.891120] kvm [1]: virtual timer IRQ4
>
> More Marvell drivers may be available in-tree for reuse - besides build errors
> the limitation is currently the lack of an IAP140 clk driver though. Patch 4/4
> works around that for UART0 with a fixed-clock.
>
> A 3.14 based tree is available on GitHub acorn-marvell/brillo_pxa_kernel. No
> driver comparisons to mainline have been attempted yet.
>
> Booting required changes to the vendor U-Boot,
> cf. https://en.opensuse.org/HCL:AndromedaBoxEdge
>
> https://github.com/afaerber/linux/commits/edge-next
>
> Have a lot of fun!
>
> Cheers,
> Andreas
>
> Cc: info-PWLG29+z7hGxBmiGZ5/UTQ@public.gmane.org
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>
> Andreas Färber (4):
>   ARM64: Prepare Marvell IAP140 aka PXA1908
>   Documentation: devicetree: arm: Document Marvell IAP140
>   ARM64: dts: marvell: Add IAP140 and Andromeda Box Edge
>   ARM64: dts: marvell: iap140-andromeda-box-edge: Add uart0 clock
>
>  .../devicetree/bindings/arm/marvell/iap140.txt     |   7 +
>  arch/arm64/Kconfig.platforms                       |   5 +
>  arch/arm64/boot/dts/marvell/Makefile               |   2 +
>  .../boot/dts/marvell/iap140-andromeda-box-edge.dts |  77 ++++++++
>  arch/arm64/boot/dts/marvell/iap140.dtsi            | 195 +++++++++++++++++++++
>  drivers/clk/Kconfig                                |   2 +-
>  drivers/mmc/host/Kconfig                           |   2 +-
>  drivers/tty/serial/Kconfig                         |   2 +-
>  8 files changed, 289 insertions(+), 3 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/marvell/iap140.txt
>  create mode 100644 arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
>  create mode 100644 arch/arm64/boot/dts/marvell/iap140.dtsi
>
> -- 
> 2.10.2
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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Re: [PATCH 0/4] ARM64: Initial Marvell IAP140 enablement

[Andreas Färber]

Hi Gregory,

Am 20.02.2017 um 14:17 schrieb Gregory CLEMENT:
>  On dim., févr. 19 2017, Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org> wrote:
> 
>> This mini-series adds initial support for the Marvell IAP140 SoC (aka PXA1908)
>> and the Andromeda Box Edge development board.
> 
> Given the name of the SoC (PXA1908) and the fact that you reuse driver
> related to PXA, for me these SoC is neither a mvebu nor a berlin SoC.

That matches my understanding.

> So
> just to avoid any misunderstanding, I don't mind being CC and possibly
> doing review but I don't plan to take this patch ( I don't think the
> berlin maintainer will do it too). 

Sure. There did not seem to be a MAINTAINERS-documented maintainer for
dts/marvell/Makefile, so I CC'ed both MVEBU and Berlin for review, in
addition to the unclear-to-me PXA vs. MMP separation.

I was unsure about the sort order used: Is it that Berlin was first and
therefore Berlin comes before Armada (then iap140 goes last), or is it
sorted by ARCH_? Becomes relevant below.

>> In order to enable the 8250 UART driver, it reuses ARCH_PXA; but some drivers
>> enabled with ARCH_PXA don't build due to arm assembly or arm64's lack of mach-,
>> so their dependencies need to be limited to ARM alongside (blacklisted). The
>> alternative would of course be to choose a new ARCH_ symbol and to selectively
>> add it to drivers known working (whitelisting). The latter would require
>> finding a suitable name.
> 
> For this kind of issue you can have a look on what we did when
> introducing mvebu SoC using ARM64.

This is how you introduced MVEBU for arm64:

http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=b4f596b19624d14864596b5b43de5f04cadd4895

There was a discussion with Jisheng on whether to use ARCH_ARMADA_3700,
but since I did not propose ARCH_IAP140 here, what are you suggesting
exactly? Berlin does not sound like a BU name either.

What I am reading out of the documentation Thomas pointed to is that
ARCH_MMP would be more correct than ARCH_PXA, despite the PXA1908 name.

MMP does help with driver compilation. Just for the OF earlycon I still
need the PXA compatible fallback, or we would need to define an MMP
earlycon. Since mmp2.dtsi does not use the pxa compatible, I'll look
into the latter for v2.

MMP sorts before MVEBU, unlike PXA.

So MMP would mean Eric and Haojian only - I will drop the other Marvell
maintainers for v2 then, except where review comments have been provided.

Regards,
Andreas

-- 
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GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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Re: [PATCH 0/4] ARM64: Initial Marvell IAP140 enablement

[Andrew Lunn]

> So MMP would mean Eric and Haojian only - I will drop the other Marvell
> maintainers for v2 then, except where review comments have been provided.

Hi Andreas

If you find there are any drivers shared by MVEBU and MMP, please do
Cc: us if you need to touch them. We have knowledge we can share.

    Andrew

Re: [PATCH 0/4] ARM64: Initial Marvell IAP140 enablement

[Robert Jarzmik]

Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org> writes:

> Hi Gregory,
>
> Am 20.02.2017 um 14:17 schrieb Gregory CLEMENT:
>>  On dim., févr. 19 2017, Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org> wrote:
>> 
>>> This mini-series adds initial support for the Marvell IAP140 SoC (aka PXA1908)
>>> and the Andromeda Box Edge development board.
>> 
>> Given the name of the SoC (PXA1908) and the fact that you reuse driver
>> related to PXA, for me these SoC is neither a mvebu nor a berlin SoC.
>
> That matches my understanding.

...zip...
> What I am reading out of the documentation Thomas pointed to is that
> ARCH_MMP would be more correct than ARCH_PXA, despite the PXA1908 name.
I agree here.

PXA for me are XScale micro-architecture based SoCs, quite old. PXA1908 has a
quite recent Cortex-A53 (or several of them), which makes me think its either an
MMP or something newer than MMP.

> MMP does help with driver compilation. Just for the OF earlycon I still
> need the PXA compatible fallback, or we would need to define an MMP
> earlycon. Since mmp2.dtsi does not use the pxa compatible, I'll look
> into the latter for v2.
>
> MMP sorts before MVEBU, unlike PXA.
>
> So MMP would mean Eric and Haojian only - I will drop the other Marvell
> maintainers for v2 then, except where review comments have been provided.
Yes please.

Cheers.

-- 
Robert
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