From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v5 1/7] arm64: allwinner: Kconfig: add essential pinctrl driver for H5 Date: Mon, 27 Feb 2017 09:25:14 +0100 Message-ID: <20170227082514.54umfltn5xmdcpv3@lukather> References: <20170226011956.53581-1-icenowy@aosc.xyz> <20170226011956.53581-2-icenowy@aosc.xyz> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="tkxmchuhxcbqiygm" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20170226011956.53581-2-icenowy-ymACFijhrKM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Rob Herring , Chen-Yu Tsai , Catalin Marinas , Will Deacon , Andre Przywara , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org --tkxmchuhxcbqiygm Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Sun, Feb 26, 2017 at 09:19:50AM +0800, Icenowy Zheng wrote: > H5 SoC has two pin controllers, one (in user manual called "CPUx") needs > a slightly advanced driver, and the other (called "CPUs") is just equal > to the on in H3, and the H3 driver can be just reused. > > Select the two necessary pinctrl drivers when building kernel for > Allwinner SoCs. > > Also add H5 in the option's description. > > Signed-off-by: Icenowy Zheng > --- > arch/arm64/Kconfig.platforms | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms > index 129cc5ae4091..81f0d6149c2e 100644 > --- a/arch/arm64/Kconfig.platforms > +++ b/arch/arm64/Kconfig.platforms > @@ -5,8 +5,11 @@ config ARCH_SUNXI > select GENERIC_IRQ_CHIP > select PINCTRL > select PINCTRL_SUN50I_A64 > + select PINCTRL_SUN50I_H5 > + select PINCTRL_SUN8I_H3_R Why not add those options as def_bool instead? Being able to remove them certainly have values if you want to strip them down. > help > - This enables support for Allwinner sunxi based SoCs like the A64. > + This enables support for Allwinner sunxi based SoCs like the A64 > + and H5. There's no point in having an ever growing list of SoCs here. You can just remove the mention of the A64. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --tkxmchuhxcbqiygm--