From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Horman Subject: Re: [PATCH 0/2] arm64: dts: renesas: Remove unit-addresses and regs from integrated caches Date: Mon, 6 Mar 2017 09:47:48 +0100 Message-ID: <20170306084747.GD11468@verge.net.au> References: <1488547097-4804-1-git-send-email-geert+renesas@glider.be> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1488547097-4804-1-git-send-email-geert+renesas@glider.be> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Geert Uytterhoeven Cc: Mark Rutland , devicetree@vger.kernel.org, Magnus Damm , linux-renesas-soc@vger.kernel.org, Rob Herring , Sudeep Holla , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org On Fri, Mar 03, 2017 at 02:18:15PM +0100, Geert Uytterhoeven wrote: > Hi Simon, Magnus, > > This patch series removes the bogus unit-addresses and reg properties > from the device nodes representing Cortex-A57/A53 cache controllers. > > Note that the latter were added to remove warnings from dtc when using > W=1: > > Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property > > In hindsight, adding the reg properties turned out to be the wrong fix. > Indeed, the Cortex-A57/A53 cache controllers are integrated controllers, > and thus the device nodes representing them should not have > unit-addresses or reg properties. > > This series does not have a runtime effect, as Linux doesn't rely much > on the properties of the cache-controller nodes. > > After this patch has been accepted, I'll submit a similar series to fix > the DTS files for the Renesas arm32 SoCs. Thanks, applied.