[PATCH 0/4] ARM: dm8168-evm: add SATA support

[PATCH 0/4] ARM: dm8168-evm: add SATA support

[Bartosz Golaszewski]

This series implements support for the on-board SATA controller
on the dm8168-evm board.

The first patch adds the clock domain and hwmod entries for the
SATA module.

The second patch models the external reference clock used by SATA.

The third adds the SATA node to the SoC's device tree.

The fourth enables the SATA driver by default in omap2plus_defconfig.

Bartosz Golaszewski (3):
  ARM: dts: dm8168-evm: add the external reference clock for SATA
  ARM: dts: dm8168-evm: add SATA node
  ARM: omap2plus_defconfig: enable ahci-dm816 module

Kevin Hilman (1):
  ARM: OMAP2+: dm81xx: Add clkdm and hwmod for SATA

 arch/arm/boot/dts/dm8168-evm.dts            | 10 +++++++++
 arch/arm/boot/dts/dm816x.dtsi               |  7 ++++++
 arch/arm/configs/omap2plus_defconfig        |  1 +
 arch/arm/mach-omap2/clockdomains81xx_data.c | 10 +++++++++
 arch/arm/mach-omap2/cm81xx.h                |  2 ++
 arch/arm/mach-omap2/omap_hwmod_81xx_data.c  | 34 +++++++++++++++++++++++++++++
 6 files changed, 64 insertions(+)

-- 
2.9.3

[PATCH 1/4] ARM: OMAP2+: dm81xx: Add clkdm and hwmod for SATA

[Bartosz Golaszewski]

From: Kevin Hilman <khilman@baylibre.com>

Add the SATA clockdomain (part of CM_DEFAULT) and a hwmod for the SATA
block on dm81xx.

Tested on DM8168 EVM.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 arch/arm/mach-omap2/clockdomains81xx_data.c | 10 +++++++++
 arch/arm/mach-omap2/cm81xx.h                |  2 ++
 arch/arm/mach-omap2/omap_hwmod_81xx_data.c  | 34 +++++++++++++++++++++++++++++
 3 files changed, 46 insertions(+)

diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
index 3b5fb05..65fbd13 100644
--- a/arch/arm/mach-omap2/clockdomains81xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
@@ -91,6 +91,14 @@ static struct clockdomain default_l3_slow_81xx_clkdm = {
 	.flags		= CLKDM_CAN_SWSUP,
 };
 
+static struct clockdomain default_sata_81xx_clkdm = {
+	.name		= "default_clkdm",
+	.pwrdm		= { .name = "default_pwrdm" },
+	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
+	.clkdm_offs	= TI816X_CM_DEFAULT_SATA_CLKDM,
+	.flags		= CLKDM_CAN_SWSUP,
+};
+
 /* 816x only */
 
 static struct clockdomain alwon_mpu_816x_clkdm = {
@@ -173,6 +181,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = {
 	&mmu_81xx_clkdm,
 	&mmu_cfg_81xx_clkdm,
 	&default_l3_slow_81xx_clkdm,
+	&default_sata_81xx_clkdm,
 	NULL,
 };
 
@@ -200,6 +209,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = {
 	&default_ducati_816x_clkdm,
 	&default_pci_816x_clkdm,
 	&default_l3_slow_81xx_clkdm,
+	&default_sata_81xx_clkdm,
 	NULL,
 };
 
diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
index 3a0ccf0..44ca275 100644
--- a/arch/arm/mach-omap2/cm81xx.h
+++ b/arch/arm/mach-omap2/cm81xx.h
@@ -35,6 +35,7 @@
 #define TI81XX_CM_MMU_CLKDM			0x000C
 #define TI81XX_CM_MMUCFG_CLKDM			0x0010
 #define TI81XX_CM_ALWON_MPU_CLKDM		0x001C
+#define TI81XX_CM_ALWON_SYSCLK5_CLKDM		0x0024
 #define TI81XX_CM_ALWON_L3_FAST_CLKDM		0x0030
 
 /* ACTIVE */
@@ -57,5 +58,6 @@
 #define TI816X_CM_DEFAULT_PCI_CLKDM		0x0010
 #define TI816X_CM_DEFAULT_L3_SLOW_CLKDM		0x0014
 #define TI816X_CM_DEFAULT_DUCATI_CLKDM		0x0018
+#define TI816X_CM_DEFAULT_SATA_CLKDM		0x0060
 
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index b82b77c..310afe4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -106,6 +106,7 @@
  */
 #define DM81XX_CM_DEFAULT_OFFSET	0x500
 #define DM81XX_CM_DEFAULT_USB_CLKCTRL	(0x558 - DM81XX_CM_DEFAULT_OFFSET)
+#define DM81XX_CM_DEFAULT_SATA_CLKCTRL	(0x560 - DM81XX_CM_DEFAULT_OFFSET)
 
 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
@@ -973,6 +974,38 @@ static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
 	.user		= OCP_USER_MPU,
 };
 
+static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
+	.sysc_offs	= 0x1100,
+	.sysc_flags	= SYSC_HAS_SIDLEMODE,
+	.idlemodes	= SIDLE_FORCE,
+	.sysc_fields	= &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
+	.name	= "sata",
+	.sysc	= &dm81xx_sata_sysc,
+};
+
+static struct omap_hwmod dm81xx_sata_hwmod = {
+	.name		= "sata",
+	.clkdm_name	= "default_sata_clkdm",
+	.flags		= HWMOD_NO_IDLEST,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+	.class		= &dm81xx_sata_hwmod_class,
+};
+
+static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
+	.master		= &dm81xx_l4_hs_hwmod,
+	.slave		= &dm81xx_sata_hwmod,
+	.clk		= "sysclk5_ck",
+	.user		= OCP_USER_MPU,
+};
+
 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
 	.rev_offs	= 0x0,
 	.sysc_offs	= 0x110,
@@ -1474,6 +1507,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
 	&dm81xx_l4_hs__emac0,
 	&dm81xx_emac0__mdio,
 	&dm816x_l4_hs__emac1,
+	&dm81xx_l4_hs__sata,
 	&dm81xx_alwon_l3_fast__tpcc,
 	&dm81xx_alwon_l3_fast__tptc0,
 	&dm81xx_alwon_l3_fast__tptc1,
-- 
2.9.3

Re: [PATCH 1/4] ARM: OMAP2+: dm81xx: Add clkdm and hwmod for SATA

[Kevin Hilman]

Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> writes:

> From: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>
> Add the SATA clockdomain (part of CM_DEFAULT) and a hwmod for the SATA
> block on dm81xx.
>
> Tested on DM8168 EVM.
>
> Signed-off-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
>  arch/arm/mach-omap2/clockdomains81xx_data.c | 10 +++++++++
>  arch/arm/mach-omap2/cm81xx.h                |  2 ++
>  arch/arm/mach-omap2/omap_hwmod_81xx_data.c  | 34 +++++++++++++++++++++++++++++
>  3 files changed, 46 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c
> index 3b5fb05..65fbd13 100644
> --- a/arch/arm/mach-omap2/clockdomains81xx_data.c
> +++ b/arch/arm/mach-omap2/clockdomains81xx_data.c
> @@ -91,6 +91,14 @@ static struct clockdomain default_l3_slow_81xx_clkdm = {
>  	.flags		= CLKDM_CAN_SWSUP,
>  };
>  
> +static struct clockdomain default_sata_81xx_clkdm = {
> +	.name		= "default_clkdm",
> +	.pwrdm		= { .name = "default_pwrdm" },
> +	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
> +	.clkdm_offs	= TI816X_CM_DEFAULT_SATA_CLKDM,
> +	.flags		= CLKDM_CAN_SWSUP,
> +};
> +
>  /* 816x only */
>  
>  static struct clockdomain alwon_mpu_816x_clkdm = {
> @@ -173,6 +181,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = {
>  	&mmu_81xx_clkdm,
>  	&mmu_cfg_81xx_clkdm,
>  	&default_l3_slow_81xx_clkdm,
> +	&default_sata_81xx_clkdm,
>  	NULL,
>  };
>  
> @@ -200,6 +209,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = {
>  	&default_ducati_816x_clkdm,
>  	&default_pci_816x_clkdm,
>  	&default_l3_slow_81xx_clkdm,
> +	&default_sata_81xx_clkdm,
>  	NULL,
>  };
>  
> diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h
> index 3a0ccf0..44ca275 100644
> --- a/arch/arm/mach-omap2/cm81xx.h
> +++ b/arch/arm/mach-omap2/cm81xx.h
> @@ -35,6 +35,7 @@
>  #define TI81XX_CM_MMU_CLKDM			0x000C
>  #define TI81XX_CM_MMUCFG_CLKDM			0x0010
>  #define TI81XX_CM_ALWON_MPU_CLKDM		0x001C
> +#define TI81XX_CM_ALWON_SYSCLK5_CLKDM		0x0024

oops, this is a stray addition (by me) but is no not needed.

>  #define TI81XX_CM_ALWON_L3_FAST_CLKDM		0x0030
>  

Kevin
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[PATCH 2/4] ARM: dts: dm8168-evm: add the external reference clock for SATA

[Bartosz Golaszewski]

This board has an external oscillator supplying the reference clock
signal for SATA. Its rate is fixed at 100Mhz. Add a corresponding
device tree node.

Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/dm8168-evm.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index 0bf55fa..f13e214 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -25,6 +25,12 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
+
+	sata_refclk: fixedclock0 {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+	};
 };
 
 &dm816x_pinmux {
-- 
2.9.3

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Re: [PATCH 2/4] ARM: dts: dm8168-evm: add the external reference clock for SATA

[Tony Lindgren]

* Bartosz Golaszewski <bgolaszewski@baylibre.com> [170313 09:45]:
> This board has an external oscillator supplying the reference clock
> signal for SATA. Its rate is fixed at 100Mhz. Add a corresponding
> device tree node.

Is this the 100MHz clock from PCIe? Just like on dm814x-evm as noted
in the workaround thread below:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/181083/671141

Regards,

Tony

> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
>  arch/arm/boot/dts/dm8168-evm.dts | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
> index 0bf55fa..f13e214 100644
> --- a/arch/arm/boot/dts/dm8168-evm.dts
> +++ b/arch/arm/boot/dts/dm8168-evm.dts
> @@ -25,6 +25,12 @@
>  		regulator-min-microvolt = <3300000>;
>  		regulator-max-microvolt = <3300000>;
>  	};
> +
> +	sata_refclk: fixedclock0 {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		clock-frequency = <100000000>;
> +	};
>  };
>  
>  &dm816x_pinmux {
> -- 
> 2.9.3
> 

Re: [PATCH 2/4] ARM: dts: dm8168-evm: add the external reference clock for SATA

[Bartosz Golaszewski]

2017-03-13 22:34 GMT+01:00 Tony Lindgren <tony@atomide.com>:
> * Bartosz Golaszewski <bgolaszewski@baylibre.com> [170313 09:45]:
>> This board has an external oscillator supplying the reference clock
>> signal for SATA. Its rate is fixed at 100Mhz. Add a corresponding
>> device tree node.
>
> Is this the 100MHz clock from PCIe? Just like on dm814x-evm as noted
> in the workaround thread below:
>
> http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/181083/671141
>
> Regards,
>
> Tony
>

Hi Tony,

these signals come from a TI CDCM61002 (U30 on the board's
schematics). It's hardwired to 100mHZ output.

Thanks,
Bartosz Golaszewski

Re: [PATCH 2/4] ARM: dts: dm8168-evm: add the external reference clock for SATA

[Tony Lindgren]

* Bartosz Golaszewski <bgolaszewski@baylibre.com> [170314 08:03]:
> 2017-03-13 22:34 GMT+01:00 Tony Lindgren <tony@atomide.com>:
> > * Bartosz Golaszewski <bgolaszewski@baylibre.com> [170313 09:45]:
> >> This board has an external oscillator supplying the reference clock
> >> signal for SATA. Its rate is fixed at 100Mhz. Add a corresponding
> >> device tree node.
> >
> > Is this the 100MHz clock from PCIe? Just like on dm814x-evm as noted
> > in the workaround thread below:
> >
> > http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/181083/671141
> >
> > Regards,
> >
> > Tony
> >
> 
> Hi Tony,
> 
> these signals come from a TI CDCM61002 (U30 on the board's
> schematics). It's hardwired to 100mHZ output.

Oh OK thanks.

Tony

[PATCH 3/4] ARM: dts: dm8168-evm: add SATA node

[Bartosz Golaszewski]

Add the SATA controller node to the dm8168-evm device tree.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 arch/arm/boot/dts/dm8168-evm.dts | 4 ++++
 arch/arm/boot/dts/dm816x.dtsi    | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index f13e214..547856e 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -179,3 +179,7 @@
 	pinctrl-0 = <&usb1_pins>;
 	mentor,multipoint = <0>;
 };
+
+&sata {
+	clocks = <&sysclk5_ck>, <&sata_refclk>;
+};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 276211e..6131081 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -293,6 +293,13 @@
 			phy-handle = <&phy1>;
 		};
 
+		sata: sata@4a140000 {
+			compatible = "ti,dm816-ahci";
+			reg = <0x4a140000 0xffff>;
+			interrupts = <16>;
+			ti,hwmods = "sata";
+		};
+
 		mcspi1: spi@48030000 {
 			compatible = "ti,omap4-mcspi";
 			reg = <0x48030000 0x1000>;
-- 
2.9.3

Re: [PATCH 3/4] ARM: dts: dm8168-evm: add SATA node

[Tony Lindgren]

* Bartosz Golaszewski <bgolaszewski@baylibre.com> [170313 09:45]:
> Add the SATA controller node to the dm8168-evm device tree.
> --- a/arch/arm/boot/dts/dm816x.dtsi
> +++ b/arch/arm/boot/dts/dm816x.dtsi
> @@ -293,6 +293,13 @@
>  			phy-handle = <&phy1>;
>  		};
>  
> +		sata: sata@4a140000 {
> +			compatible = "ti,dm816-ahci";
> +			reg = <0x4a140000 0xffff>;
> +			interrupts = <16>;
> +			ti,hwmods = "sata";
> +		};

The size should be 0x10000 instead of 0xffff, right?

Tony

Re: [PATCH 3/4] ARM: dts: dm8168-evm: add SATA node

[Sergei Shtylyov]

On 3/13/2017 7:43 PM, Bartosz Golaszewski wrote:

> Add the SATA controller node to the dm8168-evm device tree.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[...]
> diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
> index 276211e..6131081 100644
> --- a/arch/arm/boot/dts/dm816x.dtsi
> +++ b/arch/arm/boot/dts/dm816x.dtsi
> @@ -293,6 +293,13 @@
>  			phy-handle = <&phy1>;
>  		};
>
> +		sata: sata@4a140000 {
> +			compatible = "ti,dm816-ahci";
> +			reg = <0x4a140000 0xffff>;

    Again, 0x10000 for the size.

[...]

MBR, Sergei

[PATCH 4/4] ARM: omap2plus_defconfig: enable ahci-dm816 module

[Bartosz Golaszewski]

This is now supported on the dm8168-evm board, so enable it in
the defconfig for omap2+.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 arch/arm/configs/omap2plus_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index f2462a6..3944aa9 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -141,6 +141,7 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_DM816=m
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_ARC is not set
 # CONFIG_NET_CADENCE is not set
-- 
2.9.3