[PATCH v4 0/8] Add dual-role OTG support for Allwinner H3

[PATCH v4 0/8] Add dual-role OTG support for Allwinner H3

[Icenowy Zheng]

Allwinner H3 have a its USB PHY0 routed to two USB controllers: one is
a MUSB controller, which can work in peripheral mode, but works badly in
host mode (several hardware will fail on the MUSB controller, even connect
one MUSB controller in peripheral mode to another one in host mode cannot
work); the other is a pair of EHCI/OHCI controller, which can work only
in host mode, but have better compatibillity. The route is controlled in
a register, which we have set it to HCI only when we do not know about
it well.

Add support to route to the best controller according to current USB mode
(host/peripheral).

Note: Currently even if hardware only support hostmode, we should still
enable the MUSB controller, as it controls the USB mode. (Some this kind
of hardware can also work in peripheral mode by settings in the sysfs
node of MUSB, then connect it to another host via a USB Type-A to Type-A
cable.)

Patch 1 changes the device tree binding to include the "pmu0" for HCI pair.

Patch 2 and 3 are fixes for H3 PHY, in order to make MUSB really working
on H3.

Patch 4 adds support for auto routing of PHY0. It's currently only enabled
on H3, but it's easy to extend it to other SoCs which feature this
route control.

Patch 5 adds necessary device tree nodes to the H3/H5 DTSI file. Note: The
phy is not bind for OHCI/EHCI0, as OHCI/EHCI drivers will keep the VBUS
on. Only MUSB driver can properly handle a dual-role PHY.

Patch 6 enables USB OTG functionality on Orange Pi One board, which is
the only H3 board I have that have proper OTG function. It's easy to
enable OTG on other boards with their schematics.

Patch 7 enables USB OTG functionality on Orange Pi Zero board, as the
board cannot output power on Vbus, I only enabled peripheral mode by
default.

Patch 8 enables USB OTG funcionality on Orange Pi PC2 board, which is
the newly support H5 board, and have USB-related pins same as Orange
Pi One.

The USB PHY on V3s/A64 SoCs also feature this capability, and it will
be soon enabled on these SoCs after this patchset is merged.

Icenowy Zheng (8):
  dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
  phy: sun4i-usb: change PHYCTL register clearing code
  phy: sun4i-usb: add PHYCTL offset for H3 SoC
  phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI
  ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
  ARM: sun8i: h3: enable USB OTG on Orange Pi One
  ARM: sun8i: h2+: enable USB OTG for Orange Pi Zero board
  arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board

 .../devicetree/bindings/phy/sun4i-usb-phy.txt      |  1 +
 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts  | 20 +++++++-
 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts        | 22 ++++++++-
 arch/arm/boot/dts/sunxi-h3-h5.dtsi                 | 32 ++++++++++++
 .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 27 +++++++++-
 drivers/phy/phy-sun4i-usb.c                        | 57 ++++++++++++++--------
 6 files changed, 135 insertions(+), 24 deletions(-)

-- 
2.12.0

[PATCH v4 1/8] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

[Icenowy Zheng]

Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.

When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.

Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index e42334258185..005bc22938ff 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -15,6 +15,7 @@ Required properties:
 - reg : a list of offset + length pairs
 - reg-names :
   * "phy_ctrl"
+  * "pmu0" for H3, V3s and A64
   * "pmu1"
   * "pmu2" for sun4i, sun6i or sun7i
 - #phy-cells : from the generic phy bindings, must be 1
-- 
2.12.0

Re: [PATCH v4 1/8] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

[Chen-Yu Tsai]

On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
> controllers: one is MUSB and the other is a EHCI/OHCI pair.
>
> When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
> tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
>
> Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>

Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Please keep acks and review tags from others if you haven't changed the
patch.

[PATCH v4 2/8] phy: sun4i-usb: change PHYCTL register clearing code

[Icenowy Zheng]

It seems that all SoCs after A33 (including A33) need the PHYCTL
register to be cleared before writing to it. These SoCs all have another
feature: PHYCTL register is at 0x10, not 0x04.

Change PHYCTL register clearing code to judge whether clearing is needed
based on the PHYCTL offset.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
New patch in v4.

 drivers/phy/phy-sun4i-usb.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index a21b5f24a340..62b4d25448c6 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -188,10 +188,8 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
 
 	spin_lock_irqsave(&phy_data->reg_lock, flags);
 
-	if (phy_data->cfg->type == sun8i_a33_phy ||
-	    phy_data->cfg->type == sun50i_a64_phy ||
-	    phy_data->cfg->type == sun8i_v3s_phy) {
-		/* A33 or A64 needs us to set phyctl to 0 explicitly */
+	if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
+		/* SoCs newer than A33 need us to set phyctl to 0 explicitly */
 		writel(0, phyctl);
 	}
 
-- 
2.12.0

Re: [PATCH v4 2/8] phy: sun4i-usb: change PHYCTL register clearing code

[Chen-Yu Tsai]

On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
> It seems that all SoCs after A33 (including A33) need the PHYCTL
> register to be cleared before writing to it. These SoCs all have another
> feature: PHYCTL register is at 0x10, not 0x04.

As mentioned in the other patch, the basis for this description is
wrong. Just state that, among all the currently supported SoCs, when
PHYCTL is at 0x10, the register must be cleared before writing to it.

This would match what the logic in your patch means. Please also
update the comment.

ChenYu

>
> Change PHYCTL register clearing code to judge whether clearing is needed
> based on the PHYCTL offset.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
> New patch in v4.
>
>  drivers/phy/phy-sun4i-usb.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index a21b5f24a340..62b4d25448c6 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -188,10 +188,8 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
>
>         spin_lock_irqsave(&phy_data->reg_lock, flags);
>
> -       if (phy_data->cfg->type == sun8i_a33_phy ||
> -           phy_data->cfg->type == sun50i_a64_phy ||
> -           phy_data->cfg->type == sun8i_v3s_phy) {
> -               /* A33 or A64 needs us to set phyctl to 0 explicitly */
> +       if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
> +               /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
>                 writel(0, phyctl);
>         }
>
> --
> 2.12.0
>
> --
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[PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

[Icenowy Zheng]

The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
register offset missing.

Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
New patch in v4.

 drivers/phy/phy-sun4i-usb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 62b4d25448c6..a650f283f6ff 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.num_phys = 4,
 	.type = sun8i_h3_phy,
 	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 };
-- 
2.12.0

Re: [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

[Chen-Yu Tsai]

On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
> The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
> register offset missing.
>
> Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.

You are implying that all SoCs after A33 have PHYCTL at 0x10.

This is not true. As the A83T, which was released after the A33, has
PHYCTL at the old offset.

Just state that H3 has PHYCTL at 0x10.

ChenYu

> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
> New patch in v4.
>
>  drivers/phy/phy-sun4i-usb.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index 62b4d25448c6..a650f283f6ff 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
>         .num_phys = 4,
>         .type = sun8i_h3_phy,
>         .disc_thresh = 3,
> +       .phyctl_offset = REG_PHYCTL_A33,
>         .dedicated_clocks = true,
>         .enable_pmu_unk1 = true,
>  };
> --
> 2.12.0
>
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Re: [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

[Icenowy Zheng]

24.03.2017, 11:05, "Chen-Yu Tsai" <wens-jdAy2FN1RRM@public.gmane.org>:
> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
>>  The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>>  register offset missing.
>>
>>  Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
>
> You are implying that all SoCs after A33 have PHYCTL at 0x10.
>
> This is not true. As the A83T, which was released after the A33, has
> PHYCTL at the old offset.

No, in Allwinner's BSP A83T is using also PHYCTL at 0x10.

The code in linux-3.4/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
```
#if defined (CONFIG_ARCH_SUN8IW5) || defined (CONFIG_ARCH_SUN8IW6) || defined (CONFIG_ARCH_SUN8IW9) || defined (CONFIG_ARCH_SUN8IW8) || defined (CONFIG_ARCH_SUN8IW7)
#define  USBPHYC_REG_o_PHYCTL		    0x0410
#else
#define  USBPHYC_REG_o_PHYCTL		    0x0404
#endif
```

In linux-3.10/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
```
#if defined (CONFIG_ARCH_SUN50I) || defined (CONFIG_ARCH_SUN8IW10) || defined (CONFIG_ARCH_SUN8IW11)
#define  USBPHYC_REG_o_PHYCTL		    0x0410
#else
#define  USBPHYC_REG_o_PHYCTL		    0x0404
#endif
```

So sun50i* and sun50iw5~w11 all use PHYCTL at 0x10.

>
> Just state that H3 has PHYCTL at 0x10.
>
> ChenYu
>
>>  Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>  ---
>>  New patch in v4.
>>
>>   drivers/phy/phy-sun4i-usb.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>>  diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
>>  index 62b4d25448c6..a650f283f6ff 100644
>>  --- a/drivers/phy/phy-sun4i-usb.c
>>  +++ b/drivers/phy/phy-sun4i-usb.c
>>  @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
>>          .num_phys = 4,
>>          .type = sun8i_h3_phy,
>>          .disc_thresh = 3,
>>  + .phyctl_offset = REG_PHYCTL_A33,
>>          .dedicated_clocks = true,
>>          .enable_pmu_unk1 = true,
>>   };
>>  --
>>  2.12.0
>>
>>  --
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>
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Re: [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

[Chen-Yu Tsai]

On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
>
>
> 24.03.2017, 11:05, "Chen-Yu Tsai" <wens-jdAy2FN1RRM@public.gmane.org>:
>> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
>>>  The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>>>  register offset missing.
>>>
>>>  Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
>>
>> You are implying that all SoCs after A33 have PHYCTL at 0x10.
>>
>> This is not true. As the A83T, which was released after the A33, has
>> PHYCTL at the old offset.
>
> No, in Allwinner's BSP A83T is using also PHYCTL at 0x10.
>
> The code in linux-3.4/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
> ```
> #if defined (CONFIG_ARCH_SUN8IW5) || defined (CONFIG_ARCH_SUN8IW6) || defined (CONFIG_ARCH_SUN8IW9) || defined (CONFIG_ARCH_SUN8IW8) || defined (CONFIG_ARCH_SUN8IW7)
> #define  USBPHYC_REG_o_PHYCTL               0x0410
> #else
> #define  USBPHYC_REG_o_PHYCTL               0x0404
> #endif
> ```
>
> In linux-3.10/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
> ```
> #if defined (CONFIG_ARCH_SUN50I) || defined (CONFIG_ARCH_SUN8IW10) || defined (CONFIG_ARCH_SUN8IW11)
> #define  USBPHYC_REG_o_PHYCTL               0x0410
> #else
> #define  USBPHYC_REG_o_PHYCTL               0x0404
> #endif
> ```
>
> So sun50i* and sun50iw5~w11 all use PHYCTL at 0x10.
>

Seems you are right. However I think it's best to not assume or infer
anything. Who knows, Allwinner might re-release some old SoC under a
different under a different name again.

Just state the facts: H3 has its PHYCTL at 0x10.

ChenYu

>>
>> Just state that H3 has PHYCTL at 0x10.
>>
>> ChenYu
>>
>>>  Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>>  ---
>>>  New patch in v4.
>>>
>>>   drivers/phy/phy-sun4i-usb.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>>  diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
>>>  index 62b4d25448c6..a650f283f6ff 100644
>>>  --- a/drivers/phy/phy-sun4i-usb.c
>>>  +++ b/drivers/phy/phy-sun4i-usb.c
>>>  @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
>>>          .num_phys = 4,
>>>          .type = sun8i_h3_phy,
>>>          .disc_thresh = 3,
>>>  + .phyctl_offset = REG_PHYCTL_A33,
>>>          .dedicated_clocks = true,
>>>          .enable_pmu_unk1 = true,
>>>   };
>>>  --
>>>  2.12.0
>>>
>>>  --
>>>  You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
>>>  To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
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>>
>> --
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>
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Re: [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

[Icenowy Zheng]

24.03.2017, 14:56, "Chen-Yu Tsai" <wens-jdAy2FN1RRM@public.gmane.org>:
> On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
>>  24.03.2017, 11:05, "Chen-Yu Tsai" <wens-jdAy2FN1RRM@public.gmane.org>:
>>>  On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
>>>>   The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>>>>   register offset missing.
>>>>
>>>>   Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
>>>
>>>  You are implying that all SoCs after A33 have PHYCTL at 0x10.
>>>
>>>  This is not true. As the A83T, which was released after the A33, has
>>>  PHYCTL at the old offset.
>>
>>  No, in Allwinner's BSP A83T is using also PHYCTL at 0x10.
>>
>>  The code in linux-3.4/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
>>  ```
>>  #if defined (CONFIG_ARCH_SUN8IW5) || defined (CONFIG_ARCH_SUN8IW6) || defined (CONFIG_ARCH_SUN8IW9) || defined (CONFIG_ARCH_SUN8IW8) || defined (CONFIG_ARCH_SUN8IW7)
>>  #define USBPHYC_REG_o_PHYCTL 0x0410
>>  #else
>>  #define USBPHYC_REG_o_PHYCTL 0x0404
>>  #endif
>>  ```
>>
>>  In linux-3.10/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
>>  ```
>>  #if defined (CONFIG_ARCH_SUN50I) || defined (CONFIG_ARCH_SUN8IW10) || defined (CONFIG_ARCH_SUN8IW11)
>>  #define USBPHYC_REG_o_PHYCTL 0x0410
>>  #else
>>  #define USBPHYC_REG_o_PHYCTL 0x0404
>>  #endif
>>  ```
>>
>>  So sun50i* and sun50iw5~w11 all use PHYCTL at 0x10.
>
> Seems you are right. However I think it's best to not assume or infer
> anything. Who knows, Allwinner might re-release some old SoC under a
> different under a different name again.
>
> Just state the facts: H3 has its PHYCTL at 0x10.

OK. Thanks ;-)

>
> ChenYu
>
>>>  Just state that H3 has PHYCTL at 0x10.
>>>
>>>  ChenYu
>>>
>>>>   Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>>>   ---
>>>>   New patch in v4.
>>>>
>>>>    drivers/phy/phy-sun4i-usb.c | 1 +
>>>>    1 file changed, 1 insertion(+)
>>>>
>>>>   diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
>>>>   index 62b4d25448c6..a650f283f6ff 100644
>>>>   --- a/drivers/phy/phy-sun4i-usb.c
>>>>   +++ b/drivers/phy/phy-sun4i-usb.c
>>>>   @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
>>>>           .num_phys = 4,
>>>>           .type = sun8i_h3_phy,
>>>>           .disc_thresh = 3,
>>>>   + .phyctl_offset = REG_PHYCTL_A33,
>>>>           .dedicated_clocks = true,
>>>>           .enable_pmu_unk1 = true,
>>>>    };
>>>>   --
>>>>   2.12.0
>>>>
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[PATCH v4 4/8] phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI

[Icenowy Zheng]

On newer Allwinner SoCs (H3 and after), the PHY0 node is routed to both
MUSB controller for peripheral and host support (the host support is
slightly broken), and a pair of EHCI/OHCI controllers, which provide a
better support for host mode.

Add support for automatically switch the route of PHY0 according to the
status of dr_mode and id det pin.

Only H3 have this function enabled in this patch, as further SoCs will
be tested later and then have it enabled.

As H5 is reusing the PHY driver of H3, this function is also enabled.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
---
Changes in v3:
- Add Chen-Yu's ACK. (I made a patch 1 that changes dt binding)
Changes in v2:
- Re-route after force session end.
- Drop id_det based on role code in reroute function, as we already
  properly set id_det in id_det getting function.

 drivers/phy/phy-sun4i-usb.c | 50 ++++++++++++++++++++++++++++++---------------
 1 file changed, 33 insertions(+), 17 deletions(-)

diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index a650f283f6ff..f86a2574b953 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -49,12 +49,14 @@
 #define REG_PHYBIST			0x08
 #define REG_PHYTUNE			0x0c
 #define REG_PHYCTL_A33			0x10
-#define REG_PHY_UNK_H3			0x20
+#define REG_PHY_OTGCTL			0x20
 
 #define REG_PMU_UNK1			0x10
 
 #define PHYCTL_DATA			BIT(7)
 
+#define OTGCTL_ROUTE_MUSB		BIT(0)
+
 #define SUNXI_AHB_ICHR8_EN		BIT(10)
 #define SUNXI_AHB_INCR4_BURST_EN	BIT(9)
 #define SUNXI_AHB_INCRX_ALIGN_EN	BIT(8)
@@ -110,6 +112,7 @@ struct sun4i_usb_phy_cfg {
 	u8 phyctl_offset;
 	bool dedicated_clocks;
 	bool enable_pmu_unk1;
+	bool phy0_dual_route;
 };
 
 struct sun4i_usb_phy_data {
@@ -269,23 +272,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 		writel(val & ~2, phy->pmu + REG_PMU_UNK1);
 	}
 
-	if (data->cfg->type == sun8i_h3_phy) {
-		if (phy->index == 0) {
-			val = readl(data->base + REG_PHY_UNK_H3);
-			writel(val & ~1, data->base + REG_PHY_UNK_H3);
-		}
-	} else {
-		/* Enable USB 45 Ohm resistor calibration */
-		if (phy->index == 0)
-			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
+	/* Enable USB 45 Ohm resistor calibration */
+	if (phy->index == 0)
+		sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
 
-		/* Adjust PHY's magnitude and rate */
-		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
+	/* Adjust PHY's magnitude and rate */
+	sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
 
-		/* Disconnect threshold adjustment */
-		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
-				    data->cfg->disc_thresh, 2);
-	}
+	/* Disconnect threshold adjustment */
+	sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
+			    data->cfg->disc_thresh, 2);
 
 	sun4i_usb_phy_passby(phy, 1);
 
@@ -484,6 +480,21 @@ static const struct phy_ops sun4i_usb_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
+{
+	u32 regval;
+
+	regval = readl(data->base + REG_PHY_OTGCTL);
+	if (id_det == 0) {
+		/* Host mode. Route phy0 to EHCI/OHCI */
+		regval &= ~OTGCTL_ROUTE_MUSB;
+	} else {
+		/* Peripheral mode. Route phy0 to MUSB */
+		regval |= OTGCTL_ROUTE_MUSB;
+	}
+	writel(regval, data->base + REG_PHY_OTGCTL);
+}
+
 static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
 {
 	struct sun4i_usb_phy_data *data =
@@ -544,6 +555,10 @@ static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
 			sun4i_usb_phy0_set_vbus_detect(phy0, 1);
 			mutex_unlock(&phy0->mutex);
 		}
+
+		/* Re-route PHY0 if necessary */
+		if (data->cfg->phy0_dual_route)
+			sun4i_usb_phy0_reroute(data, id_det);
 	}
 
 	if (vbus_notify)
@@ -698,7 +713,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 			return PTR_ERR(phy->reset);
 		}
 
-		if (i) { /* No pmu for usbc0 */
+		if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
 			snprintf(name, sizeof(name), "pmu%d", i);
 			res = platform_get_resource_byname(pdev,
 							IORESOURCE_MEM, name);
@@ -824,6 +839,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
 	.phyctl_offset = REG_PHYCTL_A33,
 	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
+	.phy0_dual_route = true,
 };
 
 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
-- 
2.12.0