From: Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: "Bean Huo (beanhuo)" <beanhuo-AL4WhLSQfzjQT0dZR+AlfA@public.gmane.org>
Cc: Thomas Petazzoni
<thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
"richard-/L3Ra7n9ekc@public.gmane.org"
<richard-/L3Ra7n9ekc@public.gmane.org>,
"marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org"
<marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Cyrille Pitchen
<cyrille.pitchen-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>,
"computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org"
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
<linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
"pawel.moll-5wv7dgnIgG8@public.gmane.org"
<pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
"galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org"
<galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Subject: Re: [PATCH 4/5] mtd: nand: add support for Micron on-die ECC
Date: Wed, 22 Mar 2017 15:52:16 +0100 [thread overview]
Message-ID: <20170322155216.319efc3e@bbrezillon> (raw)
In-Reply-To: <0dccc0abcf234e98be6d340027cf1a30-aBoyCxvc2dBaXkNJqdKpEhSpLNRU/VIH@public.gmane.org>
> >> I noticed that this patches are based on MT29F1G08ABADAWP SLC NAND, it is
> >our 60s 34nm SLC NAND.
> >> So far, we have 2 series SLC NAND with implementations of on die ECC.
> >> 1. M79A for all 25nm (70series) SLC NAND with on-die ECC (M78A, M79A,
> >> and future design M70A) 2. M60A for all 34nm (60series) SLC NAND with
> >> on-die ECC
> >
> >Do you have an easy way to differentiate those 2 generations of chip, or should
> >we base our detection on the model name provided in the ONFI parameter page?
> >
> Of course, you can use model name, but I think we will keep a big table to include every NAND information.
> Also, it doesn't look nice and always changes.
>
> The better solution is:
>
> For the Micron SLC NAND with on Die ECC, please note only for the "SLC NAND with on Die ECC",
> You can always differentiate these two generation NAND by ONFI table byte 112 "Number of bits
> ECC correctability ", if its value is 4, it is 60s; if it's 8, it is 70s. this is a permanent method for both
> 60s and 70s "SLC NAND with on Die ECC".
The question is, how can we know if the NAND supports on-die ECC?
We were basing our detection on the "Internal ECC" bit in READ_ID, but
it seems this bit is actually reflecting the current ECC engine status
(enabled/disabled), which is disturbing, since information returned by
the READ_ID are supposed to be static :-(.
>
> >>
> >> NAND_STATUS_FAIL:
> >> For the both of series SLC NAND with on-die ECC, SR bit 0
> >> (NAND_STATUS_FAIL) indicates an uncorrectable read fail, data is lost,
> >> no recovery possible, unless we have software additional protection, the block
> >is not necessarily bad but the data is lost.
> >>
> >> NAND_STATUS_WRITE_RECOMMENDED:
> >>
> >> For the NAND_STATUS_WRITE_RECOMMENDED, it only works on 60s NAND, it
> >> is 4 bit ECC, the status register only indicates if there is 0 or 1-4 correctable
> >error bits. We don't want to trigger refresh if only 1 or 2 bits fail.
> >> the base refresh is that if there 3 or 4 bitflips. But unfortunately we can't get
> >failed bit count trough read status register.
> >> SW workaround proposal:
> >> 1. If SR bit 3 is set to 1 it means 1~4 bitflips and correctable.
> >> 2. Read out the page with ECC ON
> >> 3. Read out the page with ECC OFF
> >> 4. Compare the data
> >> 5. Count the number of bitflips for the sectors (there are 4 ECC
> >> sectors) 6. if 3 or more fail bits, trigger fresh.
> >> I know this is not good solution, but if as long as
> >> NAND_STATUS_WRITE_RECOMMENDED is set, and trigger refresh, this will
> >definitely increase NAND PE cycle.
> >
> >We discussed that with Thomas when developing the solution. I suggested to first
> >go for a simple solution even if it implies unneeded PE cycles when bitflips are
> >detected, but maybe I was wrong. In any case, it shouldn't be to hard to do what
> >you suggest.
> >
>
> Ok, but I recommend that 70s should be the first choice on this single solution,
> it doesn't need to read twice to detect its bitflips count.
That's exactly why we need to differentiate the 2 chips.
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next prev parent reply other threads:[~2017-03-22 14:52 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <538805ebf8e64015a8b833de755652b3@SIWEX5A.sing.micron.com>
[not found] ` <538805ebf8e64015a8b833de755652b3-aBoyCxvc2dBaXkNJqdKpEhSpLNRU/VIH@public.gmane.org>
2017-03-22 13:20 ` [PATCH 4/5] mtd: nand: add support for Micron on-die ECC Bean Huo (beanhuo)
[not found] ` <8a171dacd20c45bd8285ecc5dbe8854a-aBoyCxvc2dBaXkNJqdKpEhSpLNRU/VIH@public.gmane.org>
2017-03-22 13:45 ` Boris Brezillon
2017-03-22 14:39 ` Bean Huo (beanhuo)
[not found] ` <0dccc0abcf234e98be6d340027cf1a30-aBoyCxvc2dBaXkNJqdKpEhSpLNRU/VIH@public.gmane.org>
2017-03-22 14:52 ` Boris Brezillon [this message]
2017-03-22 17:11 ` Bean Huo (beanhuo)
2017-04-03 11:31 ` Bean Huo (beanhuo)
[not found] ` <414dd35931814ce38381a251917ad79f-aBoyCxvc2dBaXkNJqdKpEhSpLNRU/VIH@public.gmane.org>
2017-04-11 12:51 ` Boris Brezillon
2017-04-11 14:26 ` Bean Huo (beanhuo)
[not found] ` <106593e04c494120b323836b8bc54f7f-aBoyCxvc2dBaXkNJqdKpEhSpLNRU/VIH@public.gmane.org>
2017-04-11 14:49 ` Boris Brezillon
2017-04-11 15:10 ` Boris Brezillon
2017-04-11 15:28 ` Bean Huo (beanhuo)
2017-04-11 15:02 ` Bean Huo (beanhuo)
[not found] ` <90300f14cd2a4ae6967d8be0f7dff4e9-aBoyCxvc2dBaXkNJqdKpEhSpLNRU/VIH@public.gmane.org>
2017-04-11 15:30 ` Boris Brezillon
2017-04-11 17:01 ` Bean Huo (beanhuo)
[not found] ` <5a96e73ef951414a82c01b67088b24d3-aBoyCxvc2dBaXkNJqdKpEhSpLNRU/VIH@public.gmane.org>
2017-04-12 7:03 ` Boris Brezillon
2017-04-13 14:08 ` Bean Huo (beanhuo)
2017-03-21 10:38 [PATCH 0/5] mtd: nand: add support for " Thomas Petazzoni
[not found] ` <1490092686-16509-1-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-03-21 10:38 ` [PATCH 4/5] mtd: nand: add support for Micron " Thomas Petazzoni
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