[PATCH] arm64: dts: ls1012a: add crypto node

[PATCH] arm64: dts: ls1012a: add crypto node

[Horia Geantă]

LS1012A has a SEC v5.4 security engine.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts |  9 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  |  9 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  |  9 +++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi     | 91 +++++++++++++++++++++-
 4 files changed, 117 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
index a619f6496a4c..bab9e68947e4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
@@ -49,6 +49,15 @@
 	model = "LS1012A Freedom Board";
 	compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
 
+	aliases {
+		crypto = &crypto;
+		rtic_a = &rtic_a;
+		rtic_b = &rtic_b;
+		rtic_c = &rtic_c;
+		rtic_d = &rtic_d;
+		sec_mon = &sec_mon;
+	};
+
 	sys_mclk: clock-mclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
index 14a67f1709e7..5c4e84c7f20d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
@@ -49,6 +49,15 @@
 	model = "LS1012A QDS Board";
 	compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
 
+	aliases {
+		crypto = &crypto;
+		rtic_a = &rtic_a;
+		rtic_b = &rtic_b;
+		rtic_c = &rtic_c;
+		rtic_d = &rtic_d;
+		sec_mon = &sec_mon;
+	};
+
 	sys_mclk: clock-mclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
index 62c5c7123a15..ff9dd16aa65a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
@@ -48,6 +48,15 @@
 / {
 	model = "LS1012A RDB Board";
 	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+	aliases {
+		crypto = &crypto;
+		rtic_a = &rtic_a;
+		rtic_b = &rtic_b;
+		rtic_c = &rtic_c;
+		rtic_d = &rtic_d;
+		sec_mon = &sec_mon;
+	};
 };
 
 &duart0 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index cffebb4b3df1..68f3012ae07e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -42,7 +42,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
 	compatible = "fsl,ls1012a";
@@ -113,6 +113,95 @@
 			big-endian;
 		};
 
+		crypto: crypto@1700000 {
+			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+				     "fsl,sec-v4.0";
+			fsl,sec-era = <8>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x1700000 0x100000>;
+			reg = <0x00 0x1700000 0x0 0x100000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			rtic@60000 {
+				compatible = "fsl,sec-v5.4-rtic",
+					     "fsl,sec-v5.0-rtic",
+					     "fsl,sec-v4.0-rtic";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x60000 0x100 0x60e00 0x18>;
+				ranges = <0x0 0x60100 0x500>;
+
+				rtic_a: rtic-a@0 {
+					compatible = "fsl,sec-v5.4-rtic-memory",
+						     "fsl,sec-v5.0-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x00 0x20 0x100 0x100>;
+				};
+
+				rtic_b: rtic-b@20 {
+					compatible = "fsl,sec-v5.4-rtic-memory",
+						     "fsl,sec-v5.0-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x20 0x20 0x200 0x100>;
+				};
+
+				rtic_c: rtic-c@40 {
+					compatible = "fsl,sec-v5.4-rtic-memory",
+						     "fsl,sec-v5.0-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x40 0x20 0x300 0x100>;
+				};
+
+				rtic_d: rtic-d@60 {
+					compatible = "fsl,sec-v5.4-rtic-memory",
+						     "fsl,sec-v5.0-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x60 0x20 0x400 0x100>;
+				};
+			};
+		};
+
+		sec_mon: sec_mon@1e90000 {
+			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
+				     "fsl,sec-v4.0-mon";
+			reg = <0x0 0x1e90000 0x0 0x10000>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1012a-dcfg",
 				     "syscon";
-- 
2.12.0.264.gd6db3f216544


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Re: [PATCH] arm64: dts: ls1012a: add crypto node

[Shawn Guo]

On Wed, Mar 22, 2017 at 02:29:39PM +0200, Horia Geantă wrote:
> LS1012A has a SEC v5.4 security engine.
> 
> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts |  9 +++
>  arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  |  9 +++
>  arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  |  9 +++
>  arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi     | 91 +++++++++++++++++++++-
>  4 files changed, 117 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> index a619f6496a4c..bab9e68947e4 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> @@ -49,6 +49,15 @@
>  	model = "LS1012A Freedom Board";
>  	compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
>  
> +	aliases {
> +		crypto = &crypto;
> +		rtic_a = &rtic_a;
> +		rtic_b = &rtic_b;
> +		rtic_c = &rtic_c;
> +		rtic_d = &rtic_d;
> +		sec_mon = &sec_mon;
> +	};
> +
>  	sys_mclk: clock-mclk {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> index 14a67f1709e7..5c4e84c7f20d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> @@ -49,6 +49,15 @@
>  	model = "LS1012A QDS Board";
>  	compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
>  
> +	aliases {
> +		crypto = &crypto;
> +		rtic_a = &rtic_a;
> +		rtic_b = &rtic_b;
> +		rtic_c = &rtic_c;
> +		rtic_d = &rtic_d;
> +		sec_mon = &sec_mon;
> +	};
> +
>  	sys_mclk: clock-mclk {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> index 62c5c7123a15..ff9dd16aa65a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> @@ -48,6 +48,15 @@
>  / {
>  	model = "LS1012A RDB Board";
>  	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
> +
> +	aliases {
> +		crypto = &crypto;
> +		rtic_a = &rtic_a;
> +		rtic_b = &rtic_b;
> +		rtic_c = &rtic_c;
> +		rtic_d = &rtic_d;
> +		sec_mon = &sec_mon;
> +	};

What are these aliases used for?  Are they board specific?  If not, we
should probably have them in fsl-ls1012a.dtsi, since you are adding
them for all three fsl-ls1012a based boards.

>  };
>  
>  &duart0 {
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> index cffebb4b3df1..68f3012ae07e 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> @@ -42,7 +42,7 @@
>   *     OTHER DEALINGS IN THE SOFTWARE.
>   */
>  
> -#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>  
>  / {
>  	compatible = "fsl,ls1012a";
> @@ -113,6 +113,95 @@
>  			big-endian;
>  		};
>  
> +		crypto: crypto@1700000 {
> +			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
> +				     "fsl,sec-v4.0";
> +			fsl,sec-era = <8>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x00 0x1700000 0x100000>;
> +			reg = <0x00 0x1700000 0x0 0x100000>;
> +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			sec_jr0: jr@10000 {
> +				compatible = "fsl,sec-v5.4-job-ring",
> +					     "fsl,sec-v5.0-job-ring",
> +					     "fsl,sec-v4.0-job-ring";
> +				reg	   = <0x10000 0x10000>;
> +				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr1: jr@20000 {
> +				compatible = "fsl,sec-v5.4-job-ring",
> +					     "fsl,sec-v5.0-job-ring",
> +					     "fsl,sec-v4.0-job-ring";
> +				reg	   = <0x20000 0x10000>;
> +				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr2: jr@30000 {
> +				compatible = "fsl,sec-v5.4-job-ring",
> +					     "fsl,sec-v5.0-job-ring",
> +					     "fsl,sec-v4.0-job-ring";
> +				reg	   = <0x30000 0x10000>;
> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			sec_jr3: jr@40000 {
> +				compatible = "fsl,sec-v5.4-job-ring",
> +					     "fsl,sec-v5.0-job-ring",
> +					     "fsl,sec-v4.0-job-ring";
> +				reg	   = <0x40000 0x10000>;
> +				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			rtic@60000 {
> +				compatible = "fsl,sec-v5.4-rtic",
> +					     "fsl,sec-v5.0-rtic",
> +					     "fsl,sec-v4.0-rtic";
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				reg = <0x60000 0x100 0x60e00 0x18>;
> +				ranges = <0x0 0x60100 0x500>;
> +
> +				rtic_a: rtic-a@0 {
> +					compatible = "fsl,sec-v5.4-rtic-memory",
> +						     "fsl,sec-v5.0-rtic-memory",
> +						     "fsl,sec-v4.0-rtic-memory";
> +					reg = <0x00 0x20 0x100 0x100>;
> +				};
> +
> +				rtic_b: rtic-b@20 {
> +					compatible = "fsl,sec-v5.4-rtic-memory",
> +						     "fsl,sec-v5.0-rtic-memory",
> +						     "fsl,sec-v4.0-rtic-memory";
> +					reg = <0x20 0x20 0x200 0x100>;
> +				};
> +
> +				rtic_c: rtic-c@40 {
> +					compatible = "fsl,sec-v5.4-rtic-memory",
> +						     "fsl,sec-v5.0-rtic-memory",
> +						     "fsl,sec-v4.0-rtic-memory";
> +					reg = <0x40 0x20 0x300 0x100>;
> +				};
> +
> +				rtic_d: rtic-d@60 {
> +					compatible = "fsl,sec-v5.4-rtic-memory",
> +						     "fsl,sec-v5.0-rtic-memory",
> +						     "fsl,sec-v4.0-rtic-memory";
> +					reg = <0x60 0x20 0x400 0x100>;
> +				};
> +			};
> +		};
> +
> +		sec_mon: sec_mon@1e90000 {

Hyphen is more preferred to be used in node name than underscore.

Shawn

> +			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
> +				     "fsl,sec-v4.0-mon";
> +			reg = <0x0 0x1e90000 0x0 0x10000>;
> +			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
>  		dcfg: dcfg@1ee0000 {
>  			compatible = "fsl,ls1012a-dcfg",
>  				     "syscon";
> -- 
> 2.12.0.264.gd6db3f216544
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH] arm64: dts: ls1012a: add crypto node

[Horia Geantă]

On 3/24/2017 3:56 AM, Shawn Guo wrote:
> On Wed, Mar 22, 2017 at 02:29:39PM +0200, Horia Geantă wrote:
>> LS1012A has a SEC v5.4 security engine.
>>
>> Signed-off-by: Horia Geantă <horia.geanta-3arQi8VN3Tc@public.gmane.org>
>> ---
>>  arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts |  9 +++
>>  arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  |  9 +++
>>  arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  |  9 +++
>>  arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi     | 91 +++++++++++++++++++++-
>>  4 files changed, 117 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
>> index a619f6496a4c..bab9e68947e4 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
>> @@ -49,6 +49,15 @@
>>  	model = "LS1012A Freedom Board";
>>  	compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
>>  
>> +	aliases {
>> +		crypto = &crypto;
>> +		rtic_a = &rtic_a;
>> +		rtic_b = &rtic_b;
>> +		rtic_c = &rtic_c;
>> +		rtic_d = &rtic_d;
>> +		sec_mon = &sec_mon;
>> +	};
>> +
>>  	sys_mclk: clock-mclk {
>>  		compatible = "fixed-clock";
>>  		#clock-cells = <0>;
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
>> index 14a67f1709e7..5c4e84c7f20d 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
>> @@ -49,6 +49,15 @@
>>  	model = "LS1012A QDS Board";
>>  	compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
>>  
>> +	aliases {
>> +		crypto = &crypto;
>> +		rtic_a = &rtic_a;
>> +		rtic_b = &rtic_b;
>> +		rtic_c = &rtic_c;
>> +		rtic_d = &rtic_d;
>> +		sec_mon = &sec_mon;
>> +	};
>> +
>>  	sys_mclk: clock-mclk {
>>  		compatible = "fixed-clock";
>>  		#clock-cells = <0>;
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
>> index 62c5c7123a15..ff9dd16aa65a 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
>> @@ -48,6 +48,15 @@
>>  / {
>>  	model = "LS1012A RDB Board";
>>  	compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
>> +
>> +	aliases {
>> +		crypto = &crypto;
>> +		rtic_a = &rtic_a;
>> +		rtic_b = &rtic_b;
>> +		rtic_c = &rtic_c;
>> +		rtic_d = &rtic_d;
>> +		sec_mon = &sec_mon;
>> +	};
> 
> What are these aliases used for?  Are they board specific?  If not, we
> should probably have them in fsl-ls1012a.dtsi, since you are adding
> them for all three fsl-ls1012a based boards.
> 
Indeed, these can be shared and thus should be moved to
fsl-ls1012a.dtsi. Will be fixed in v2.

crypto alias is used in u-boot to fixup the crypto node with a
"fsl,sec-era" property.

rtic and sec_mon aliases have been added to be in line with the PPC
device trees, I am not aware how they are used.

>>  };
>>  
>>  &duart0 {
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
>> index cffebb4b3df1..68f3012ae07e 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
>> @@ -42,7 +42,7 @@
>>   *     OTHER DEALINGS IN THE SOFTWARE.
>>   */
>>  
>> -#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>  
>>  / {
>>  	compatible = "fsl,ls1012a";
>> @@ -113,6 +113,95 @@
>>  			big-endian;
>>  		};
>>  
>> +		crypto: crypto@1700000 {
>> +			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
>> +				     "fsl,sec-v4.0";
>> +			fsl,sec-era = <8>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges = <0x0 0x00 0x1700000 0x100000>;
>> +			reg = <0x00 0x1700000 0x0 0x100000>;
>> +			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			sec_jr0: jr@10000 {
>> +				compatible = "fsl,sec-v5.4-job-ring",
>> +					     "fsl,sec-v5.0-job-ring",
>> +					     "fsl,sec-v4.0-job-ring";
>> +				reg	   = <0x10000 0x10000>;
>> +				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			sec_jr1: jr@20000 {
>> +				compatible = "fsl,sec-v5.4-job-ring",
>> +					     "fsl,sec-v5.0-job-ring",
>> +					     "fsl,sec-v4.0-job-ring";
>> +				reg	   = <0x20000 0x10000>;
>> +				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			sec_jr2: jr@30000 {
>> +				compatible = "fsl,sec-v5.4-job-ring",
>> +					     "fsl,sec-v5.0-job-ring",
>> +					     "fsl,sec-v4.0-job-ring";
>> +				reg	   = <0x30000 0x10000>;
>> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			sec_jr3: jr@40000 {
>> +				compatible = "fsl,sec-v5.4-job-ring",
>> +					     "fsl,sec-v5.0-job-ring",
>> +					     "fsl,sec-v4.0-job-ring";
>> +				reg	   = <0x40000 0x10000>;
>> +				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			rtic@60000 {
>> +				compatible = "fsl,sec-v5.4-rtic",
>> +					     "fsl,sec-v5.0-rtic",
>> +					     "fsl,sec-v4.0-rtic";
>> +				#address-cells = <1>;
>> +				#size-cells = <1>;
>> +				reg = <0x60000 0x100 0x60e00 0x18>;
>> +				ranges = <0x0 0x60100 0x500>;
>> +
>> +				rtic_a: rtic-a@0 {
>> +					compatible = "fsl,sec-v5.4-rtic-memory",
>> +						     "fsl,sec-v5.0-rtic-memory",
>> +						     "fsl,sec-v4.0-rtic-memory";
>> +					reg = <0x00 0x20 0x100 0x100>;
>> +				};
>> +
>> +				rtic_b: rtic-b@20 {
>> +					compatible = "fsl,sec-v5.4-rtic-memory",
>> +						     "fsl,sec-v5.0-rtic-memory",
>> +						     "fsl,sec-v4.0-rtic-memory";
>> +					reg = <0x20 0x20 0x200 0x100>;
>> +				};
>> +
>> +				rtic_c: rtic-c@40 {
>> +					compatible = "fsl,sec-v5.4-rtic-memory",
>> +						     "fsl,sec-v5.0-rtic-memory",
>> +						     "fsl,sec-v4.0-rtic-memory";
>> +					reg = <0x40 0x20 0x300 0x100>;
>> +				};
>> +
>> +				rtic_d: rtic-d@60 {
>> +					compatible = "fsl,sec-v5.4-rtic-memory",
>> +						     "fsl,sec-v5.0-rtic-memory",
>> +						     "fsl,sec-v4.0-rtic-memory";
>> +					reg = <0x60 0x20 0x400 0x100>;
>> +				};
>> +			};
>> +		};
>> +
>> +		sec_mon: sec_mon@1e90000 {
> 
> Hyphen is more preferred to be used in node name than underscore.
> 
This would imply changing the
Documentation/devicetree/bindings/crypto/fsl-sec4.txt binding and
dealing with all the consequences, which IIUC is probably not worth.

Thanks,
Horia
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Re: [PATCH] arm64: dts: ls1012a: add crypto node

[Shawn Guo]

On Fri, Mar 24, 2017 at 07:17:50AM +0000, Horia Geantă wrote:
> >> +		sec_mon: sec_mon@1e90000 {
> > 
> > Hyphen is more preferred to be used in node name than underscore.
> > 
> This would imply changing the
> Documentation/devicetree/bindings/crypto/fsl-sec4.txt binding and
> dealing with all the consequences, which IIUC is probably not worth.

I do not care the bindings doc that much, since I'm not the maintainer
of it.  What are the consequences specifically, if we use a better node
name in dts than bindings example?

Shawn

Re: [PATCH] arm64: dts: ls1012a: add crypto node

[Horia Geantă]

On 3/24/2017 9:35 AM, Shawn Guo wrote:
> On Fri, Mar 24, 2017 at 07:17:50AM +0000, Horia Geantă wrote:
>>>> +		sec_mon: sec_mon@1e90000 {
>>>
>>> Hyphen is more preferred to be used in node name than underscore.
>>>
>> This would imply changing the
>> Documentation/devicetree/bindings/crypto/fsl-sec4.txt binding and
>> dealing with all the consequences, which IIUC is probably not worth.
> 
> I do not care the bindings doc that much, since I'm not the maintainer
> of it.  What are the consequences specifically, if we use a better node
> name in dts than bindings example?
> 
Users relying on finding the sec_mon node will obviously stop working.
I don't see any in-kernel users, however there could be others I am not
aware of and DT bindings should provide for backwards compatibility.

I could deprecate "sec_mon" in the bindings and suggest "sec-mon"
instead, while leaving all existing dts files as-is.
The risk is breaking LS1012A users relying on "sec_mon".

I see that ePAPR:
-allows both for hyphen and underline in case of node names
-allows only for hyphen (i.e. forbids underline) in case of alias nodes

In the first case, I understand there's an (undocumented?) agreement to
prefer hyphen over underline.
For the 2nd one, does this mean I should change alias names?

Thanks,
Horia

Re: [PATCH] arm64: dts: ls1012a: add crypto node

[Shawn Guo]

On Fri, Mar 24, 2017 at 08:29:17AM +0000, Horia Geantă wrote:
> On 3/24/2017 9:35 AM, Shawn Guo wrote:
> > On Fri, Mar 24, 2017 at 07:17:50AM +0000, Horia Geantă wrote:
> >>>> +		sec_mon: sec_mon@1e90000 {
> >>>
> >>> Hyphen is more preferred to be used in node name than underscore.
> >>>
> >> This would imply changing the
> >> Documentation/devicetree/bindings/crypto/fsl-sec4.txt binding and
> >> dealing with all the consequences, which IIUC is probably not worth.
> > 
> > I do not care the bindings doc that much, since I'm not the maintainer
> > of it.  What are the consequences specifically, if we use a better node
> > name in dts than bindings example?
> > 
> Users relying on finding the sec_mon node will obviously stop working.
> I don't see any in-kernel users, however there could be others I am not
> aware of and DT bindings should provide for backwards compatibility.

Okay, point taken.  You can keep the node name as it is.

> I could deprecate "sec_mon" in the bindings and suggest "sec-mon"
> instead, while leaving all existing dts files as-is.
> The risk is breaking LS1012A users relying on "sec_mon".

For existing bindings, I do not care that much.  But for new ones, I do
hope that we recommend to use hyphen, as that's more idiomatic at least
for Linux kernel.

> I see that ePAPR:
> -allows both for hyphen and underline in case of node names
> -allows only for hyphen (i.e. forbids underline) in case of alias nodes
> 
> In the first case, I understand there's an (undocumented?) agreement to
> prefer hyphen over underline.

Both are valid, but hyphen is more idiomatic for Linux kernel.

> For the 2nd one, does this mean I should change alias names?

This is something I see difference between specification and DTC.

	aliases {
		alias-name = &label_name;
	};

	label_name: node-name {
		...
	};

The spec says that only hyphen is valid for alias name, but DTC works
happily with underscore too.  From my experience with DTC playing, both
hyphen and underscore are valid for alias and node name.  But for label
name, only underscore is valid.  Using hyphen in label name will cause
DTC to report syntax error.

Shawn
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Re: [PATCH] arm64: dts: ls1012a: add crypto node

[Horia Geantă]

On 3/24/2017 4:04 PM, Shawn Guo wrote:
> On Fri, Mar 24, 2017 at 08:29:17AM +0000, Horia Geantă wrote:
>> On 3/24/2017 9:35 AM, Shawn Guo wrote:
>>> On Fri, Mar 24, 2017 at 07:17:50AM +0000, Horia Geantă wrote:
>>>>>> +		sec_mon: sec_mon@1e90000 {
>>>>>
>>>>> Hyphen is more preferred to be used in node name than underscore.
>>>>>
>>>> This would imply changing the
>>>> Documentation/devicetree/bindings/crypto/fsl-sec4.txt binding and
>>>> dealing with all the consequences, which IIUC is probably not worth.
>>>
>>> I do not care the bindings doc that much, since I'm not the maintainer
>>> of it.  What are the consequences specifically, if we use a better node
>>> name in dts than bindings example?
>>>
>> Users relying on finding the sec_mon node will obviously stop working.
>> I don't see any in-kernel users, however there could be others I am not
>> aware of and DT bindings should provide for backwards compatibility.
> 
> Okay, point taken.  You can keep the node name as it is.
> 
>> I could deprecate "sec_mon" in the bindings and suggest "sec-mon"
>> instead, while leaving all existing dts files as-is.
>> The risk is breaking LS1012A users relying on "sec_mon".
> 
> For existing bindings, I do not care that much.  But for new ones, I do
> hope that we recommend to use hyphen, as that's more idiomatic at least
> for Linux kernel.
> 
>> I see that ePAPR:
>> -allows both for hyphen and underline in case of node names
>> -allows only for hyphen (i.e. forbids underline) in case of alias nodes
>>
>> In the first case, I understand there's an (undocumented?) agreement to
>> prefer hyphen over underline.
> 
> Both are valid, but hyphen is more idiomatic for Linux kernel.
> 
>> For the 2nd one, does this mean I should change alias names?
> 
> This is something I see difference between specification and DTC.
> 
> 	aliases {
> 		alias-name = &label_name;
> 	};
> 
> 	label_name: node-name {
> 		...
> 	};
> 
> The spec says that only hyphen is valid for alias name, but DTC works
> happily with underscore too.  From my experience with DTC playing, both
> hyphen and underscore are valid for alias and node name.  But for label
> name, only underscore is valid.  Using hyphen in label name will cause
> DTC to report syntax error.
> 
Yes indeed, thanks for pointing it out.

For the sake of current patch, please clarify whether a v2 is needed.
IIUC:
-sec_mon node name could stay the same (existing binding)
-label names are ok, since underline is the only option allowed by DTC
-alias names are out-of-spec but accepted by DTC; if changing underline
to hyphen is requested, I will push out v2

Thanks,
Horia

Re: [PATCH] arm64: dts: ls1012a: add crypto node

[Shawn Guo]

On Tue, Mar 28, 2017 at 07:19:43AM +0000, Horia Geantă wrote:
> For the sake of current patch, please clarify whether a v2 is needed.
> IIUC:
> -sec_mon node name could stay the same (existing binding)
> -label names are ok, since underline is the only option allowed by DTC
> -alias names are out-of-spec but accepted by DTC; if changing underline
> to hyphen is requested, I will push out v2

All these are fine.  But we agreed that the alias definitions can be
shared and should be moved to fsl-ls1012a.dtsi, right?

Shawn

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[PATCH v2] arm64: dts: ls1012a: add crypto node

[Horia Geantă]

LS1012A has a SEC v5.4 security engine.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
v2: move aliases from board specific files into the shared dtsi.

 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 100 ++++++++++++++++++++++++-
 1 file changed, 99 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index cffebb4b3df1..1c3493606cca 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -42,7 +42,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
 	compatible = "fsl,ls1012a";
@@ -50,6 +50,15 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		crypto = &crypto;
+		rtic_a = &rtic_a;
+		rtic_b = &rtic_b;
+		rtic_c = &rtic_c;
+		rtic_d = &rtic_d;
+		sec_mon = &sec_mon;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -113,6 +122,95 @@
 			big-endian;
 		};
 
+		crypto: crypto@1700000 {
+			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+				     "fsl,sec-v4.0";
+			fsl,sec-era = <8>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x1700000 0x100000>;
+			reg = <0x00 0x1700000 0x0 0x100000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			rtic@60000 {
+				compatible = "fsl,sec-v5.4-rtic",
+					     "fsl,sec-v5.0-rtic",
+					     "fsl,sec-v4.0-rtic";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x60000 0x100 0x60e00 0x18>;
+				ranges = <0x0 0x60100 0x500>;
+
+				rtic_a: rtic-a@0 {
+					compatible = "fsl,sec-v5.4-rtic-memory",
+						     "fsl,sec-v5.0-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x00 0x20 0x100 0x100>;
+				};
+
+				rtic_b: rtic-b@20 {
+					compatible = "fsl,sec-v5.4-rtic-memory",
+						     "fsl,sec-v5.0-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x20 0x20 0x200 0x100>;
+				};
+
+				rtic_c: rtic-c@40 {
+					compatible = "fsl,sec-v5.4-rtic-memory",
+						     "fsl,sec-v5.0-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x40 0x20 0x300 0x100>;
+				};
+
+				rtic_d: rtic-d@60 {
+					compatible = "fsl,sec-v5.4-rtic-memory",
+						     "fsl,sec-v5.0-rtic-memory",
+						     "fsl,sec-v4.0-rtic-memory";
+					reg = <0x60 0x20 0x400 0x100>;
+				};
+			};
+		};
+
+		sec_mon: sec_mon@1e90000 {
+			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
+				     "fsl,sec-v4.0-mon";
+			reg = <0x0 0x1e90000 0x0 0x10000>;
+			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1012a-dcfg",
 				     "syscon";
-- 
2.12.0.264.gd6db3f216544


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Re: [PATCH v2] arm64: dts: ls1012a: add crypto node

[Shawn Guo]

On Tue, Mar 28, 2017 at 02:46:19PM +0300, Horia Geantă wrote:
> LS1012A has a SEC v5.4 security engine.
> 
> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>

Applied, thanks.