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From: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
To: Michael Turquette
	<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
	Maxime Ripard
	<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
	Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
Subject: [PATCH v3 3/5] arm64: allwinner: a64: add r_ccu node
Date: Wed, 29 Mar 2017 18:42:44 +0800	[thread overview]
Message-ID: <20170329104246.34204-4-icenowy@aosc.io> (raw)
In-Reply-To: <20170329104246.34204-1-icenowy-h8G6r0blFSE@public.gmane.org>

From: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>

A64 SoC have a CCU (r_ccu) in PRCM block.

Add the device node for it.

The mux 3 of R_CCU is an internal oscillator, which is 16MHz according
to the user manual, and has only 30% accuracy based on our experience
on older SoCs. The real mesaured value of it on two Pine64 boards is
around 11MHz, which is around 70% of 16MHz.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
Changes in v3:
- Change osc32000 to iosc, which is 16MHz plus minus 30%, according to the
  RTC chapter of the user manual and our experiences on A33.
Changes in v2:
- Add osc32000.

 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..0fe9865d4bd6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -43,8 +43,10 @@
  */
 
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -98,6 +100,14 @@
 		clock-output-names = "osc32k";
 	};
 
+	iosc: internal-osc-clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <16000000>;
+		clock-accuracy = <300000000>;
+		clock-output-names = "iosc";
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
@@ -392,5 +402,14 @@
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		r_ccu: clock@1f01400 {
+			compatible = "allwinner,sun50i-a64-r-ccu";
+			reg = <0x01f01400 0x100>;
+			clocks = <&osc24M>, <&osc32k>, <&iosc>;
+			clock-names = "hosc", "losc", "iosc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
 	};
 };
-- 
2.12.0

  parent reply	other threads:[~2017-03-29 10:42 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-29 10:42 [PATCH v3 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs Icenowy Zheng
     [not found] ` <20170329104246.34204-1-icenowy-h8G6r0blFSE@public.gmane.org>
2017-03-29 10:42   ` [PATCH v3 1/5] dt-bindings: update device tree binding for Allwinner PRCM CCUs Icenowy Zheng
     [not found]     ` <20170329104246.34204-2-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-03 14:49       ` Rob Herring
2017-03-29 10:42   ` [PATCH v3 2/5] clk: sunxi-ng: add support for " Icenowy Zheng
     [not found]     ` <20170329104246.34204-3-icenowy-h8G6r0blFSE@public.gmane.org>
2017-03-29 15:27       ` Icenowy Zheng
2017-03-29 10:42   ` Icenowy Zheng [this message]
2017-03-29 10:42   ` [PATCH v3 4/5] ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu Icenowy Zheng
2017-03-29 10:42   ` [PATCH v3 5/5] arm64: allwinner: a64: add R_PIO pinctrl node Icenowy Zheng
2017-04-02 16:02   ` [PATCH v3 0/5] Add support for the R_CCU on Allwinner H3/A64 SoCs Maxime Ripard
2017-04-02 16:32     ` Icenowy Zheng
2017-04-03  7:36       ` Maxime Ripard

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