From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
To: xuwei5@hisilicon.com, robh+dt@kernel.org, mark.rutland@arm.com,
catalin.marinas@arm.com, will.deacon@arm.com,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: hw.wangxiaoyin@hisilicon.com, chenya99@hisilicon.com
Subject: [PATCH 1/2] arm64: dts: add drive-strength levels of pin for Hi3660 SoC
Date: Thu, 30 Mar 2017 14:48:02 +0800 [thread overview]
Message-ID: <20170330064803.18648-1-hw.wangxiaoyin@hisilicon.com> (raw)
Add drive-strength levels of pin for Hi3660 Soc.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
---
include/dt-bindings/pinctrl/hisi.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
index 38f1ea879ea1..0359bfdc9119 100644
--- a/include/dt-bindings/pinctrl/hisi.h
+++ b/include/dt-bindings/pinctrl/hisi.h
@@ -56,4 +56,19 @@
#define DRIVE4_08MA (4 << 4)
#define DRIVE4_10MA (6 << 4)
+/* drive strength definition for hi3660 */
+#define DRIVE6_MASK (15 << 4)
+#define DRIVE6_04MA (0 << 4)
+#define DRIVE6_12MA (4 << 4)
+#define DRIVE6_19MA (8 << 4)
+#define DRIVE6_27MA (10 << 4)
+#define DRIVE6_32MA (15 << 4)
+#define DRIVE7_02MA (0 << 4)
+#define DRIVE7_04MA (1 << 4)
+#define DRIVE7_06MA (2 << 4)
+#define DRIVE7_08MA (3 << 4)
+#define DRIVE7_10MA (4 << 4)
+#define DRIVE7_12MA (5 << 4)
+#define DRIVE7_14MA (6 << 4)
+#define DRIVE7_16MA (7 << 4)
#endif
--
2.11.0-rc2
next reply other threads:[~2017-03-30 6:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-30 6:48 Wang Xiaoyin [this message]
2017-03-30 6:48 ` [PATCH 2/2] arm64: dts: add pinctrl dtsi file for HiKey960 development board Wang Xiaoyin
[not found] ` <20170330064803.18648-1-hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
2017-04-08 6:42 ` [PATCH 1/2] arm64: dts: add drive-strength levels of pin for Hi3660 SoC Wei Xu
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