[PATCH v1 2/3] ARM: dts: imx6qdl.dtsi: add "fsl,imx6q-snvs-lpgpr" node

[PATCH v1 2/3] ARM: dts: imx6qdl.dtsi: add "fsl,imx6q-snvs-lpgpr" node

[Oleksij Rempel]

This node is for Low Power General Purpose Registe wich can
be used as Non-Volatile Storage.

Signed-off-by: Oleksij Rempel <o.rempel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 6d7bf6496117..8e90014705c3 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -768,6 +768,12 @@
 					mask = <0x60>;
 					status = "disabled";
 				};
+
+				snvs_lpgpr: snvs-lpgpr {
+					compatible = "fsl,imx6q-snvs-lpgpr";
+					regmap = <&snvs>;
+					offset = <0x68>;
+				};
 			};
 
 			epit1: epit@020d0000 { /* EPIT1 */
-- 
2.11.0

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[PATCH v1 3/3] nvmem: dt: document SNVS LPGPR binding

[Oleksij Rempel]

Documenation bindings for the Low Power General Purpose Registe
available on i.MX6 SoCs in the Secure Non-Volatile Storage.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt

diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
new file mode 100644
index 000000000000..9a8be1a2d12e
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
@@ -0,0 +1,15 @@
+Device tree bindings for Low Power General Purpose Registe found in i.MX6Q/D
+Secure Non-Volatile Storage.
+
+Required properties:
+- compatible: should be one of
+	"fsl,imx6q-snvs-lpgpr" (i.MX6Q/D/DL/S).
+- offset: Should contain the offset relative to syscon parrent node.
+- regmap: Should contain a phandle pointing to syscon.
+
+Example:
+	snvs_lpgpr: snvs-lpgpr {
+		compatible = "fsl,imx6q-snvs-lpgpr";
+		regmap = <&snvs>;
+		offset = <0x68>;
+	};
-- 
2.11.0

Re: [PATCH v1 3/3] nvmem: dt: document SNVS LPGPR binding

[Rob Herring]

On Thu, Apr 06, 2017 at 09:31:07AM +0200, Oleksij Rempel wrote:
> Documenation bindings for the Low Power General Purpose Registe

s/Registe/Register/

> available on i.MX6 SoCs in the Secure Non-Volatile Storage.
> 
> Signed-off-by: Oleksij Rempel <o.rempel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Cc: Srinivas Kandagatla <srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> 
> diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> new file mode 100644
> index 000000000000..9a8be1a2d12e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> @@ -0,0 +1,15 @@
> +Device tree bindings for Low Power General Purpose Registe found in i.MX6Q/D
> +Secure Non-Volatile Storage.
> +
> +Required properties:
> +- compatible: should be one of
> +	"fsl,imx6q-snvs-lpgpr" (i.MX6Q/D/DL/S).
> +- offset: Should contain the offset relative to syscon parrent node.

typo

 +- regmap: Should contain a phandle pointing to syscon.
> +
> +Example:
> +	snvs_lpgpr: snvs-lpgpr {
> +		compatible = "fsl,imx6q-snvs-lpgpr";
> +		regmap = <&snvs>;
> +		offset = <0x68>;

Why does this need to be in DT? Is something going to refer to this 
node? If not, the &snvs node should be enough information for the OS.

Rob
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Re: [PATCH v1 3/3] nvmem: dt: document SNVS LPGPR binding

[Oleksij Rempel]

Hi,

On 04/10/2017 08:22 PM, Rob Herring wrote:
> On Thu, Apr 06, 2017 at 09:31:07AM +0200, Oleksij Rempel wrote:
>> Documenation bindings for the Low Power General Purpose Registe
>
> s/Registe/Register/
>
>> available on i.MX6 SoCs in the Secure Non-Volatile Storage.
>>
>> Signed-off-by: Oleksij Rempel <o.rempel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>> Cc: Srinivas Kandagatla <srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> Cc: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> ---
>>  Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 15 +++++++++++++++
>>  1 file changed, 15 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>
>> diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>> new file mode 100644
>> index 000000000000..9a8be1a2d12e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>> @@ -0,0 +1,15 @@
>> +Device tree bindings for Low Power General Purpose Registe found in i.MX6Q/D
>> +Secure Non-Volatile Storage.
>> +
>> +Required properties:
>> +- compatible: should be one of
>> +	"fsl,imx6q-snvs-lpgpr" (i.MX6Q/D/DL/S).
>> +- offset: Should contain the offset relative to syscon parrent node.
>
> typo

ok.

>  +- regmap: Should contain a phandle pointing to syscon.
>> +
>> +Example:
>> +	snvs_lpgpr: snvs-lpgpr {
>> +		compatible = "fsl,imx6q-snvs-lpgpr";
>> +		regmap = <&snvs>;
>> +		offset = <0x68>;
>
> Why does this need to be in DT? Is something going to refer to this
> node? If not, the &snvs node should be enough information for the OS.

Jes, it is refereed by other driver.

Thank you.
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[PATCH v2 2/3] ARM: dts: imx6qdl.dtsi: add "fsl, imx6q-snvs-lpgpr" node

[Oleksij Rempel]

This node is for Low Power General Purpose Register which can
be used as Non-Volatile Storage.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
---
 arch/arm/boot/dts/imx6qdl.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 6d7bf6496117..8e90014705c3 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -768,6 +768,12 @@
 					mask = <0x60>;
 					status = "disabled";
 				};
+
+				snvs_lpgpr: snvs-lpgpr {
+					compatible = "fsl,imx6q-snvs-lpgpr";
+					regmap = <&snvs>;
+					offset = <0x68>;
+				};
 			};
 
 			epit1: epit@020d0000 { /* EPIT1 */
-- 
2.11.0

[PATCH v2 3/3] nvmem: dt: document SNVS LPGPR binding

[Oleksij Rempel]

Documentation bindings for the Low Power General Purpose Register
available on i.MX6 SoCs in the Secure Non-Volatile Storage.

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt

diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
new file mode 100644
index 000000000000..5399087a76d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
@@ -0,0 +1,15 @@
+Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
+Secure Non-Volatile Storage.
+
+Required properties:
+- compatible: should be one of
+	"fsl,imx6q-snvs-lpgpr" (i.MX6Q/D/DL/S).
+- offset: Should contain the offset relative to syscon parent node.
+- regmap: Should contain a phandle pointing to syscon.
+
+Example:
+	snvs_lpgpr: snvs-lpgpr {
+		compatible = "fsl,imx6q-snvs-lpgpr";
+		regmap = <&snvs>;
+		offset = <0x68>;
+	};
-- 
2.11.0

Re: [PATCH v1 3/3] nvmem: dt: document SNVS LPGPR binding

[Rob Herring]

On Mon, Apr 10, 2017 at 11:36 PM, Oleksij Rempel <ore-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> Hi,
>
>
> On 04/10/2017 08:22 PM, Rob Herring wrote:
>>
>> On Thu, Apr 06, 2017 at 09:31:07AM +0200, Oleksij Rempel wrote:
>>>
>>> Documenation bindings for the Low Power General Purpose Registe
>>
>>
>> s/Registe/Register/
>>
>>> available on i.MX6 SoCs in the Secure Non-Volatile Storage.
>>>
>>> Signed-off-by: Oleksij Rempel <o.rempel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
>>> Cc: Srinivas Kandagatla <srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>> Cc: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
>>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>> ---
>>>  Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 15
>>> +++++++++++++++
>>>  1 file changed, 15 insertions(+)
>>>  create mode 100644
>>> Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>> b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>> new file mode 100644
>>> index 000000000000..9a8be1a2d12e
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>> @@ -0,0 +1,15 @@
>>> +Device tree bindings for Low Power General Purpose Registe found in
>>> i.MX6Q/D
>>> +Secure Non-Volatile Storage.
>>> +
>>> +Required properties:
>>> +- compatible: should be one of
>>> +       "fsl,imx6q-snvs-lpgpr" (i.MX6Q/D/DL/S).
>>> +- offset: Should contain the offset relative to syscon parrent node.
>>
>>
>> typo
>
>
> ok.
>
>>  +- regmap: Should contain a phandle pointing to syscon.
>>>
>>> +
>>> +Example:
>>> +       snvs_lpgpr: snvs-lpgpr {
>>> +               compatible = "fsl,imx6q-snvs-lpgpr";
>>> +               regmap = <&snvs>;
>>> +               offset = <0x68>;
>>
>>
>> Why does this need to be in DT? Is something going to refer to this
>> node? If not, the &snvs node should be enough information for the OS.
>
>
> Jes, it is refereed by other driver.

What I mean is snvs-lpgpr referenced elsewhere in DT, not by some
driver? You are not using the nvmem binding here so it doesn't seem
like it is. If that's the case, then you don't need this node. The
only information here is the offset which can be part of a driver for
the parent node. To put it another way, we don't want to fill DT with
a node per register.

Rob
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Re: [PATCH v1 3/3] nvmem: dt: document SNVS LPGPR binding

[Oleksij Rempel]

On Tue, Apr 11, 2017 at 08:35:00AM -0500, Rob Herring wrote:
> On Mon, Apr 10, 2017 at 11:36 PM, Oleksij Rempel <ore-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> > Hi,
> > On 04/10/2017 08:22 PM, Rob Herring wrote:
> >>
> >> On Thu, Apr 06, 2017 at 09:31:07AM +0200, Oleksij Rempel wrote:
> >>>
> >>> Documenation bindings for the Low Power General Purpose Registe
> >>
> > Jes, it is refereed by other driver.
> 
> What I mean is snvs-lpgpr referenced elsewhere in DT, not by some
> driver? You are not using the nvmem binding here so it doesn't seem
> like it is. If that's the case, then you don't need this node. The
> only information here is the offset which can be part of a driver for
> the parent node. To put it another way, we don't want to fill DT with
> a node per register.

This node is referenced insight of product DT. Since the system has
or may have more then one nvmem node we need to assigne aliase to it.

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH v1 3/3] nvmem: dt: document SNVS LPGPR binding

[Oleksij Rempel]

On Wed, Apr 12, 2017 at 08:23:53AM +0200, Oleksij Rempel wrote:
> On Tue, Apr 11, 2017 at 08:35:00AM -0500, Rob Herring wrote:
> > On Mon, Apr 10, 2017 at 11:36 PM, Oleksij Rempel <ore-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote:
> > > Hi,
> > > On 04/10/2017 08:22 PM, Rob Herring wrote:
> > >>
> > >> On Thu, Apr 06, 2017 at 09:31:07AM +0200, Oleksij Rempel wrote:
> > >>>
> > >>> Documenation bindings for the Low Power General Purpose Registe
> > >>
> > > Jes, it is refereed by other driver.
> > 
> > What I mean is snvs-lpgpr referenced elsewhere in DT, not by some
> > driver? You are not using the nvmem binding here so it doesn't seem
> > like it is. If that's the case, then you don't need this node. The
> > only information here is the offset which can be part of a driver for
> > the parent node. To put it another way, we don't want to fill DT with
> > a node per register.
> 
> This node is referenced insight of product DT. Since the system has
> or may have more then one nvmem node we need to assigne aliase to it.

Hi, are there still some doubts about this patch set?

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
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