From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Simon Horman <horms@verge.net.au>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org
Cc: Magnus Damm <magnus.damm@gmail.com>,
Russell King <linux@armlinux.org.uk>,
linux-arm-kernel@lists.infradead.org,
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: [PATCH 2/3] ARM: dts: sk-rzg1m: add SCIF0 pins
Date: Sat, 15 Apr 2017 00:09:43 +0300 [thread overview]
Message-ID: <20170414211509.818645915@cogentembedded.com> (raw)
[-- Attachment #1: ARM-dts-sk-rzg1m-add-SCIF0-pins.patch --]
[-- Type: text/plain, Size: 1057 bytes --]
Add the (previously omitted) SCIF0 pin data to the SK-RZG1M board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm/boot/dts/r8a7743-sk-rzg1m.dts | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
Index: renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
+++ renesas/arch/arm/boot/dts/r8a7743-sk-rzg1m.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the SK-RZG1M board
*
- * Copyright (C) 2016 Cogent Embedded, Inc.
+ * Copyright (C) 2016-2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -39,7 +39,17 @@
clock-frequency = <20000000>;
};
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+};
+
&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
next reply other threads:[~2017-04-14 21:09 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-14 21:09 Sergei Shtylyov [this message]
2017-04-20 14:19 ` [PATCH 2/3] ARM: dts: sk-rzg1m: add SCIF0 pins Geert Uytterhoeven
2017-04-20 15:45 ` Sergei Shtylyov
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