* [PATCH 3/3] ARM: dts: sk-rzg1e: add Ether pins
@ 2017-04-15 20:18 Sergei Shtylyov
0 siblings, 0 replies; only message in thread
From: Sergei Shtylyov @ 2017-04-15 20:18 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Mark Rutland,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Magnus Damm, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sergei Shtylyov
[-- Attachment #1: ARM-dts-sk-rzg1e-add-Ether-pins.patch --]
[-- Type: text/plain, Size: 1176 bytes --]
Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
---
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
+++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -39,6 +39,16 @@
groups = "scif2_data";
function = "scif2";
};
+
+ ether_pins: ether {
+ groups = "eth_link", "eth_mdio", "eth_rmii";
+ function = "eth";
+ };
+
+ phy1_pins: phy1 {
+ groups = "intc_irq8";
+ function = "intc";
+ };
};
&scif2 {
@@ -49,6 +59,9 @@
};
ðer {
+ pinctrl-0 = <ðer_pins &phy1_pins>;
+ pinctrl-names = "default";
+
phy-handle = <&phy1>;
renesas,ether-link-active-low;
status = "okay";
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