* [PATCH] ARM: sun8i: v3s: enable SPI
@ 2017-05-17 13:52 Icenowy Zheng
[not found] ` <20170517135257.1674-1-icenowy-h8G6r0blFSE@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Icenowy Zheng @ 2017-05-17 13:52 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Icenowy Zheng
Allwinner V3s SoC has a SPI controller, muxed with the MMC2 controller
at PC bank. The controller itself is identical to the one in H3 SoC.
Add device tree node and the only pinmux node for it.
Tested with a Winbond W25Q128FV SPI NOR soldered on the Lichee Pi
early sample.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 6ff50665e5e6..a49ebef53c91 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -234,6 +234,11 @@
drive-strength = <30>;
bias-pull-up;
};
+
+ spi0_pins: spi0 {
+ pins = "PC0", "PC1", "PC2", "PC3";
+ function = "spi0";
+ };
};
timer@01c20c00 {
@@ -314,6 +319,20 @@
#size-cells = <0>;
};
+ spi0: spi@1c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
--
2.12.2
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] ARM: sun8i: v3s: enable SPI
[not found] ` <20170517135257.1674-1-icenowy-h8G6r0blFSE@public.gmane.org>
@ 2017-05-17 17:33 ` Maxime Ripard
0 siblings, 0 replies; 2+ messages in thread
From: Maxime Ripard @ 2017-05-17 17:33 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 568 bytes --]
On Wed, May 17, 2017 at 09:52:57PM +0800, Icenowy Zheng wrote:
> Allwinner V3s SoC has a SPI controller, muxed with the MMC2 controller
> at PC bank. The controller itself is identical to the one in H3 SoC.
>
> Add device tree node and the only pinmux node for it.
>
> Tested with a Winbond W25Q128FV SPI NOR soldered on the Lichee Pi
> early sample.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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2017-05-17 13:52 [PATCH] ARM: sun8i: v3s: enable SPI Icenowy Zheng
[not found] ` <20170517135257.1674-1-icenowy-h8G6r0blFSE@public.gmane.org>
2017-05-17 17:33 ` Maxime Ripard
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