[PATCH 0/4] net-next: stmmac: dwmac-sun8i: add support for V3s

[PATCH 0/4] net-next: stmmac: dwmac-sun8i: add support for V3s

[Icenowy Zheng]

Allwinner V3s features an EMAC like the on in H3, but without external MII
interfaces, so being not able really to use RMII/RGMII.

And it has a different default value of syscon (0x38000 instead of 0x58000
on H3), which shows a problem that the EMAC clock freq should be 24MHz.
(Both H3 and V3s SoCs doesn't have extra xtal input for EPHY, and the
main xtal is 24MHz. The default value of H3 is set to 24MHz, but the V3s
default value is set to 25MHz).

First two patches are device tree binding patches, the third forces
the frequency to 24MHz and the fourth really add the V3s support.

Icenowy Zheng (4):
  dt-bindings: net-next: Add DT bindings documentation for Allwinner V3s
    EMAC
  dt-bindings: syscon: Add DT bindings documentation for Allwinner V3s
    syscon
  net-next: stmmac: dwmac-sun8i: force EPHY clock freq to 24MHz
  net-next: stmmac: dwmac-sun8i: add support for V3s EMAC

 Documentation/devicetree/bindings/misc/allwinner,syscon.txt |  1 +
 Documentation/devicetree/bindings/net/dwmac-sun8i.txt       | 10 ++++++++--
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c           | 12 ++++++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c       |  1 +
 4 files changed, 22 insertions(+), 2 deletions(-)

-- 
2.13.0

[PATCH 1/4] dt-bindings: net-next: Add DT bindings documentation for Allwinner V3s EMAC

[Icenowy Zheng]

Allwinner V3s SoC has a Ethernet MAC like the one in Allwinner H3, but
have no external MII capability. That means that it can only use the
EPHY and cannot do Gbps transmission.

Add binding for it.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
 Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 08e708c73193..725f3b187886 100644
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -7,6 +7,7 @@ Required properties:
 - compatible: should be one of the following string:
 		"allwinner,sun8i-a83t-emac"
 		"allwinner,sun8i-h3-emac"
+		"allwinner,sun8i-v3s-emac"
 		"allwinner,sun50i-a64-emac"
 - reg: address and length of the register for the device.
 - interrupts: interrupt for the device
@@ -22,6 +23,7 @@ Required properties:
 - syscon: A phandle to the syscon of the SoC with one of the following
  compatible string:
   - allwinner,sun8i-h3-system-controller
+  - allwinner,sun8i-v3s-system-controller
   - allwinner,sun50i-a64-system-controller
   - allwinner,sun8i-a83t-system-controller
 
@@ -31,7 +33,9 @@ Optional properties:
 Both delay properties need to be a multiple of 100. They control the delay for
 external PHY.
 
-Optional properties for "allwinner,sun8i-h3-emac":
+Optional properties for the following compatibles:
+  - "allwinner,sun8i-h3-emac",
+  - "allwinner,sun8i-v3s-emac":
 - allwinner,leds-active-low: EPHY LEDs are active low
 
 Required child node of emac:
@@ -44,7 +48,9 @@ Required properties of the mdio node:
 The device node referenced by "phy" or "phy-handle" should be a child node
 of the mdio node. See phy.txt for the generic PHY bindings.
 
-Required properties of the phy node with "allwinner,sun8i-h3-emac":
+Required properties of the phy node with the following compatibles:
+  - "allwinner,sun8i-h3-emac",
+  - "allwinner,sun8i-v3s-emac":
 - clocks: a phandle to the reference clock for the EPHY
 - resets: a phandle to the reset control for the EPHY
 
-- 
2.13.0

[PATCH 2/4] dt-bindings: syscon: Add DT bindings documentation for Allwinner V3s syscon

[Icenowy Zheng]

Allwinner V3s SoC has a syscon like the one in H3.

Add its compatible string.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
 Documentation/devicetree/bindings/misc/allwinner,syscon.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/misc/allwinner,syscon.txt b/Documentation/devicetree/bindings/misc/allwinner,syscon.txt
index cb5769137c6c..31494a24fe69 100644
--- a/Documentation/devicetree/bindings/misc/allwinner,syscon.txt
+++ b/Documentation/devicetree/bindings/misc/allwinner,syscon.txt
@@ -9,6 +9,7 @@ Required properties for the system controller:
 - reg: address and length of the register for the device.
 - compatible: should be "syscon" and one of the following string:
 		"allwinner,sun8i-h3-system-controller"
+		"allwinner,sun8i-v3s-system-controller"
 		"allwinner,sun50i-a64-system-controller"
 		"allwinner,sun8i-a83t-system-controller"
 
-- 
2.13.0

[PATCH 3/4] net-next: stmmac: dwmac-sun8i: force EPHY clock freq to 24MHz

[Icenowy Zheng]

The EPHY control part of the EMAC syscon register has a bit called
CLK_SEL. On the datasheet it says that if it's 0 the EPHY clock is 25MHz
and if it's 1 the clock is 24MHz.

However, according to the datasheets, no Allwinner SoC with EPHY has any
extra xtal input pins for the EPHY, and the system xtal is 24MHz.

That means the EPHY is not possible to get a 25MHz xtal input, and thus
the frequency can only be 24MHz.

It doesn't matter on H3 as the default value of H3 is 24MHz, however on
V3s the default value is wrongly set to 25MHz, which prevented the EPHY
from working properly.

Force the EPHY clock frequency to 24MHz.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 54f93ee53ef7..61ce3b54f0c6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -185,6 +185,7 @@ static const struct emac_variant emac_variant_a64 = {
 
 /* H3 specific bits for EPHY */
 #define H3_EPHY_ADDR_SHIFT	20
+#define H3_EPHY_CLK_SEL		BIT(18) /* 1: 24MHz, 0: 25MHz */
 #define H3_EPHY_LED_POL		BIT(17) /* 1: active low, 0: active high */
 #define H3_EPHY_SHUTDOWN	BIT(16) /* 1: shutdown, 0: power up */
 #define H3_EPHY_SELECT		BIT(15) /* 1: internal PHY, 0: external PHY */
@@ -656,6 +657,9 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
 			else
 				reg &= ~H3_EPHY_LED_POL;
 
+			/* Force EPHY xtal frequency to 24MHz. */
+			reg |= H3_EPHY_CLK_SEL;
+
 			ret = of_mdio_parse_addr(priv->device,
 						 priv->plat->phy_node);
 			if (ret < 0) {
-- 
2.13.0

[PATCH 4/4] net-next: stmmac: dwmac-sun8i: add support for V3s EMAC

[Icenowy Zheng]

Allwinner V3s SoC has an Ethernet MAC and an internal PHY like the ones
in H3 SoC, however the MAC has no external *MII interfaces available at
GPIOs, thus only MII connection to internal PHY is supported.

Add this variant of EMAC to dwmac-sun8i driver.

The default value of the syscon EMAC-related register seems to have
changed from H3, but it seems to be a harmless change.

Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c     | 8 ++++++++
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 61ce3b54f0c6..fffd6d5fc907 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -81,6 +81,12 @@ static const struct emac_variant emac_variant_h3 = {
 	.support_rgmii = true
 };
 
+static const struct emac_variant emac_variant_v3s = {
+	.default_syscon_value = 0x38000,
+	.internal_phy = PHY_INTERFACE_MODE_MII,
+	.support_mii = true
+};
+
 static const struct emac_variant emac_variant_a83t = {
 	.default_syscon_value = 0,
 	.internal_phy = 0,
@@ -975,6 +981,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
 static const struct of_device_id sun8i_dwmac_match[] = {
 	{ .compatible = "allwinner,sun8i-h3-emac",
 		.data = &emac_variant_h3 },
+	{ .compatible = "allwinner,sun8i-v3s-emac",
+		.data = &emac_variant_v3s },
 	{ .compatible = "allwinner,sun8i-a83t-emac",
 		.data = &emac_variant_a83t },
 	{ .compatible = "allwinner,sun50i-a64-emac",
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 3840529344ed..a366b3747eeb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -313,6 +313,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
 		{ .compatible = "snps,dwc-qos-ethernet-4.10" },
 		{ .compatible = "allwinner,sun8i-a83t-emac" },
 		{ .compatible = "allwinner,sun8i-h3-emac" },
+		{ .compatible = "allwinner,sun8i-v3s-emac" },
 		{ .compatible = "allwinner,sun50i-a64-emac" },
 	};
 
-- 
2.13.0

Re: [PATCH 0/4] net-next: stmmac: dwmac-sun8i: add support for V3s

[David Miller]

From: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Date: Sat, 17 Jun 2017 22:07:33 +0800

> Allwinner V3s features an EMAC like the on in H3, but without external MII
> interfaces, so being not able really to use RMII/RGMII.
> 
> And it has a different default value of syscon (0x38000 instead of 0x58000
> on H3), which shows a problem that the EMAC clock freq should be 24MHz.
> (Both H3 and V3s SoCs doesn't have extra xtal input for EPHY, and the
> main xtal is 24MHz. The default value of H3 is set to 24MHz, but the V3s
> default value is set to 25MHz).
> 
> First two patches are device tree binding patches, the third forces
> the frequency to 24MHz and the fourth really add the V3s support.

Series applied to net-next, thanks!