From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v4 1/6] clk: sunxi-ng: div: Add support for fixed post-divider Date: Tue, 27 Jun 2017 11:46:07 +0200 Message-ID: <20170627094607.2hkgzkycclboemvu@flea.lan> References: Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="5tptchyg3tgiuxg4" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Priit Laes Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Chen-Yu Tsai , Russell King , Philipp Zabel , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Jonathan Liu List-Id: devicetree@vger.kernel.org --5tptchyg3tgiuxg4 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Hi! On Sun, Jun 25, 2017 at 11:45:42PM +0300, Priit Laes wrote: > SATA clock on sun4i/sun7i is of type (parent) / M / 6 where > 6 is fixed post-divider. > > Signed-off-by: Priit Laes > --- > drivers/clk/sunxi-ng/ccu_div.c | 12 ++++++++++-- > drivers/clk/sunxi-ng/ccu_div.h | 3 ++- > 2 files changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c > index c0e5c10..de30e15 100644 > --- a/drivers/clk/sunxi-ng/ccu_div.c > +++ b/drivers/clk/sunxi-ng/ccu_div.c > @@ -62,8 +62,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, > parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, > parent_rate); > > - return divider_recalc_rate(hw, parent_rate, val, cd->div.table, > - cd->div.flags); > + val = divider_recalc_rate(hw, parent_rate, val, cd->div.table, > + cd->div.flags); > + > + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) > + val /= cd->fixed_post_div; > + > + return val; > } > > static int ccu_div_determine_rate(struct clk_hw *hw, > @@ -89,6 +94,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate, > val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, > cd->div.flags); > > + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV) > + val *= cd->fixed_post_div; > + > spin_lock_irqsave(cd->common.lock, flags); > > reg = readl(cd->common.base + cd->common.reg); You also need to adjust the round rate call back to take into account the post divider before calling divider_round_rate_parent, and after since that function can modify the parent_rate. > diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h > index 08d0744..f3a5028 100644 > --- a/drivers/clk/sunxi-ng/ccu_div.h > +++ b/drivers/clk/sunxi-ng/ccu_div.h > @@ -86,9 +86,10 @@ struct ccu_div_internal { > struct ccu_div { > u32 enable; > > - struct ccu_div_internal div; > + struct ccu_div_internal div; Spurious change? Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --5tptchyg3tgiuxg4--