From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v2 05/10] mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode Date: Fri, 21 Jul 2017 09:21:16 +0200 Message-ID: <20170721072116.bub4fxqq2zg6kj3t@flea> References: <20170720034452.15920-1-wens@csie.org> <20170720034452.15920-6-wens@csie.org> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="l5oxp2yqvksnbrtt" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20170720034452.15920-6-wens-jdAy2FN1RRM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Chen-Yu Tsai Cc: Ulf Hansson , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org --l5oxp2yqvksnbrtt Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Thu, Jul 20, 2017 at 11:44:47AM +0800, Chen-Yu Tsai wrote: > The MMC controller can support DDR52 transfers under the new timing > mode. According to the BSP kernel, the module clock has to be double > the card clock, regardless of the bus width. The default timings in > the hardware can be used. > > This also reworks the code setting the internal divider, getting rid > of a extra conditional. > > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --l5oxp2yqvksnbrtt--