From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Boyd <sboyd@codeaurora.org>
Subject: Re: [PATCH V2 02/10] dt-bindings: Add Spreadtrum clock binding
 documentation
Date: Fri, 21 Jul 2017 15:57:29 -0700
Message-ID: <20170721225729.GB2146@codeaurora.org>
References: <20170711105627.20526-1-chunyan.zhang@spreadtrum.com>
 <20170711105627.20526-3-chunyan.zhang@spreadtrum.com>
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To: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Cc: Michael Turquette <mturquette@baylibre.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Arnd Bergmann <arnd@arndb.de>, Mark Brown <broonie@kernel.org>, Xiaolong Zhang <xiaolong.zhang@spreadtrum.com>, Ben Li <ben.li@spreadtrum.com>, Orson Zhai <orson.zhai@spreadtrum.com>, Chunyan Zhang <zhang.lyra@gmail.com>
List-Id: devicetree@vger.kernel.org

On 07/11, Chunyan Zhang wrote:
> Introduce a new binding with its documentation for Spreadtrum clock
> sub-framework.
> 
> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
> ---
>  Documentation/devicetree/bindings/clock/sprd.txt | 36 ++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt
> new file mode 100644
> index 0000000..c6f3abf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/sprd.txt
> @@ -0,0 +1,36 @@
> +Spreadtrum Clock Binding
> +------------------------
> +
> +Required properties:
> +- compatible: must contain the following compatible:
> +	- "sprd,sc9860-clk" (only support SC9860 for the time being)
> +
> +- reg:	Must contain the registers base address and length.
> +	Clocks on most of Spreadtrum's SoCs were designed to locate in a few
> +	different address areas, so there would be more than one items under
> +	this property.
> +
> +- #clock-cells: must be 1
> +
> +Example:
> +
> +clk: clk {

clock-controller for the node name?

> +	compatible = "sprd,sc9860-clk";
> +	#clock-cells = <1>;
> +	reg = <0 0x20000000 0 0x400>,
> +	      <0 0x20210000 0 0x3000>,
> +	      <0 0x402b0000 0 0x4000>,
> +	      <0 0x402d0000 0 0x400>,
> +	      <0 0x402e0000 0 0x4000>,
> +	      <0 0x40400000 0 0x400>,
> +	      <0 0x40880000 0 0x400>,
> +	      <0 0x415e0000 0 0x400>,
> +	      <0 0x60200000 0 0x400>,
> +	      <0 0x61000000 0 0x400>,
> +	      <0 0x61100000 0 0x3000>,
> +	      <0 0x62000000 0 0x4000>,
> +	      <0 0x62100000 0 0x4000>,
> +	      <0 0x63000000 0 0x400>,
> +	      <0 0x63100000 0 0x3000>,
> +	      <0 0x70b00000 0 0x3000>;

I'm still suspecting that we need multiple nodes, for each device
the clocks are embedded in. Mediatek SoCs have a similar design,
and they have many nodes. Does it happen to always be in some
fixed offset inside the different devices that use the clks?

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