From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 Date: Tue, 25 Jul 2017 17:36:18 -0700 Message-ID: <20170726003618.GG2146@codeaurora.org> References: <20170723102749.17323-1-icenowy@aosc.io> <20170723102749.17323-7-icenowy@aosc.io> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20170723102749.17323-7-icenowy@aosc.io> Sender: linux-kernel-owner@vger.kernel.org To: Icenowy Zheng Cc: Liam Girdwood , Mark Brown , Maxime Ripard , Chen-Yu Tsai , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-sunxi@googlegroups.com List-Id: devicetree@vger.kernel.org On 07/23, Icenowy Zheng wrote: > The CPUX clock, which is the main clock of the ARM core on Allwinner H3, > can be adjusted by changing the frequency of the PLL_CPUX clock. > > Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX > clock can be adjusted when adjusting the CPUX clock. > > Signed-off-by: Icenowy Zheng > --- Acked-by: Stephen Boyd -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project