From: SZ Lin <sz.lin@moxa.com>
Cc: SZ Lin <sz.lin@moxa.com>, Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Russell King <linux@armlinux.org.uk>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH] ARM: dts: ls1021a: Add support for QSPI with ls1021a SoC
Date: Wed, 9 Aug 2017 09:59:09 +0800 [thread overview]
Message-ID: <20170809015909.12969-1-sz.lin@moxa.com> (raw)
Add QSPI node support, and this function is disabled by default
This setting could be overwritten in board-level definitions
Signed-off-by: SZ Lin <sz.lin@moxa.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 7bb9df2c1460..9da876e47810 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -154,6 +154,20 @@
big-endian;
};
+ qspi: quadspi@1550000 {
+ compatible = "fsl,ls1021a-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1550000 0x0 0x10000>,
+ <0x0 0x40000000 0x0 0x40000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "qspi_en", "qspi";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>;
+ big-endian;
+ status = "disabled";
+ };
+
esdhc: esdhc@1560000 {
compatible = "fsl,esdhc";
reg = <0x0 0x1560000 0x0 0x10000>;
--
2.14.0
next reply other threads:[~2017-08-09 1:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-09 1:59 SZ Lin [this message]
[not found] ` <CAFk6z8OwHJa5v65gCKTPzaoA_eHw7aud4uZikNZATr5kXe7kGw@mail.gmail.com>
[not found] ` <CAFk6z8OwHJa5v65gCKTPzaoA_eHw7aud4uZikNZATr5kXe7kGw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-08-21 8:38 ` [PATCH] ARM: dts: ls1021a: Add support for QSPI with ls1021a SoC SZ Lin (林上智)
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