From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Abhishek Sahu <absahu@codeaurora.org>
Cc: dwmw2@infradead.org, computersforpeace@gmail.com,
marek.vasut@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
richard@nod.at, cyrille.pitchen@wedev4u.fr,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
andy.gross@linaro.org, architt@codeaurora.org,
sricharan@codeaurora.org, stable@vger.kernel.org
Subject: Re: [PATCH v3 01/20] mtd: nand: qcom: program NAND_DEV_CMD_VLD register
Date: Thu, 10 Aug 2017 11:42:50 +0200 [thread overview]
Message-ID: <20170810114250.6663a6b0@bbrezillon> (raw)
In-Reply-To: <1501949998-29859-2-git-send-email-absahu@codeaurora.org>
Le Sat, 5 Aug 2017 21:49:39 +0530,
Abhishek Sahu <absahu@codeaurora.org> a écrit :
> The NAND page read fails without complete boot chain since
> NAND_DEV_CMD_VLD value is not proper. The default power on reset
> value for this register is
>
> 0xe - ERASE_START_VALID | WRITE_START_VALID | READ_STOP_VALID
>
> The READ_START_VALID should be enabled for sending PAGE_READ
> command. READ_STOP_VALID should be cleared since normal NAND
> page read does not require READ_STOP command.
>
> Fixes: c76b78d8ec05a ("mtd: nand: Qualcomm NAND controller driver")
> Cc: stable@vger.kernel.org
> Reviewed-by: Archit Taneja <architt@codeaurora.org>
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
> drivers/mtd/nand/qcom_nandc.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index 0289f09..7406019 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -110,6 +110,10 @@
>
> /* NAND_DEV_CMD_VLD bits */
> #define READ_START_VLD 0
> +#define READ_STOP_VALID 1
> +#define WRITE_START_VALID 2
> +#define ERASE_START_VALID 3
> +#define SEQ_READ_START_VLD 4
Why not
#define READ_START_VLD BIT(0)
#define READ_STOP_VALID BIT(1)
#define WRITE_START_VALID BIT(2)
#define ERASE_START_VALID BIT(3)
#define SEQ_READ_START_VLD BIT(4)
>
> /* NAND_EBI2_ECC_BUF_CFG bits */
> #define NUM_STEPS 0
> @@ -148,6 +152,12 @@
> #define FETCH_ID 0xb
> #define RESET_DEVICE 0xd
>
> +/* Default Value for NAND_DEV_CMD_VLD */
> +#define NAND_DEV_CMD_VLD_VAL (BIT(READ_START_VLD) | \
> + BIT(WRITE_START_VALID) | \
> + BIT(ERASE_START_VALID) | \
> + BIT(SEQ_READ_START_VLD))
> +
and then:
#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | \
WRITE_START_VALID | \
ERASE_START_VALID | \
SEQ_READ_START_VLD)
BTW, can you use consistent suffixes? Sometime definitions are suffixed
with _VLD and others are suffixed with _VALID.
> /*
> * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -1995,13 +2005,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
> {
> /* kill onenand */
> nandc_write(nandc, SFLASHC_BURST_CFG, 0);
> + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>
> /* enable ADM DMA */
> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
>
> /* save the original values of these registers */
> nandc->cmd1 = nandc_read(nandc, NAND_DEV_CMD1);
> - nandc->vld = nandc_read(nandc, NAND_DEV_CMD_VLD);
> + nandc->vld = NAND_DEV_CMD_VLD_VAL;
>
> return 0;
> }
next prev parent reply other threads:[~2017-08-10 9:42 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-05 16:19 [PATCH v3 00/20] Add QCOM QPIC NAND support Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 01/20] mtd: nand: qcom: program NAND_DEV_CMD_VLD register Abhishek Sahu
2017-08-10 9:42 ` Boris Brezillon [this message]
2017-08-10 10:31 ` Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 02/20] mtd: nand: qcom: support for NAND controller properties Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 03/20] mtd: nand: qcom: add bam property for QPIC NAND controller Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 04/20] mtd: nand: qcom: add and initialize QPIC DMA resources Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 05/20] mtd: nand: qcom: DMA mapping support for register read buffer Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 06/20] mtd: nand: qcom: allocate BAM transaction Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 07/20] mtd: nand: qcom: add BAM DMA descriptor handling Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 08/20] mtd: nand: qcom: support for passing flags in transfer functions Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 09/20] mtd: nand: qcom: support for read location registers Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 10/20] mtd: nand: qcom: erased codeword detection configuration Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 11/20] mtd: nand: qcom: enable BAM or ADM mode Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 12/20] mtd: nand: qcom: QPIC data descriptors handling Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 13/20] mtd: nand: qcom: support for different DEV_CMD register offsets Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 15/20] mtd: nand: qcom: support for command descriptor formation Abhishek Sahu
2017-08-09 8:32 ` Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 16/20] dt-bindings: qcom_nandc: fix the ipq806x device tree example Abhishek Sahu
[not found] ` <1501949998-29859-17-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-10 20:26 ` Rob Herring
2017-08-05 16:19 ` [PATCH v3 17/20] dt-bindings: qcom_nandc: IPQ4019 QPIC NAND documentation Abhishek Sahu
[not found] ` <1501949998-29859-18-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-10 20:27 ` Rob Herring
2017-08-05 16:19 ` [PATCH v3 18/20] dt-bindings: qcom_nandc: IPQ8074 " Abhishek Sahu
2017-08-10 20:30 ` Rob Herring
2017-08-11 9:02 ` Abhishek Sahu
[not found] ` <1501949998-29859-1-git-send-email-absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-08-05 16:19 ` [PATCH v3 14/20] mtd: nand: qcom: add command elements in BAM transaction Abhishek Sahu
2017-08-09 8:29 ` Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 19/20] mtd: nand: qcom: Support for IPQ4019 QPIC NAND controller Abhishek Sahu
2017-08-05 16:19 ` [PATCH v3 20/20] mtd: nand: qcom: Support for IPQ8074 " Abhishek Sahu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170810114250.6663a6b0@bbrezillon \
--to=boris.brezillon@free-electrons.com \
--cc=absahu@codeaurora.org \
--cc=andy.gross@linaro.org \
--cc=architt@codeaurora.org \
--cc=computersforpeace@gmail.com \
--cc=cyrille.pitchen@wedev4u.fr \
--cc=devicetree@vger.kernel.org \
--cc=dwmw2@infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=marek.vasut@gmail.com \
--cc=mark.rutland@arm.com \
--cc=richard@nod.at \
--cc=robh+dt@kernel.org \
--cc=sricharan@codeaurora.org \
--cc=stable@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).