From mboxrd@z Thu Jan 1 00:00:00 1970 From: Romain Perier Subject: [PATCH] ARM: dts: rockchip: set PLLs and core clocks rates for RK3188 Date: Thu, 10 Aug 2017 13:46:25 +0200 Message-ID: <20170810114625.28823-1-romain.perier@collabora.com> Return-path: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Heiko Stuebner Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Romain Perier List-Id: devicetree@vger.kernel.org Currently, rates for PLLs or core peri clocks are not set to a specific rate when booting the kernel. Depending on the previously used bootloader the state of the clk tree can be good or not. This commits set PLLs and core clocks rates by using the assigned-clocks property in CRU (like for RK3288) Signed-off-by: Romain Perier --- arch/arm/boot/dts/rk3188.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 1399bc04ea77..de6bde651cc2 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -160,6 +160,17 @@ #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_DPLL>, + <&cru PLL_CPLL>, <&cru PLL_APLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + + assigned-clock-rates = <891000000>, <300000000>, + <132000000>, <312000000>, + <148500000>, <148500000>, + <74250000>, <127285715>, + <127285715>, <63642858>; }; efuse: efuse@20010000 { -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html