From: Vignesh R <vigneshr@ti.com>
To: Marek Vasut <marek.vasut@gmail.com>,
Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>,
Rob Herring <robh+dt@kernel.org>
Cc: David Woodhouse <dwmw2@infradead.org>,
Brian Norris <computersforpeace@gmail.com>,
Boris Brezillon <boris.brezillon@free-electrons.com>,
Richard Weinberger <richard@nod.at>,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Vignesh R <vigneshr@ti.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v2 4/5] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit
Date: Wed, 16 Aug 2017 10:20:52 +0530 [thread overview]
Message-ID: <20170816045053.15492-5-vigneshr@ti.com> (raw)
In-Reply-To: <20170816045053.15492-1-vigneshr@ti.com>
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.
Based on DT parameter cdns,rclk-en enable adapted loop-back circuit
for boards which do have QSPI return clock provided.
This patch also modifies cqspi_readdata_capture() function's bypass
parameter to bool to match how its used in the function.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
v2:
Split doc update to separate patch
drivers/mtd/spi-nor/cadence-quadspi.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index bb0cb02a6938..c11ced529ddd 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -78,6 +78,7 @@ struct cqspi_st {
bool is_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
+ bool rclk_en;
u32 trigger_address;
u32 wr_delay;
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
@@ -788,7 +789,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
}
static void cqspi_readdata_capture(struct cqspi_st *cqspi,
- const unsigned int bypass,
+ const bool bypass,
const unsigned int delay)
{
void __iomem *reg_base = cqspi->iobase;
@@ -852,7 +853,8 @@ static void cqspi_configure(struct spi_nor *nor)
cqspi->sclk = sclk;
cqspi_config_baudrate_div(cqspi);
cqspi_delay(nor);
- cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
+ cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
+ f_pdata->read_delay);
}
if (switch_cs || switch_ck)
@@ -1049,6 +1051,8 @@ static int cqspi_of_get_pdata(struct platform_device *pdev)
return -ENXIO;
}
+ cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
+
return 0;
}
--
2.14.1
next prev parent reply other threads:[~2017-08-16 4:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-16 4:50 [PATCH v2 0/5] K2G: Add QSPI support Vignesh R
2017-08-16 4:50 ` [PATCH v2 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Vignesh R
2017-08-17 21:59 ` Rob Herring
2017-08-16 4:50 ` [PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Vignesh R
2017-08-16 4:50 ` [PATCH v2 3/5] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit Vignesh R
2017-08-17 22:00 ` Rob Herring
2017-08-16 4:50 ` Vignesh R [this message]
2017-08-16 4:50 ` [PATCH v2 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support Vignesh R
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