[PATCH v1 0/3] arm: npcm: add basic support for Nuvoton BMCs

[PATCH v1 0/3] arm: npcm: add basic support for Nuvoton BMCs

[Brendan Higgins]

This patch set adds support for the Nuvoton NPCM Baseboard Management Controller
(BMC) SoC architecture as well as the NPCM750 variant. NPCM is an ARM based SoC
with external DDR RAM and supports a large set of peripherals.

The NPCM750 is based on Cortex A9 and comes in single core and dual core
flavors.

The device tree added in this patchset has a number of bindings for which the
corresponding drivers will be sent out later and thus do not yet have binding
documentation. Apologies in advance if you would like the bindings to be added
along with the corresponding drivers.

Thanks!

[PATCH v1 1/3] arm: npcm: add basic support for Nuvoton BMCs

[Brendan Higgins]

Adds basic support for the Nuvoton NPCM750 BMC.

Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
---
 arch/arm/Kconfig             |   2 +
 arch/arm/Makefile            |   1 +
 arch/arm/mach-npcm/Kconfig   |  60 +++++++++++++++
 arch/arm/mach-npcm/Makefile  |   3 +
 arch/arm/mach-npcm/headsmp.S | 120 ++++++++++++++++++++++++++++++
 arch/arm/mach-npcm/npcm7xx.c |  34 +++++++++
 arch/arm/mach-npcm/platsmp.c | 170 +++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 390 insertions(+)
 create mode 100644 arch/arm/mach-npcm/Kconfig
 create mode 100644 arch/arm/mach-npcm/Makefile
 create mode 100644 arch/arm/mach-npcm/headsmp.S
 create mode 100644 arch/arm/mach-npcm/npcm7xx.c
 create mode 100644 arch/arm/mach-npcm/platsmp.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 61a0cb15067e..05543f1cfbde 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -782,6 +782,8 @@ source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-nomadik/Kconfig"
 
+source "arch/arm/mach-npcm/Kconfig"
+
 source "arch/arm/mach-nspire/Kconfig"
 
 source "arch/arm/plat-omap/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 47d3a1ab08d2..60ca50c7d762 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -191,6 +191,7 @@ machine-$(CONFIG_ARCH_MEDIATEK)		+= mediatek
 machine-$(CONFIG_ARCH_MXS)		+= mxs
 machine-$(CONFIG_ARCH_NETX)		+= netx
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
+machine-$(CONFIG_ARCH_NPCM)		+= npcm
 machine-$(CONFIG_ARCH_NSPIRE)		+= nspire
 machine-$(CONFIG_ARCH_OXNAS)		+= oxnas
 machine-$(CONFIG_ARCH_OMAP1)		+= omap1
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
new file mode 100644
index 000000000000..82714b8a890f
--- /dev/null
+++ b/arch/arm/mach-npcm/Kconfig
@@ -0,0 +1,60 @@
+menuconfig ARCH_NPCM
+	bool "Nuvoton NPCM Architecture"
+	select ARCH_REQUIRE_GPIOLIB
+	select USE_OF
+	select PINCTRL
+	select PINCTRL_NPCM7XX
+
+if ARCH_NPCM
+
+comment "NPCMX50 CPU type"
+
+config CPU_NPCM750
+	depends on ARCH_NPCM
+	bool "Support for NPCM750 BMC CPU (Poleg)"
+	select CACHE_L2X0
+	select CPU_V7
+	select ARM_GIC
+	select ARM_ERRATA_754322
+	select ARM_ERRATA_764369
+	select USB_EHCI_ROOT_HUB_TT
+	select USB_ARCH_HAS_HCD
+	select USB_ARCH_HAS_EHCI
+	select USB_EHCI_HCD
+	select USB_ARCH_HAS_OHCI
+	select USB_OHCI_HCD
+	select USB
+	select FIQ
+	select CPU_USE_DOMAINS
+	select COMMON_CLK if OF
+	select NPCM750_TIMER
+	select MFD_SYSCON
+	help
+	  Support for single core NPCM750 BMC CPU (Poleg).
+
+	  Single core variant of the Nuvoton NPCM750 BMC based on the Cortex A9.
+
+config CPU_NPCM750_SMP
+	depends on ARCH_NPCM
+	bool "Support for NPCM750 BMC CPU SMP (Poleg)"
+	select HAVE_SMP
+	select HAVE_ARM_SCU
+	select ARM_ERRATA_458693
+	select ARM_ERRATA_742231
+	select ARM_ERRATA_794072
+	select PL310_ERRATA_588369
+	select PL310_ERRATA_727915
+	select ARM_ERRATA_720789
+	select DEBUG_SPINLOCK
+	select GENERIC_CLOCKEVENTS
+	select SMP
+	select HAVE_ARM_TWD if SMP
+	select HAVE_ARM_SCU if SMP
+	select CLKDEV_LOOKUP
+	select COMMON_CLK if OF
+	help
+	  Support for dual core NPCM750 BMC CPU (Poleg).
+
+	  Dual core variant of the Nuvoton NPCM750 BMC based on the Cortex A9.
+
+endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
new file mode 100644
index 000000000000..e7d27340f968
--- /dev/null
+++ b/arch/arm/mach-npcm/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
+
+obj-$(CONFIG_ARCH_NPCM)		+= npcm7xx.o
diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S
new file mode 100644
index 000000000000..d22d2fc1a35c
--- /dev/null
+++ b/arch/arm/mach-npcm/headsmp.S
@@ -0,0 +1,120 @@
+/*
+ * linux/arch/arm/mach-realview/headsmp.S
+ *
+ * Copyright (c) 2003 ARM Limited
+ * Copyright 2017 Google, Inc.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+.equ SVC_MODE, 0x13
+.equ I_BIT, 0x80
+.equ F_BIT, 0x40
+
+ENTRY(npcm7xx_wakeup_z1)
+	stmfd	sp!, {r0-r12, lr}
+	ldr	r0, =0x01
+	ldr	r1, =0x01
+	ldr	r2, =0x01
+
+	and	r3, r0, #0x0F /* Mask off unused bits of ID, and move to r3 */
+	and	r1, r1, #0x0F /* Mask off unused bits of target_filter */
+	and	r2, r2, #0x0F /* Mask off unused bits of filter_list */
+
+	orr	r3, r3, r1, LSL #16 /* Combine ID and target_filter */
+	orr	r3, r3, r2, LSL #24 /* and now the filter list */
+
+	/* Get the address of the GIC */
+	mrc	p15, 4, r0, c15, c0, 0 /* Read periph base address */
+	add	r0, r0, #0x1F00 /* Add offset of the sgi_trigger reg */
+
+	/* Write to the Software Generated Interrupt Register (ICDSGIR) */
+	str	r3, [r0]
+
+	ldmfd	sp!, {r0-r12, pc}
+ENDPROC(npcm7xx_wakeup_z1)
+
+ENTRY(v7_invalidate_l1_npcmX50)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0 /* invalidate I cache */
+	mcr	p15, 2, r0, c0, c0, 0
+	mrc	p15, 1, r0, c0, c0, 0
+
+	ldr	r1, =0x7fff
+	and	r2, r1, r0, lsr #13
+
+	ldr	r1, =0x3ff
+
+	and	r3, r1, r0, lsr #3 /* NumWays - 1 */
+	add	r2, r2, #1         /* NumSets */
+
+	and	r0, r0, #0x7
+	add	r0, r0, #4 /* SetShift */
+
+	clz	r1, r3     /* WayShift */
+	add	r4, r3, #1 /* NumWays */
+1:	sub	r2, r2, #1 /* NumSets-- */
+	mov	r3, r4     /* Temp = NumWays */
+2:	subs	r3, r3, #1 /* Temp-- */
+	mov	r5, r3, lsl r1
+	mov	r6, r2, lsl r0
+	/* Reg = (Temp << WayShift) | (NumSets << SetShift) */
+	orr	r5, r5, r6
+	mcr	p15, 0, r5, c7, c6, 2
+	bgt	2b
+	cmp	r2, #0
+	bgt	1b
+	dsb
+	isb
+	mov	pc, lr
+ENDPROC(v7_invalidate_l1_npcmX50)
+
+/*
+ * MSM specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(npcm7xx_secondary_startup)
+	msr	CPSR_c, #(SVC_MODE)
+
+	bl	v7_invalidate_l1_npcmX50
+	/* disable vector table remapping */
+	mrc	p15, 0,r0, c1, c0, 0
+	and	r0, #0xffffdfff
+	mcr	p15, 0,r0, c1, c0, 0
+
+#ifdef CONFIG_CACHE_L2X0
+	/* Enable L1 & L2 prefetch + Zero line */
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #(7 << 1)
+	mcr	p15, 0, r0, c1, c0, 1
+#endif /* CONFIG_CACHE_L2X0 */
+
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15
+	adr	r4, 1f
+	ldmia	r4, {r5, r6}
+	sub	r4, r4, r5
+	add	r6, r6, r4
+	str r3,[r2]
+
+pen:	ldr	r7, [r6]
+	cmp	r7, r0
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	b	secondary_startup
+ENDPROC(npcm7xx_secondary_startup)
+
+	.align
+1:	.long	.
+	.long	pen_release
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
new file mode 100644
index 000000000000..8ff4b269db14
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Nuvoton Technology corporation.
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#define NPCM7XX_AUX_VAL (L310_AUX_CTRL_INSTR_PREFETCH |			       \
+			 L310_AUX_CTRL_DATA_PREFETCH |			       \
+			 L310_AUX_CTRL_NS_LOCKDOWN |			       \
+			 L310_AUX_CTRL_CACHE_REPLACE_RR |		       \
+			 L2C_AUX_CTRL_SHARED_OVERRIDE |			       \
+			 L310_AUX_CTRL_FULL_LINE_ZERO)
+
+static const char *const npcm7xx_dt_match[] = {
+	"nuvoton,npcm7xx",
+	NULL
+};
+
+DT_MACHINE_START(NPCM7XX_DT, "NPCMX50 Chip family")
+	.atag_offset	= 0x100,
+	.dt_compat	= npcm7xx_dt_match,
+	.l2c_aux_val	= NPCM7XX_AUX_VAL,
+	.l2c_aux_mask	= ~NPCM7XX_AUX_VAL,
+MACHINE_END
diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c
new file mode 100644
index 000000000000..181a71510acb
--- /dev/null
+++ b/arch/arm/mach-npcm/platsmp.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2002 ARM Ltd.
+ * Copyright (C) 2008 STMicroelctronics.
+ * Copyright (C) 2009 ST-Ericsson.
+ * Copyright 2017 Google, Inc.
+ *
+ * This file is based on arm realview platform
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+#include <asm/smp.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#define NPCM7XX_SCRPAD_REG 0x13c
+
+static void __iomem *gcr_base;
+static void __iomem *scu_base;
+
+/* This is called from headsmp.S to wakeup the secondary core */
+extern void npcm7xx_secondary_startup(void);
+extern void npcm7xx_wakeup_z1(void);
+
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void npcm7xx_write_pen_release(int val)
+{
+	pen_release = val;
+	/* write to pen_release must be visible to all observers. */
+	smp_wmb();
+	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static void npcm7xx_smp_secondary_init(unsigned int cpu)
+{
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	npcm7xx_write_pen_release(-1);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+static int npcm7xx_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting pen_release.
+	 */
+	npcm7xx_write_pen_release(cpu_logical_map(cpu));
+	iowrite32(virt_to_phys(npcm7xx_secondary_startup),
+		  gcr_base + NPCM7XX_SCRPAD_REG);
+	/* make npcm7xx_secondary_startup visible to all observers. */
+	smp_rmb();
+
+	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+	timeout  = jiffies + (HZ * 1);
+	while (time_before(jiffies, timeout)) {
+		/* make sure we see any writes to pen_release. */
+		smp_rmb();
+		if (pen_release == -1)
+			break;
+
+		udelay(10);
+	}
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return pen_release != -1 ? -EIO : 0;
+}
+
+
+static void __init npcm7xx_wakeup_secondary(void)
+{
+	/*
+	 * write the address of secondary startup into the backup ram register
+	 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
+	 * backup ram register at offset 0x1FF0, which is what boot rom code
+	 * is waiting for. This would wake up the secondary core from WFE
+	 */
+	iowrite32(virt_to_phys(npcm7xx_secondary_startup), gcr_base +
+		  NPCM7XX_SCRPAD_REG);
+	/* make sure npcm7xx_secondary_startup is seen by all observers. */
+	smp_wmb();
+	dsb_sev();
+
+	/* make sure write buffer is drained */
+	mb();
+}
+
+static void __init npcm7xx_smp_init_cpus(void)
+{
+	struct device_node *gcr_np, *scu_np;
+	unsigned int i, ncores;
+
+	gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
+	gcr_base = of_iomap(gcr_np, 0);
+	if (IS_ERR(gcr_base)) {
+		pr_err("no gcr device node: %ld\n", PTR_ERR(gcr_base));
+		return;
+	}
+
+	scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+	scu_base = of_iomap(scu_np, 0);
+	if (IS_ERR(scu_base)) {
+		pr_err("no scu device node: %ld\n", PTR_ERR(scu_base));
+		return;
+	}
+
+	ncores = scu_get_core_count(scu_base);
+
+	if (ncores > nr_cpu_ids) {
+		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+			ncores, nr_cpu_ids);
+		ncores = nr_cpu_ids;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+}
+
+static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
+{
+	scu_enable(scu_base);
+	npcm7xx_wakeup_secondary();
+}
+
+static struct smp_operations npcm7xx_smp_ops __initdata = {
+	.smp_init_cpus    = npcm7xx_smp_init_cpus,
+	.smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
+	.smp_boot_secondary = npcm7xx_smp_boot_secondary,
+	.smp_secondary_init = npcm7xx_smp_secondary_init,
+};
+
+CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm7xx-smp", &npcm7xx_smp_ops);
-- 
2.14.1.480.gb18f417b89-goog

[PATCH v1 2/3] arm: dts: add Nuvoton NPCM750 device tree

[Brendan Higgins]

Add a common device tree for all Nuvoton NPCM750 BMCs and a board
specific device tree for the NPCM750 (Poleg) evaluation board.

Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
---
 .../devicetree/bindings/arm/npcm/npcm.txt          |   6 +
 arch/arm/boot/dts/nuvoton-npcm750-evb.dts          |  63 ++++++
 arch/arm/boot/dts/nuvoton-npcm750.dtsi             | 222 +++++++++++++++++++++
 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h   |  39 ++++
 4 files changed, 330 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts
 create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
 create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h

diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
new file mode 100644
index 000000000000..19aabe9a7414
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
@@ -0,0 +1,6 @@
+NPCM Platforms Device Tree Bindings
+-----------------------------------
+NPCM750 SoC
+Required root node properties:
+	- compatible = "nuvoton,npcm750";
+	- enable-method = "nuvoton,npcm7xx-smp"; required for dual core variant.
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
new file mode 100644
index 000000000000..10f523388dc1
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -0,0 +1,63 @@
+/*
+ * DTS file for all NPCM750 SoCs
+ *
+ * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "nuvoton-npcm750.dtsi"
+
+/ {
+	model = "Nuvoton npcm750 Development Board (Device Tree)";
+	compatible = "nuvoton,npcm750";
+	enable-method = "nuvoton,npcm7xx-smp";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	clocks {
+		clk: clock-controller@f0801000 {
+			status = "okay";
+		};
+	};
+
+	ahb {
+	};
+
+	apb {
+		watchdog1: watchdog@f0009000 {
+			status = "okay";
+		};
+
+		uart0: uart0@f0001000 {
+			status = "okay";
+		};
+
+		uart1: uart1@f0002000 {
+			status = "okay";
+		};
+
+		uart2: uart2@f0003000 {
+			status = "okay";
+		};
+
+		uart3: uart3@f0004000 {
+			status = "okay";
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
new file mode 100644
index 000000000000..fc64550c49a6
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -0,0 +1,222 @@
+/*
+ * DTSi file for the NPCM750 SoC
+ *
+ * Copyright 2012 Tomer Maimon <tomer.maimon@nuvoton.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h>
+
+/ {
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			clocks = <&clk NPCM7XX_CLK_CPU>;
+			clock-names = "clk_cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0xf03fc000 0x80000>;
+		interrupts = <0 21 4>;
+		cache-unified;
+		cache-level = <2>;
+		clocks = <&clk NPCM7XX_CLK_AXI>;
+		clock-names = "clk_axi";
+	    };
+
+	    clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		clk: clock-controller@f0801000 {
+			compatible = "nuvoton,npcm750-clk";
+			#clock-cells = <1>;
+		};
+
+		/* external clock signal rg1refck, supplied by the phy */
+		clk_rg1refck: clk_rg1refck {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <125000000>;
+			clock-output-names = "clk_rg1refck";
+		};
+
+		/* external clock signal rg2refck, supplied by the phy */
+		clk_rg2refck: clk_rg2refck {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <125000000>;
+			clock-output-names = "clk_rg2refck";
+		};
+
+		clk_xin: clk_xin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			clock-output-names = "clk_xin";
+		};
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges = <0x80000000 0x80000000 0x20000000 /* AHB18 */
+			0xa0000000 0xa0000000 0x28000000 /* AHB3  */
+			0xe0000000 0xe0000000 0x10000000 /* AHB14 */
+			0xf0000000 0xf0000000 0x00800000 /* AHB1  */
+			0xf0800000 0xf0800000 0x00800000 /* AHB8  */
+			0xf8000000 0xf8000000 0x04000000  /* AHB18 - cont */
+			0xfffd0000 0xfffd0000 0x00040000>;   /* RAM2 */
+
+		gic: interrupt-controller@f03ff000 {
+			compatible = "arm,cortex-a9-gic";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0xf03ff000 0x1000>,
+			    <0xf03fe100 0x100>;
+		};
+
+		gcr: gcr@f0800000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "nuvoton,npcm750-gcr", "syscon",
+				"simple-mfd";
+			reg = <0xf0800000 0x1000>;
+		};
+
+		scu: scu@f03fe000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "arm,cortex-a9-scu";
+			reg = <0xf03fe000 0x1000>;
+		};
+
+		clk_rst: clk_rst@f0801000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "nuvoton,npcm750-clk_rst", "syscon",
+				"simple-mfd";
+			reg = <0xF0801000 0x1000>;
+		};
+
+		twd: timer@f03fe600 {
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xf03fe600 0x20>;
+			interrupts = <1 13 0x304>;
+		};
+	};
+
+	apb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges = <0xf0000000 0xf0000000 0x00080000
+			0xf0080000 0xf0080000 0x00080000
+			0xf0100000 0xf0100000 0x00080000
+			0xf0180000 0xf0180000 0x00080000
+			0xf0200000 0xf0200000 0x00600000>;
+
+		timer0: timer@f0000000 {
+			compatible = "nuvoton,npcm750-timer";
+			interrupts = <0 32 4>;
+			clocks = <&clk NPCM7XX_CLK_TIMER>;
+			clock-names = "clk_timer";
+		};
+
+		watchdog0: watchdog@f0008000 {
+			compatible = "nuvoton,npcm750-wdt";
+			interrupts = <0 47 4>;
+			reg = <0xf0008000 0x1000>;
+			status = "disabled";
+			clocks = <&clk NPCM7XX_CLK_TIMER>;
+			clock-names = "clk_timer";
+		};
+
+		watchdog1: watchdog@f0009000 {
+			compatible = "nuvoton,npcm750-wdt";
+			interrupts = <0 48 4>;
+			reg = <0xf0009000 0x1000>;
+			status = "disabled";
+			clocks = <&clk NPCM7XX_CLK_TIMER>;
+			clock-names = "clk_timer";
+		};
+
+		watchdog2: watchdog@f000a000 {
+			compatible = "nuvoton,npcm750-wdt";
+			interrupts = <0 49 4>;
+			reg = <0xf000a000 0x1000>;
+			status = "disabled";
+			clocks = <&clk NPCM7XX_CLK_TIMER>;
+			clock-names = "clk_timer";
+		};
+
+		uart0: uart0@f0001000 {
+			compatible = "nuvoton,npcm750-uart";
+			reg = <0xf0001000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+			clock-names = "clk_uart";
+			interrupts = <0 2 4>;
+			status = "disabled";
+		};
+
+		uart1: uart1@f0002000 {
+			compatible = "nuvoton,npcm750-uart";
+			reg = <0xf0002000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+			clock-names = "clk_uart";
+			interrupts = <0 3 4>;
+			status = "disabled";
+		};
+
+		uart2: uart2@f0003000 {
+			compatible = "nuvoton,npcm750-uart";
+			reg = <0xf0003000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+			clock-names = "clk_uart";
+			interrupts = <0 4 4>;
+			status = "disabled";
+		};
+
+		uart3: uart3@f0004000 {
+			compatible = "nuvoton,npcm750-uart";
+			reg = <0xf0004000 0x1000>;
+			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
+			clock-names = "clk_uart";
+			interrupts = <0 5 4>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
new file mode 100644
index 000000000000..c69d3bbf7e42
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2016 Nuvoton Technologies,  tali.perry@nuvoton.com
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ */
+
+#ifndef _DT_BINDINGS_CLK_NPCM7XX_H
+#define _DT_BINDINGS_CLK_NPCM7XX_H
+
+#define NPCM7XX_CLK_PLL0	0
+#define NPCM7XX_CLK_PLL1	1
+#define NPCM7XX_CLK_PLL2	2
+#define NPCM7XX_CLK_GFX		3
+#define NPCM7XX_CLK_APB1	4
+#define NPCM7XX_CLK_APB2	5
+#define NPCM7XX_CLK_APB3	6
+#define NPCM7XX_CLK_APB4	7
+#define NPCM7XX_CLK_APB5	8
+#define NPCM7XX_CLK_MC		9
+#define NPCM7XX_CLK_CPU		10
+#define NPCM7XX_CLK_SPI0	11
+#define NPCM7XX_CLK_SPI3	12
+#define NPCM7XX_CLK_SPIX	13
+#define NPCM7XX_CLK_UART_CORE	14
+#define NPCM7XX_CLK_TIMER	15
+#define NPCM7XX_CLK_HOST_UART	16
+#define NPCM7XX_CLK_MMC		17
+#define NPCM7XX_CLK_SDHC	18
+#define NPCM7XX_CLK_ADC		19
+#define NPCM7XX_CLK_GFX_MEM	20
+#define NPCM7XX_CLK_USB_BRIDGE	21
+#define NPCM7XX_CLK_AXI		22
+#define NPCM7XX_CLK_AHB		23
+#define NPCM7XX_CLK_EMC		24
+#define NPCM7XX_CLK_GMAC	25
+
+#endif
-- 
2.14.1.480.gb18f417b89-goog

[PATCH v1 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture

[Brendan Higgins]

Add maintainers and reviewers for the Nuvoton NPCM architecture.

Signed-off-by: Brendan Higgins <brendanhiggins@google.com>
---
 MAINTAINERS | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 44cb004c765d..67064bf11904 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1598,6 +1598,19 @@ F:	drivers/pinctrl/nomadik/
 F:	drivers/i2c/busses/i2c-nomadik.c
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git
 
+ARM/NUVOTON NPCM ARCHITECTURE
+M:	Avi Fishman <avifishman70@gmail.com>
+M:	Tomer Maimon <tmaimon77@gmail.com>
+R:	Brendan Higgins <brendanhiggins@google.com>
+R:	Rick Altherr <raltherr@google.com>
+L:	openbmc@lists.ozlabs.org (moderated for non-subscribers)
+S:	Maintained
+F:	arch/arm/mach-npcm/
+F:	arch/arm/boot/dts/nuvoton-npcm*
+F:	include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
+F:	drivers/*/*npcm*
+F:	Documentation/*/*npcm*
+
 ARM/NUVOTON W90X900 ARM ARCHITECTURE
 M:	Wan ZongShun <mcuos.com@gmail.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.14.1.480.gb18f417b89-goog

Re: [PATCH v1 1/3] arm: npcm: add basic support for Nuvoton BMCs

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1132 bytes --]

Hi Brendan,

[auto build test WARNING on linus/master]
[also build test WARNING on v4.13-rc6 next-20170823]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Brendan-Higgins/arm-npcm-add-basic-support-for-Nuvoton-BMCs/20170824-031106
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All warnings (new ones prefixed by >>):

warning: (CPU_NPCM750_SMP) selects ARM_ERRATA_458693 which has unmet direct dependencies (CPU_V7 && !ARCH_MULTIPLATFORM)
warning: (CPU_NPCM750_SMP) selects ARM_ERRATA_742231 which has unmet direct dependencies (CPU_V7 && SMP && !ARCH_MULTIPLATFORM)

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
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Re: [PATCH v1 1/3] arm: npcm: add basic support for Nuvoton BMCs

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2146 bytes --]

Hi Brendan,

[auto build test ERROR on linus/master]
[also build test ERROR on v4.13-rc6 next-20170823]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Brendan-Higgins/arm-npcm-add-basic-support-for-Nuvoton-BMCs/20170824-031106
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   arch/arm/mach-npcm/headsmp.S: Assembler messages:
>> arch/arm/mach-npcm/headsmp.S:73: Error: selected processor does not support `dsb' in ARM mode
>> arch/arm/mach-npcm/headsmp.S:74: Error: selected processor does not support `isb' in ARM mode

vim +73 arch/arm/mach-npcm/headsmp.S

    42	
    43	ENTRY(v7_invalidate_l1_npcmX50)
    44		mov	r0, #0
    45		mcr	p15, 0, r0, c7, c5, 0 /* invalidate I cache */
    46		mcr	p15, 2, r0, c0, c0, 0
    47		mrc	p15, 1, r0, c0, c0, 0
    48	
    49		ldr	r1, =0x7fff
    50		and	r2, r1, r0, lsr #13
    51	
    52		ldr	r1, =0x3ff
    53	
    54		and	r3, r1, r0, lsr #3 /* NumWays - 1 */
    55		add	r2, r2, #1         /* NumSets */
    56	
    57		and	r0, r0, #0x7
    58		add	r0, r0, #4 /* SetShift */
    59	
    60		clz	r1, r3     /* WayShift */
    61		add	r4, r3, #1 /* NumWays */
    62	1:	sub	r2, r2, #1 /* NumSets-- */
    63		mov	r3, r4     /* Temp = NumWays */
    64	2:	subs	r3, r3, #1 /* Temp-- */
    65		mov	r5, r3, lsl r1
    66		mov	r6, r2, lsl r0
    67		/* Reg = (Temp << WayShift) | (NumSets << SetShift) */
    68		orr	r5, r5, r6
    69		mcr	p15, 0, r5, c7, c6, 2
    70		bgt	2b
    71		cmp	r2, #0
    72		bgt	1b
  > 73		dsb
  > 74		isb
    75		mov	pc, lr
    76	ENDPROC(v7_invalidate_l1_npcmX50)
    77	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 62836 bytes --]

Re: [PATCH v1 2/3] arm: dts: add Nuvoton NPCM750 device tree

[Rob Herring]

On Mon, Aug 21, 2017 at 08:35:01PM -0700, Brendan Higgins wrote:
> Add a common device tree for all Nuvoton NPCM750 BMCs and a board
> specific device tree for the NPCM750 (Poleg) evaluation board.
> 
> Signed-off-by: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> ---
>  .../devicetree/bindings/arm/npcm/npcm.txt          |   6 +
>  arch/arm/boot/dts/nuvoton-npcm750-evb.dts          |  63 ++++++
>  arch/arm/boot/dts/nuvoton-npcm750.dtsi             | 222 +++++++++++++++++++++
>  include/dt-bindings/clock/nuvoton,npcm7xx-clks.h   |  39 ++++
>  4 files changed, 330 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt
>  create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts
>  create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
>  create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
> 
> diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
> new file mode 100644
> index 000000000000..19aabe9a7414
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
> @@ -0,0 +1,6 @@
> +NPCM Platforms Device Tree Bindings
> +-----------------------------------
> +NPCM750 SoC
> +Required root node properties:
> +	- compatible = "nuvoton,npcm750";
> +	- enable-method = "nuvoton,npcm7xx-smp"; required for dual core variant.

enable-method is not a root node property. There's a file to document 
all of these.

> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> new file mode 100644
> index 000000000000..10f523388dc1
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> @@ -0,0 +1,63 @@
> +/*
> + * DTS file for all NPCM750 SoCs
> + *
> + * Copyright 2012 Tomer Maimon <tomer.maimon-KrzQf0k3Iz9BDgjK7y7TUQ@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/dts-v1/;
> +#include "nuvoton-npcm750.dtsi"
> +
> +/ {
> +	model = "Nuvoton npcm750 Development Board (Device Tree)";
> +	compatible = "nuvoton,npcm750";
> +	enable-method = "nuvoton,npcm7xx-smp";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +		serial3 = &uart3;
> +	};
> +
> +	memory {
> +		reg = <0 0x40000000>;
> +	};
> +
> +	clocks {
> +		clk: clock-controller@f0801000 {
> +			status = "okay";
> +		};
> +	};
> +
> +	ahb {
> +	};

You don't need this.

> +
> +	apb {
> +		watchdog1: watchdog@f0009000 {
> +			status = "okay";
> +		};
> +
> +		uart0: uart0@f0001000 {

Use generic node names.

s/uart/serial/

> +			status = "okay";
> +		};
> +
> +		uart1: uart1@f0002000 {
> +			status = "okay";
> +		};
> +
> +		uart2: uart2@f0003000 {
> +			status = "okay";
> +		};
> +
> +		uart3: uart3@f0004000 {
> +			status = "okay";
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
> new file mode 100644
> index 000000000000..fc64550c49a6
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
> @@ -0,0 +1,222 @@
> +/*
> + * DTSi file for the NPCM750 SoC
> + *
> + * Copyright 2012 Tomer Maimon <tomer.maimon-KrzQf0k3Iz9BDgjK7y7TUQ@public.gmane.org>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include "skeleton.dtsi"
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/nuvoton,npcm7xx-clks.h>
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			clocks = <&clk NPCM7XX_CLK_CPU>;
> +			clock-names = "clk_cpu";
> +			reg = <0>;
> +			next-level-cache = <&L2>;
> +		};
> +
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			clocks = <&clk NPCM7XX_CLK_CPU>;
> +			clock-names = "clk_cpu";
> +			reg = <1>;
> +			next-level-cache = <&L2>;
> +		};
> +
> +	};
> +
> +	L2: l2-cache {
> +		compatible = "arm,pl310-cache";
> +		reg = <0xf03fc000 0x80000>;

Pretty sure the PL310 doesn't have 512KB of address space.

> +		interrupts = <0 21 4>;
> +		cache-unified;
> +		cache-level = <2>;
> +		clocks = <&clk NPCM7XX_CLK_AXI>;
> +		clock-names = "clk_axi";

> +	    };
> +
> +	    clocks {

Indentation is wrong.

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		clk: clock-controller@f0801000 {

unit-address is not valid without a reg property. 

> +			compatible = "nuvoton,npcm750-clk";
> +			#clock-cells = <1>;
> +		};
> +
> +		/* external clock signal rg1refck, supplied by the phy */
> +		clk_rg1refck: clk_rg1refck {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <125000000>;
> +			clock-output-names = "clk_rg1refck";
> +		};
> +
> +		/* external clock signal rg2refck, supplied by the phy */
> +		clk_rg2refck: clk_rg2refck {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <125000000>;
> +			clock-output-names = "clk_rg2refck";
> +		};
> +
> +		clk_xin: clk_xin {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <50000000>;
> +			clock-output-names = "clk_xin";
> +		};

These 3 clocks are not part of the bus, so move to top level.

> +	};
> +
> +	ahb {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges = <0x80000000 0x80000000 0x20000000 /* AHB18 */
> +			0xa0000000 0xa0000000 0x28000000 /* AHB3  */
> +			0xe0000000 0xe0000000 0x10000000 /* AHB14 */
> +			0xf0000000 0xf0000000 0x00800000 /* AHB1  */
> +			0xf0800000 0xf0800000 0x00800000 /* AHB8  */
> +			0xf8000000 0xf8000000 0x04000000  /* AHB18 - cont */
> +			0xfffd0000 0xfffd0000 0x00040000>;   /* RAM2 */
> +
> +		gic: interrupt-controller@f03ff000 {
> +			compatible = "arm,cortex-a9-gic";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			reg = <0xf03ff000 0x1000>,
> +			    <0xf03fe100 0x100>;
> +		};
> +
> +		gcr: gcr@f0800000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "nuvoton,npcm750-gcr", "syscon",
> +				"simple-mfd";
> +			reg = <0xf0800000 0x1000>;
> +		};
> +
> +		scu: scu@f03fe000 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "arm,cortex-a9-scu";
> +			reg = <0xf03fe000 0x1000>;
> +		};
> +
> +		clk_rst: clk_rst@f0801000 {

Don't use '_' in node or property names.

Build your dtb with W=2 and fix any warnings.

> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "nuvoton,npcm750-clk_rst", "syscon",
> +				"simple-mfd";
> +			reg = <0xF0801000 0x1000>;
> +		};
> +
> +		twd: timer@f03fe600 {
> +			compatible = "arm,cortex-a9-twd-timer";
> +			reg = <0xf03fe600 0x20>;
> +			interrupts = <1 13 0x304>;
> +		};
> +	};
> +
> +	apb {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		ranges = <0xf0000000 0xf0000000 0x00080000
> +			0xf0080000 0xf0080000 0x00080000

You have overlapping addresses at least in the ranges. Make sure you 
don't actually have any regions overlapping.

It looks like you don't really need this entry.

> +			0xf0100000 0xf0100000 0x00080000
> +			0xf0180000 0xf0180000 0x00080000
> +			0xf0200000 0xf0200000 0x00600000>;
> +
> +		timer0: timer@f0000000 {
> +			compatible = "nuvoton,npcm750-timer";
> +			interrupts = <0 32 4>;
> +			clocks = <&clk NPCM7XX_CLK_TIMER>;
> +			clock-names = "clk_timer";

-names is pointless when there is only 1.

> +		};
> +
> +		watchdog0: watchdog@f0008000 {
> +			compatible = "nuvoton,npcm750-wdt";
> +			interrupts = <0 47 4>;
> +			reg = <0xf0008000 0x1000>;
> +			status = "disabled";
> +			clocks = <&clk NPCM7XX_CLK_TIMER>;
> +			clock-names = "clk_timer";
> +		};
> +
> +		watchdog1: watchdog@f0009000 {
> +			compatible = "nuvoton,npcm750-wdt";
> +			interrupts = <0 48 4>;
> +			reg = <0xf0009000 0x1000>;
> +			status = "disabled";
> +			clocks = <&clk NPCM7XX_CLK_TIMER>;
> +			clock-names = "clk_timer";
> +		};
> +
> +		watchdog2: watchdog@f000a000 {
> +			compatible = "nuvoton,npcm750-wdt";
> +			interrupts = <0 49 4>;
> +			reg = <0xf000a000 0x1000>;
> +			status = "disabled";
> +			clocks = <&clk NPCM7XX_CLK_TIMER>;
> +			clock-names = "clk_timer";
> +		};
> +
> +		uart0: uart0@f0001000 {
> +			compatible = "nuvoton,npcm750-uart";
> +			reg = <0xf0001000 0x1000>;
> +			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
> +			clock-names = "clk_uart";
> +			interrupts = <0 2 4>;
> +			status = "disabled";
> +		};
> +
> +		uart1: uart1@f0002000 {
> +			compatible = "nuvoton,npcm750-uart";
> +			reg = <0xf0002000 0x1000>;
> +			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
> +			clock-names = "clk_uart";
> +			interrupts = <0 3 4>;
> +			status = "disabled";
> +		};
> +
> +		uart2: uart2@f0003000 {
> +			compatible = "nuvoton,npcm750-uart";
> +			reg = <0xf0003000 0x1000>;
> +			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
> +			clock-names = "clk_uart";
> +			interrupts = <0 4 4>;
> +			status = "disabled";
> +		};
> +
> +		uart3: uart3@f0004000 {
> +			compatible = "nuvoton,npcm750-uart";
> +			reg = <0xf0004000 0x1000>;
> +			clocks = <&clk NPCM7XX_CLK_UART_CORE>;
> +			clock-names = "clk_uart";
> +			interrupts = <0 5 4>;
> +			status = "disabled";
> +		};
> +	};
> +};
> diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
> new file mode 100644
> index 000000000000..c69d3bbf7e42
> --- /dev/null
> +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h
> @@ -0,0 +1,39 @@
> +/*
> + * Copyright (C) 2016 Nuvoton Technologies,  tali.perry-KrzQf0k3Iz9BDgjK7y7TUQ@public.gmane.org
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_NPCM7XX_H
> +#define _DT_BINDINGS_CLK_NPCM7XX_H
> +
> +#define NPCM7XX_CLK_PLL0	0
> +#define NPCM7XX_CLK_PLL1	1
> +#define NPCM7XX_CLK_PLL2	2
> +#define NPCM7XX_CLK_GFX		3
> +#define NPCM7XX_CLK_APB1	4
> +#define NPCM7XX_CLK_APB2	5
> +#define NPCM7XX_CLK_APB3	6
> +#define NPCM7XX_CLK_APB4	7
> +#define NPCM7XX_CLK_APB5	8
> +#define NPCM7XX_CLK_MC		9
> +#define NPCM7XX_CLK_CPU		10
> +#define NPCM7XX_CLK_SPI0	11
> +#define NPCM7XX_CLK_SPI3	12
> +#define NPCM7XX_CLK_SPIX	13
> +#define NPCM7XX_CLK_UART_CORE	14
> +#define NPCM7XX_CLK_TIMER	15
> +#define NPCM7XX_CLK_HOST_UART	16
> +#define NPCM7XX_CLK_MMC		17
> +#define NPCM7XX_CLK_SDHC	18
> +#define NPCM7XX_CLK_ADC		19
> +#define NPCM7XX_CLK_GFX_MEM	20
> +#define NPCM7XX_CLK_USB_BRIDGE	21
> +#define NPCM7XX_CLK_AXI		22
> +#define NPCM7XX_CLK_AHB		23
> +#define NPCM7XX_CLK_EMC		24
> +#define NPCM7XX_CLK_GMAC	25
> +
> +#endif
> -- 
> 2.14.1.480.gb18f417b89-goog
> 
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