From: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
To: Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Cyrille Pitchen
<cyrille.pitchen-yU5RGvR974pGWvitb5QawA@public.gmane.org>
Cc: David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>,
Brian Norris
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Boris Brezillon
<boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>,
linux-arm-kernel
<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
Subject: [RESEND PATCH v2 1/5] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
Date: Tue, 19 Sep 2017 16:26:01 +0530 [thread overview]
Message-ID: <20170919105605.18533-2-vigneshr@ti.com> (raw)
In-Reply-To: <20170919105605.18533-1-vigneshr-l0cyMroinI0@public.gmane.org>
Update binding documentation to add a new compatible for TI 66AK2G SoC,
to handle TI SoC specific quirks in the driver.
Signed-off-by: Vignesh R <vigneshr-l0cyMroinI0@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index f248056da24c..7dbe3bd9ac56 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -1,7 +1,9 @@
* Cadence Quad SPI controller
Required properties:
-- compatible : Should be "cdns,qspi-nor".
+- compatible : should be one of the following:
+ Generic default - "cdns,qspi-nor".
+ For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
--
2.14.1
--
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next prev parent reply other threads:[~2017-09-19 10:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-19 10:56 [RESEND PATCH v2 0/5] K2G: Add QSPI support Vignesh R
[not found] ` <20170919105605.18533-1-vigneshr-l0cyMroinI0@public.gmane.org>
2017-09-19 10:56 ` Vignesh R [this message]
2017-09-19 10:56 ` [RESEND PATCH v2 4/5] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit Vignesh R
2017-09-19 10:56 ` [RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Vignesh R
2017-09-22 8:04 ` kbuild test robot
2017-09-22 9:02 ` Vignesh R
2017-09-19 10:56 ` [RESEND PATCH v2 3/5] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit Vignesh R
2017-09-19 10:56 ` [RESEND PATCH v2 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support Vignesh R
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